1.\" $OpenBSD: mpfgpio.4,v 1.1 2022/02/18 10:51:43 visa Exp $ 2.\" 3.\" Copyright (c) 2022 Visa Hankala 4.\" 5.\" Permission to use, copy, modify, and distribute this software for any 6.\" purpose with or without fee is hereby granted, provided that the above 7.\" copyright notice and this permission notice appear in all copies. 8.\" 9.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16.\" 17.Dd $Mdocdate: February 18 2022 $ 18.Dt MPFGPIO 4 riscv64 19.Os 20.Sh NAME 21.Nm mpfgpio 22.Nd Microchip PolarFire SoC MSS GPIO controller 23.Sh SYNOPSIS 24.Cd "mpfgpio* at fdt?" 25.Cd "gpio* at mpfgpio?" 26.Sh DESCRIPTION 27The 28.Nm 29driver provides support for the Microchip PolarFire SoC MSS GPIO controller. 30.Pp 31The PolarFire SoC MSS has three GPIO units: 32.Dv GPIO_0 , 33.Dv GPIO_1 34and 35.Dv GPIO_2 . 36.Dv GPIO_0 37and 38.Dv GPIO_1 39control up to 14 and 24 IOs, respectively. 40These IOs are routed through IOMUXes. 41.Dv GPIO_2 42controls up to 32 IOs through the FPGA fabric. 43.Pp 44The IOs can be configured as either inputs or outputs, 45and accessed using 46.Xr gpioctl 8 . 47.Sh SEE ALSO 48.Xr gpio 4 , 49.Xr intro 4 , 50.Xr gpioctl 8 51.Sh HISTORY 52The 53.Nm 54driver first appeared in 55.Ox 7.1 . 56