1#!/usr/bin/env perl 2# 3# ==================================================================== 4# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL 5# project. The module is, however, dual licensed under OpenSSL and 6# CRYPTOGAMS licenses depending on where you obtain it. For further 7# details see http://www.openssl.org/~appro/cryptogams/. 8# ==================================================================== 9# 10# July 2004 11# 12# 2.22x RC4 tune-up:-) It should be noted though that my hand [as in 13# "hand-coded assembler"] doesn't stand for the whole improvement 14# coefficient. It turned out that eliminating RC4_CHAR from config 15# line results in ~40% improvement (yes, even for C implementation). 16# Presumably it has everything to do with AMD cache architecture and 17# RAW or whatever penalties. Once again! The module *requires* config 18# line *without* RC4_CHAR! As for coding "secret," I bet on partial 19# register arithmetics. For example instead of 'inc %r8; and $255,%r8' 20# I simply 'inc %r8b'. Even though optimization manual discourages 21# to operate on partial registers, it turned out to be the best bet. 22# At least for AMD... How IA32E would perform remains to be seen... 23 24# November 2004 25# 26# As was shown by Marc Bevand reordering of couple of load operations 27# results in even higher performance gain of 3.3x:-) At least on 28# Opteron... For reference, 1x in this case is RC4_CHAR C-code 29# compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock. 30# Latter means that if you want to *estimate* what to expect from 31# *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz. 32 33# November 2004 34# 35# Intel P4 EM64T core was found to run the AMD64 code really slow... 36# The only way to achieve comparable performance on P4 was to keep 37# RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to 38# compose blended code, which would perform even within 30% marginal 39# on either AMD and Intel platforms, I implement both cases. See 40# rc4_skey.c for further details... 41 42# April 2005 43# 44# P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing 45# those with add/sub results in 50% performance improvement of folded 46# loop... 47 48# May 2005 49# 50# As was shown by Zou Nanhai loop unrolling can improve Intel EM64T 51# performance by >30% [unlike P4 32-bit case that is]. But this is 52# provided that loads are reordered even more aggressively! Both code 53# pathes, AMD64 and EM64T, reorder loads in essentially same manner 54# as my IA-64 implementation. On Opteron this resulted in modest 5% 55# improvement [I had to test it], while final Intel P4 performance 56# achieves respectful 432MBps on 2.8GHz processor now. For reference. 57# If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than 58# RC4_INT code-path. While if executed on Opteron, it's only 25% 59# slower than the RC4_INT one [meaning that if CPU �-arch detection 60# is not implemented, then this final RC4_CHAR code-path should be 61# preferred, as it provides better *all-round* performance]. 62 63# March 2007 64# 65# Intel Core2 was observed to perform poorly on both code paths:-( It 66# apparently suffers from some kind of partial register stall, which 67# occurs in 64-bit mode only [as virtually identical 32-bit loop was 68# observed to outperform 64-bit one by almost 50%]. Adding two movzb to 69# cloop1 boosts its performance by 80%! This loop appears to be optimal 70# fit for Core2 and therefore the code was modified to skip cloop8 on 71# this CPU. 72 73# May 2010 74# 75# Intel Westmere was observed to perform suboptimally. Adding yet 76# another movzb to cloop1 improved performance by almost 50%! Core2 77# performance is improved too, but nominally... 78 79# May 2011 80# 81# The only code path that was not modified is P4-specific one. Non-P4 82# Intel code path optimization is heavily based on submission by Maxim 83# Perminov, Maxim Locktyukhin and Jim Guilford of Intel. I've used 84# some of the ideas even in attempt to optmize the original RC4_INT 85# code path... Current performance in cycles per processed byte (less 86# is better) and improvement coefficients relative to previous 87# version of this module are: 88# 89# Opteron 5.3/+0%(*) 90# P4 6.5 91# Core2 6.2/+15%(**) 92# Westmere 4.2/+60% 93# Sandy Bridge 4.2/+120% 94# Atom 9.3/+80% 95# 96# (*) But corresponding loop has less instructions, which should have 97# positive effect on upcoming Bulldozer, which has one less ALU. 98# For reference, Intel code runs at 6.8 cpb rate on Opteron. 99# (**) Note that Core2 result is ~15% lower than corresponding result 100# for 32-bit code, meaning that it's possible to improve it, 101# but more than likely at the cost of the others (see rc4-586.pl 102# to get the idea)... 103 104$flavour = shift; 105$output = shift; 106if ($flavour =~ /\./) { $output = $flavour; undef $flavour; } 107 108$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; 109( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or 110( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or 111die "can't locate x86_64-xlate.pl"; 112 113open OUT,"| \"$^X\" $xlate $flavour $output"; 114*STDOUT=*OUT; 115 116$dat="%rdi"; # arg1 117$len="%rsi"; # arg2 118$inp="%rdx"; # arg3 119$out="%rcx"; # arg4 120 121{ 122$code=<<___; 123.text 124.extern OPENSSL_ia32cap_P 125 126.globl RC4 127.type RC4,\@function,4 128.align 16 129RC4: or $len,$len 130 jne .Lentry 131 ret 132.Lentry: 133 push %rbx 134 push %r12 135 push %r13 136.Lprologue: 137 mov $len,%r11 138 mov $inp,%r12 139 mov $out,%r13 140___ 141my $len="%r11"; # reassign input arguments 142my $inp="%r12"; 143my $out="%r13"; 144 145my @XX=("%r10","%rsi"); 146my @TX=("%rax","%rbx"); 147my $YY="%rcx"; 148my $TY="%rdx"; 149 150$code.=<<___; 151 xor $XX[0],$XX[0] 152 xor $YY,$YY 153 154 lea 8($dat),$dat 155 mov -8($dat),$XX[0]#b 156 mov -4($dat),$YY#b 157 cmpl \$-1,256($dat) 158 je .LRC4_CHAR 159 mov OPENSSL_ia32cap_P(%rip),%r8d 160 xor $TX[1],$TX[1] 161 inc $XX[0]#b 162 sub $XX[0],$TX[1] 163 sub $inp,$out 164 movl ($dat,$XX[0],4),$TX[0]#d 165 test \$-16,$len 166 jz .Lloop1 167 bt \$30,%r8d # Intel CPU? 168 jc .Lintel 169 and \$7,$TX[1] 170 lea 1($XX[0]),$XX[1] 171 jz .Loop8 172 sub $TX[1],$len 173.Loop8_warmup: 174 add $TX[0]#b,$YY#b 175 movl ($dat,$YY,4),$TY#d 176 movl $TX[0]#d,($dat,$YY,4) 177 movl $TY#d,($dat,$XX[0],4) 178 add $TY#b,$TX[0]#b 179 inc $XX[0]#b 180 movl ($dat,$TX[0],4),$TY#d 181 movl ($dat,$XX[0],4),$TX[0]#d 182 xorb ($inp),$TY#b 183 movb $TY#b,($out,$inp) 184 lea 1($inp),$inp 185 dec $TX[1] 186 jnz .Loop8_warmup 187 188 lea 1($XX[0]),$XX[1] 189 jmp .Loop8 190.align 16 191.Loop8: 192___ 193for ($i=0;$i<8;$i++) { 194$code.=<<___ if ($i==7); 195 add \$8,$XX[1]#b 196___ 197$code.=<<___; 198 add $TX[0]#b,$YY#b 199 movl ($dat,$YY,4),$TY#d 200 movl $TX[0]#d,($dat,$YY,4) 201 movl `4*($i==7?-1:$i)`($dat,$XX[1],4),$TX[1]#d 202 ror \$8,%r8 # ror is redundant when $i=0 203 movl $TY#d,4*$i($dat,$XX[0],4) 204 add $TX[0]#b,$TY#b 205 movb ($dat,$TY,4),%r8b 206___ 207push(@TX,shift(@TX)); #push(@XX,shift(@XX)); # "rotate" registers 208} 209$code.=<<___; 210 add \$8,$XX[0]#b 211 ror \$8,%r8 212 sub \$8,$len 213 214 xor ($inp),%r8 215 mov %r8,($out,$inp) 216 lea 8($inp),$inp 217 218 test \$-8,$len 219 jnz .Loop8 220 cmp \$0,$len 221 jne .Lloop1 222 jmp .Lexit 223 224.align 16 225.Lintel: 226 test \$-32,$len 227 jz .Lloop1 228 and \$15,$TX[1] 229 jz .Loop16_is_hot 230 sub $TX[1],$len 231.Loop16_warmup: 232 add $TX[0]#b,$YY#b 233 movl ($dat,$YY,4),$TY#d 234 movl $TX[0]#d,($dat,$YY,4) 235 movl $TY#d,($dat,$XX[0],4) 236 add $TY#b,$TX[0]#b 237 inc $XX[0]#b 238 movl ($dat,$TX[0],4),$TY#d 239 movl ($dat,$XX[0],4),$TX[0]#d 240 xorb ($inp),$TY#b 241 movb $TY#b,($out,$inp) 242 lea 1($inp),$inp 243 dec $TX[1] 244 jnz .Loop16_warmup 245 246 mov $YY,$TX[1] 247 xor $YY,$YY 248 mov $TX[1]#b,$YY#b 249 250.Loop16_is_hot: 251 lea ($dat,$XX[0],4),$XX[1] 252___ 253sub RC4_loop { 254 my $i=shift; 255 my $j=$i<0?0:$i; 256 my $xmm="%xmm".($j&1); 257 258 $code.=" add \$16,$XX[0]#b\n" if ($i==15); 259 $code.=" movdqu ($inp),%xmm2\n" if ($i==15); 260 $code.=" add $TX[0]#b,$YY#b\n" if ($i<=0); 261 $code.=" movl ($dat,$YY,4),$TY#d\n"; 262 $code.=" pxor %xmm0,%xmm2\n" if ($i==0); 263 $code.=" psllq \$8,%xmm1\n" if ($i==0); 264 $code.=" pxor $xmm,$xmm\n" if ($i<=1); 265 $code.=" movl $TX[0]#d,($dat,$YY,4)\n"; 266 $code.=" add $TY#b,$TX[0]#b\n"; 267 $code.=" movl `4*($j+1)`($XX[1]),$TX[1]#d\n" if ($i<15); 268 $code.=" movz $TX[0]#b,$TX[0]#d\n"; 269 $code.=" movl $TY#d,4*$j($XX[1])\n"; 270 $code.=" pxor %xmm1,%xmm2\n" if ($i==0); 271 $code.=" lea ($dat,$XX[0],4),$XX[1]\n" if ($i==15); 272 $code.=" add $TX[1]#b,$YY#b\n" if ($i<15); 273 $code.=" pinsrw \$`($j>>1)&7`,($dat,$TX[0],4),$xmm\n"; 274 $code.=" movdqu %xmm2,($out,$inp)\n" if ($i==0); 275 $code.=" lea 16($inp),$inp\n" if ($i==0); 276 $code.=" movl ($XX[1]),$TX[1]#d\n" if ($i==15); 277} 278 RC4_loop(-1); 279$code.=<<___; 280 jmp .Loop16_enter 281.align 16 282.Loop16: 283___ 284 285for ($i=0;$i<16;$i++) { 286 $code.=".Loop16_enter:\n" if ($i==1); 287 RC4_loop($i); 288 push(@TX,shift(@TX)); # "rotate" registers 289} 290$code.=<<___; 291 mov $YY,$TX[1] 292 xor $YY,$YY # keyword to partial register 293 sub \$16,$len 294 mov $TX[1]#b,$YY#b 295 test \$-16,$len 296 jnz .Loop16 297 298 psllq \$8,%xmm1 299 pxor %xmm0,%xmm2 300 pxor %xmm1,%xmm2 301 movdqu %xmm2,($out,$inp) 302 lea 16($inp),$inp 303 304 cmp \$0,$len 305 jne .Lloop1 306 jmp .Lexit 307 308.align 16 309.Lloop1: 310 add $TX[0]#b,$YY#b 311 movl ($dat,$YY,4),$TY#d 312 movl $TX[0]#d,($dat,$YY,4) 313 movl $TY#d,($dat,$XX[0],4) 314 add $TY#b,$TX[0]#b 315 inc $XX[0]#b 316 movl ($dat,$TX[0],4),$TY#d 317 movl ($dat,$XX[0],4),$TX[0]#d 318 xorb ($inp),$TY#b 319 movb $TY#b,($out,$inp) 320 lea 1($inp),$inp 321 dec $len 322 jnz .Lloop1 323 jmp .Lexit 324 325.align 16 326.LRC4_CHAR: 327 add \$1,$XX[0]#b 328 movzb ($dat,$XX[0]),$TX[0]#d 329 test \$-8,$len 330 jz .Lcloop1 331 jmp .Lcloop8 332.align 16 333.Lcloop8: 334 mov ($inp),%r8d 335 mov 4($inp),%r9d 336___ 337# unroll 2x4-wise, because 64-bit rotates kill Intel P4... 338for ($i=0;$i<4;$i++) { 339$code.=<<___; 340 add $TX[0]#b,$YY#b 341 lea 1($XX[0]),$XX[1] 342 movzb ($dat,$YY),$TY#d 343 movzb $XX[1]#b,$XX[1]#d 344 movzb ($dat,$XX[1]),$TX[1]#d 345 movb $TX[0]#b,($dat,$YY) 346 cmp $XX[1],$YY 347 movb $TY#b,($dat,$XX[0]) 348 jne .Lcmov$i # Intel cmov is sloooow... 349 mov $TX[0],$TX[1] 350.Lcmov$i: 351 add $TX[0]#b,$TY#b 352 xor ($dat,$TY),%r8b 353 ror \$8,%r8d 354___ 355push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers 356} 357for ($i=4;$i<8;$i++) { 358$code.=<<___; 359 add $TX[0]#b,$YY#b 360 lea 1($XX[0]),$XX[1] 361 movzb ($dat,$YY),$TY#d 362 movzb $XX[1]#b,$XX[1]#d 363 movzb ($dat,$XX[1]),$TX[1]#d 364 movb $TX[0]#b,($dat,$YY) 365 cmp $XX[1],$YY 366 movb $TY#b,($dat,$XX[0]) 367 jne .Lcmov$i # Intel cmov is sloooow... 368 mov $TX[0],$TX[1] 369.Lcmov$i: 370 add $TX[0]#b,$TY#b 371 xor ($dat,$TY),%r9b 372 ror \$8,%r9d 373___ 374push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers 375} 376$code.=<<___; 377 lea -8($len),$len 378 mov %r8d,($out) 379 lea 8($inp),$inp 380 mov %r9d,4($out) 381 lea 8($out),$out 382 383 test \$-8,$len 384 jnz .Lcloop8 385 cmp \$0,$len 386 jne .Lcloop1 387 jmp .Lexit 388___ 389$code.=<<___; 390.align 16 391.Lcloop1: 392 add $TX[0]#b,$YY#b 393 movzb $YY#b,$YY#d 394 movzb ($dat,$YY),$TY#d 395 movb $TX[0]#b,($dat,$YY) 396 movb $TY#b,($dat,$XX[0]) 397 add $TX[0]#b,$TY#b 398 add \$1,$XX[0]#b 399 movzb $TY#b,$TY#d 400 movzb $XX[0]#b,$XX[0]#d 401 movzb ($dat,$TY),$TY#d 402 movzb ($dat,$XX[0]),$TX[0]#d 403 xorb ($inp),$TY#b 404 lea 1($inp),$inp 405 movb $TY#b,($out) 406 lea 1($out),$out 407 sub \$1,$len 408 jnz .Lcloop1 409 jmp .Lexit 410 411.align 16 412.Lexit: 413 sub \$1,$XX[0]#b 414 movl $XX[0]#d,-8($dat) 415 movl $YY#d,-4($dat) 416 417 mov (%rsp),%r13 418 mov 8(%rsp),%r12 419 mov 16(%rsp),%rbx 420 add \$24,%rsp 421.Lepilogue: 422 ret 423.size RC4,.-RC4 424___ 425} 426 427$idx="%r8"; 428$ido="%r9"; 429 430$code.=<<___; 431.globl RC4_set_key 432.type RC4_set_key,\@function,3 433.align 16 434RC4_set_key: 435 lea 8($dat),$dat 436 lea ($inp,$len),$inp 437 neg $len 438 mov $len,%rcx 439 xor %eax,%eax 440 xor $ido,$ido 441 xor %r10,%r10 442 xor %r11,%r11 443 444 mov OPENSSL_ia32cap_P(%rip),$idx#d 445 bt \$20,$idx#d # RC4_CHAR? 446 jc .Lc1stloop 447 jmp .Lw1stloop 448 449.align 16 450.Lw1stloop: 451 mov %eax,($dat,%rax,4) 452 add \$1,%al 453 jnc .Lw1stloop 454 455 xor $ido,$ido 456 xor $idx,$idx 457.align 16 458.Lw2ndloop: 459 mov ($dat,$ido,4),%r10d 460 add ($inp,$len,1),$idx#b 461 add %r10b,$idx#b 462 add \$1,$len 463 mov ($dat,$idx,4),%r11d 464 cmovz %rcx,$len 465 mov %r10d,($dat,$idx,4) 466 mov %r11d,($dat,$ido,4) 467 add \$1,$ido#b 468 jnc .Lw2ndloop 469 jmp .Lexit_key 470 471.align 16 472.Lc1stloop: 473 mov %al,($dat,%rax) 474 add \$1,%al 475 jnc .Lc1stloop 476 477 xor $ido,$ido 478 xor $idx,$idx 479.align 16 480.Lc2ndloop: 481 mov ($dat,$ido),%r10b 482 add ($inp,$len),$idx#b 483 add %r10b,$idx#b 484 add \$1,$len 485 mov ($dat,$idx),%r11b 486 jnz .Lcnowrap 487 mov %rcx,$len 488.Lcnowrap: 489 mov %r10b,($dat,$idx) 490 mov %r11b,($dat,$ido) 491 add \$1,$ido#b 492 jnc .Lc2ndloop 493 movl \$-1,256($dat) 494 495.align 16 496.Lexit_key: 497 xor %eax,%eax 498 mov %eax,-8($dat) 499 mov %eax,-4($dat) 500 ret 501.size RC4_set_key,.-RC4_set_key 502 503.globl RC4_options 504.type RC4_options,\@abi-omnipotent 505.align 16 506RC4_options: 507 lea .Lopts(%rip),%rax 508 mov OPENSSL_ia32cap_P(%rip),%edx 509 bt \$20,%edx 510 jc .L8xchar 511 bt \$30,%edx 512 jnc .Ldone 513 add \$25,%rax 514 ret 515.L8xchar: 516 add \$12,%rax 517.Ldone: 518 ret 519.align 64 520.Lopts: 521.asciz "rc4(8x,int)" 522.asciz "rc4(8x,char)" 523.asciz "rc4(16x,int)" 524.asciz "RC4 for x86_64, CRYPTOGAMS by <appro\@openssl.org>" 525.align 64 526.size RC4_options,.-RC4_options 527___ 528 529sub reg_part { 530my ($reg,$conv)=@_; 531 if ($reg =~ /%r[0-9]+/) { $reg .= $conv; } 532 elsif ($conv eq "b") { $reg =~ s/%[er]([^x]+)x?/%$1l/; } 533 elsif ($conv eq "w") { $reg =~ s/%[er](.+)/%$1/; } 534 elsif ($conv eq "d") { $reg =~ s/%[er](.+)/%e$1/; } 535 return $reg; 536} 537 538$code =~ s/(%[a-z0-9]+)#([bwd])/reg_part($1,$2)/gem; 539$code =~ s/\`([^\`]*)\`/eval $1/gem; 540 541print $code; 542 543close STDOUT; 544