1#!/usr/bin/env perl 2# 3# ==================================================================== 4# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL 5# project. The module is, however, dual licensed under OpenSSL and 6# CRYPTOGAMS licenses depending on where you obtain it. For further 7# details see http://www.openssl.org/~appro/cryptogams/. 8# ==================================================================== 9# 10# July 2004 11# 12# 2.22x RC4 tune-up:-) It should be noted though that my hand [as in 13# "hand-coded assembler"] doesn't stand for the whole improvement 14# coefficient. It turned out that eliminating RC4_CHAR from config 15# line results in ~40% improvement (yes, even for C implementation). 16# Presumably it has everything to do with AMD cache architecture and 17# RAW or whatever penalties. Once again! The module *requires* config 18# line *without* RC4_CHAR! As for coding "secret," I bet on partial 19# register arithmetics. For example instead of 'inc %r8; and $255,%r8' 20# I simply 'inc %r8b'. Even though optimization manual discourages 21# to operate on partial registers, it turned out to be the best bet. 22# At least for AMD... How IA32E would perform remains to be seen... 23 24# November 2004 25# 26# As was shown by Marc Bevand reordering of couple of load operations 27# results in even higher performance gain of 3.3x:-) At least on 28# Opteron... For reference, 1x in this case is RC4_CHAR C-code 29# compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock. 30# Latter means that if you want to *estimate* what to expect from 31# *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz. 32 33# November 2004 34# 35# Intel P4 EM64T core was found to run the AMD64 code really slow... 36# The only way to achieve comparable performance on P4 was to keep 37# RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to 38# compose blended code, which would perform even within 30% marginal 39# on either AMD and Intel platforms, I implement both cases. See 40# rc4_skey.c for further details... 41 42# April 2005 43# 44# P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing 45# those with add/sub results in 50% performance improvement of folded 46# loop... 47 48# May 2005 49# 50# As was shown by Zou Nanhai loop unrolling can improve Intel EM64T 51# performance by >30% [unlike P4 32-bit case that is]. But this is 52# provided that loads are reordered even more aggressively! Both code 53# paths, AMD64 and EM64T, reorder loads in essentially same manner 54# as my IA-64 implementation. On Opteron this resulted in modest 5% 55# improvement [I had to test it], while final Intel P4 performance 56# achieves respectful 432MBps on 2.8GHz processor now. For reference. 57# If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than 58# RC4_INT code-path. While if executed on Opteron, it's only 25% 59# slower than the RC4_INT one [meaning that if CPU �-arch detection 60# is not implemented, then this final RC4_CHAR code-path should be 61# preferred, as it provides better *all-round* performance]. 62 63# March 2007 64# 65# Intel Core2 was observed to perform poorly on both code paths:-( It 66# apparently suffers from some kind of partial register stall, which 67# occurs in 64-bit mode only [as virtually identical 32-bit loop was 68# observed to outperform 64-bit one by almost 50%]. Adding two movzb to 69# cloop1 boosts its performance by 80%! This loop appears to be optimal 70# fit for Core2 and therefore the code was modified to skip cloop8 on 71# this CPU. 72 73# May 2010 74# 75# Intel Westmere was observed to perform suboptimally. Adding yet 76# another movzb to cloop1 improved performance by almost 50%! Core2 77# performance is improved too, but nominally... 78 79# May 2011 80# 81# The only code path that was not modified is P4-specific one. Non-P4 82# Intel code path optimization is heavily based on submission by Maxim 83# Perminov, Maxim Locktyukhin and Jim Guilford of Intel. I've used 84# some of the ideas even in attempt to optimize the original RC4_INT 85# code path... Current performance in cycles per processed byte (less 86# is better) and improvement coefficients relative to previous 87# version of this module are: 88# 89# Opteron 5.3/+0%(*) 90# P4 6.5 91# Core2 6.2/+15%(**) 92# Westmere 4.2/+60% 93# Sandy Bridge 4.2/+120% 94# Atom 9.3/+80% 95# 96# (*) But corresponding loop has less instructions, which should have 97# positive effect on upcoming Bulldozer, which has one less ALU. 98# For reference, Intel code runs at 6.8 cpb rate on Opteron. 99# (**) Note that Core2 result is ~15% lower than corresponding result 100# for 32-bit code, meaning that it's possible to improve it, 101# but more than likely at the cost of the others (see rc4-586.pl 102# to get the idea)... 103 104$flavour = shift; 105$output = shift; 106if ($flavour =~ /\./) { $output = $flavour; undef $flavour; } 107 108$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; 109( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or 110( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or 111die "can't locate x86_64-xlate.pl"; 112 113open OUT,"| \"$^X\" $xlate $flavour $output"; 114*STDOUT=*OUT; 115 116$dat="%rdi"; # arg1 117$len="%rsi"; # arg2 118$inp="%rdx"; # arg3 119$out="%rcx"; # arg4 120 121{ 122$code=<<___; 123.text 124.extern OPENSSL_ia32cap_P 125.hidden OPENSSL_ia32cap_P 126 127.globl rc4_internal 128.type rc4_internal,\@function,4 129.align 16 130rc4_internal: 131 _CET_ENDBR 132 or $len,$len 133 jne .Lentry 134 ret 135.Lentry: 136 push %rbx 137 push %r12 138 push %r13 139.Lprologue: 140 mov $len,%r11 141 mov $inp,%r12 142 mov $out,%r13 143___ 144my $len="%r11"; # reassign input arguments 145my $inp="%r12"; 146my $out="%r13"; 147 148my @XX=("%r10","%rsi"); 149my @TX=("%rax","%rbx"); 150my $YY="%rcx"; 151my $TY="%rdx"; 152 153$code.=<<___; 154 xor $XX[0],$XX[0] 155 xor $YY,$YY 156 157 lea 8($dat),$dat 158 mov -8($dat),$XX[0]#b 159 mov -4($dat),$YY#b 160 cmpl \$-1,256($dat) 161 je .LRC4_CHAR 162 mov OPENSSL_ia32cap_P(%rip),%r8d 163 xor $TX[1],$TX[1] 164 inc $XX[0]#b 165 sub $XX[0],$TX[1] 166 sub $inp,$out 167 movl ($dat,$XX[0],4),$TX[0]#d 168 test \$-16,$len 169 jz .Lloop1 170 bt \$IA32CAP_BIT0_INTEL,%r8d # Intel CPU? 171 jc .Lintel 172 and \$7,$TX[1] 173 lea 1($XX[0]),$XX[1] 174 jz .Loop8 175 sub $TX[1],$len 176.Loop8_warmup: 177 add $TX[0]#b,$YY#b 178 movl ($dat,$YY,4),$TY#d 179 movl $TX[0]#d,($dat,$YY,4) 180 movl $TY#d,($dat,$XX[0],4) 181 add $TY#b,$TX[0]#b 182 inc $XX[0]#b 183 movl ($dat,$TX[0],4),$TY#d 184 movl ($dat,$XX[0],4),$TX[0]#d 185 xorb ($inp),$TY#b 186 movb $TY#b,($out,$inp) 187 lea 1($inp),$inp 188 dec $TX[1] 189 jnz .Loop8_warmup 190 191 lea 1($XX[0]),$XX[1] 192 jmp .Loop8 193.align 16 194.Loop8: 195___ 196for ($i=0;$i<8;$i++) { 197$code.=<<___ if ($i==7); 198 add \$8,$XX[1]#b 199___ 200$code.=<<___; 201 add $TX[0]#b,$YY#b 202 movl ($dat,$YY,4),$TY#d 203 movl $TX[0]#d,($dat,$YY,4) 204 movl `4*($i==7?-1:$i)`($dat,$XX[1],4),$TX[1]#d 205 ror \$8,%r8 # ror is redundant when $i=0 206 movl $TY#d,4*$i($dat,$XX[0],4) 207 add $TX[0]#b,$TY#b 208 movb ($dat,$TY,4),%r8b 209___ 210push(@TX,shift(@TX)); #push(@XX,shift(@XX)); # "rotate" registers 211} 212$code.=<<___; 213 add \$8,$XX[0]#b 214 ror \$8,%r8 215 sub \$8,$len 216 217 xor ($inp),%r8 218 mov %r8,($out,$inp) 219 lea 8($inp),$inp 220 221 test \$-8,$len 222 jnz .Loop8 223 cmp \$0,$len 224 jne .Lloop1 225 jmp .Lexit 226 227.align 16 228.Lintel: 229 test \$-32,$len 230 jz .Lloop1 231 and \$15,$TX[1] 232 jz .Loop16_is_hot 233 sub $TX[1],$len 234.Loop16_warmup: 235 add $TX[0]#b,$YY#b 236 movl ($dat,$YY,4),$TY#d 237 movl $TX[0]#d,($dat,$YY,4) 238 movl $TY#d,($dat,$XX[0],4) 239 add $TY#b,$TX[0]#b 240 inc $XX[0]#b 241 movl ($dat,$TX[0],4),$TY#d 242 movl ($dat,$XX[0],4),$TX[0]#d 243 xorb ($inp),$TY#b 244 movb $TY#b,($out,$inp) 245 lea 1($inp),$inp 246 dec $TX[1] 247 jnz .Loop16_warmup 248 249 mov $YY,$TX[1] 250 xor $YY,$YY 251 mov $TX[1]#b,$YY#b 252 253.Loop16_is_hot: 254 lea ($dat,$XX[0],4),$XX[1] 255___ 256sub RC4_loop { 257 my $i=shift; 258 my $j=$i<0?0:$i; 259 my $xmm="%xmm".($j&1); 260 261 $code.=" add \$16,$XX[0]#b\n" if ($i==15); 262 $code.=" movdqu ($inp),%xmm2\n" if ($i==15); 263 $code.=" add $TX[0]#b,$YY#b\n" if ($i<=0); 264 $code.=" movl ($dat,$YY,4),$TY#d\n"; 265 $code.=" pxor %xmm0,%xmm2\n" if ($i==0); 266 $code.=" psllq \$8,%xmm1\n" if ($i==0); 267 $code.=" pxor $xmm,$xmm\n" if ($i<=1); 268 $code.=" movl $TX[0]#d,($dat,$YY,4)\n"; 269 $code.=" add $TY#b,$TX[0]#b\n"; 270 $code.=" movl `4*($j+1)`($XX[1]),$TX[1]#d\n" if ($i<15); 271 $code.=" movz $TX[0]#b,$TX[0]#d\n"; 272 $code.=" movl $TY#d,4*$j($XX[1])\n"; 273 $code.=" pxor %xmm1,%xmm2\n" if ($i==0); 274 $code.=" lea ($dat,$XX[0],4),$XX[1]\n" if ($i==15); 275 $code.=" add $TX[1]#b,$YY#b\n" if ($i<15); 276 $code.=" pinsrw \$`($j>>1)&7`,($dat,$TX[0],4),$xmm\n"; 277 $code.=" movdqu %xmm2,($out,$inp)\n" if ($i==0); 278 $code.=" lea 16($inp),$inp\n" if ($i==0); 279 $code.=" movl ($XX[1]),$TX[1]#d\n" if ($i==15); 280} 281 RC4_loop(-1); 282$code.=<<___; 283 jmp .Loop16_enter 284.align 16 285.Loop16: 286___ 287 288for ($i=0;$i<16;$i++) { 289 $code.=".Loop16_enter:\n" if ($i==1); 290 RC4_loop($i); 291 push(@TX,shift(@TX)); # "rotate" registers 292} 293$code.=<<___; 294 mov $YY,$TX[1] 295 xor $YY,$YY # keyword to partial register 296 sub \$16,$len 297 mov $TX[1]#b,$YY#b 298 test \$-16,$len 299 jnz .Loop16 300 301 psllq \$8,%xmm1 302 pxor %xmm0,%xmm2 303 pxor %xmm1,%xmm2 304 movdqu %xmm2,($out,$inp) 305 lea 16($inp),$inp 306 307 cmp \$0,$len 308 jne .Lloop1 309 jmp .Lexit 310 311.align 16 312.Lloop1: 313 add $TX[0]#b,$YY#b 314 movl ($dat,$YY,4),$TY#d 315 movl $TX[0]#d,($dat,$YY,4) 316 movl $TY#d,($dat,$XX[0],4) 317 add $TY#b,$TX[0]#b 318 inc $XX[0]#b 319 movl ($dat,$TX[0],4),$TY#d 320 movl ($dat,$XX[0],4),$TX[0]#d 321 xorb ($inp),$TY#b 322 movb $TY#b,($out,$inp) 323 lea 1($inp),$inp 324 dec $len 325 jnz .Lloop1 326 jmp .Lexit 327 328.align 16 329.LRC4_CHAR: 330 add \$1,$XX[0]#b 331 movzb ($dat,$XX[0]),$TX[0]#d 332 test \$-8,$len 333 jz .Lcloop1 334 jmp .Lcloop8 335.align 16 336.Lcloop8: 337 mov ($inp),%r8d 338 mov 4($inp),%r9d 339___ 340# unroll 2x4-wise, because 64-bit rotates kill Intel P4... 341for ($i=0;$i<4;$i++) { 342$code.=<<___; 343 add $TX[0]#b,$YY#b 344 lea 1($XX[0]),$XX[1] 345 movzb ($dat,$YY),$TY#d 346 movzb $XX[1]#b,$XX[1]#d 347 movzb ($dat,$XX[1]),$TX[1]#d 348 movb $TX[0]#b,($dat,$YY) 349 cmp $XX[1],$YY 350 movb $TY#b,($dat,$XX[0]) 351 jne .Lcmov$i # Intel cmov is sloooow... 352 mov $TX[0],$TX[1] 353.Lcmov$i: 354 add $TX[0]#b,$TY#b 355 xor ($dat,$TY),%r8b 356 ror \$8,%r8d 357___ 358push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers 359} 360for ($i=4;$i<8;$i++) { 361$code.=<<___; 362 add $TX[0]#b,$YY#b 363 lea 1($XX[0]),$XX[1] 364 movzb ($dat,$YY),$TY#d 365 movzb $XX[1]#b,$XX[1]#d 366 movzb ($dat,$XX[1]),$TX[1]#d 367 movb $TX[0]#b,($dat,$YY) 368 cmp $XX[1],$YY 369 movb $TY#b,($dat,$XX[0]) 370 jne .Lcmov$i # Intel cmov is sloooow... 371 mov $TX[0],$TX[1] 372.Lcmov$i: 373 add $TX[0]#b,$TY#b 374 xor ($dat,$TY),%r9b 375 ror \$8,%r9d 376___ 377push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers 378} 379$code.=<<___; 380 lea -8($len),$len 381 mov %r8d,($out) 382 lea 8($inp),$inp 383 mov %r9d,4($out) 384 lea 8($out),$out 385 386 test \$-8,$len 387 jnz .Lcloop8 388 cmp \$0,$len 389 jne .Lcloop1 390 jmp .Lexit 391___ 392$code.=<<___; 393.align 16 394.Lcloop1: 395 add $TX[0]#b,$YY#b 396 movzb $YY#b,$YY#d 397 movzb ($dat,$YY),$TY#d 398 movb $TX[0]#b,($dat,$YY) 399 movb $TY#b,($dat,$XX[0]) 400 add $TX[0]#b,$TY#b 401 add \$1,$XX[0]#b 402 movzb $TY#b,$TY#d 403 movzb $XX[0]#b,$XX[0]#d 404 movzb ($dat,$TY),$TY#d 405 movzb ($dat,$XX[0]),$TX[0]#d 406 xorb ($inp),$TY#b 407 lea 1($inp),$inp 408 movb $TY#b,($out) 409 lea 1($out),$out 410 sub \$1,$len 411 jnz .Lcloop1 412 jmp .Lexit 413 414.align 16 415.Lexit: 416 sub \$1,$XX[0]#b 417 movl $XX[0]#d,-8($dat) 418 movl $YY#d,-4($dat) 419 420 mov (%rsp),%r13 421 mov 8(%rsp),%r12 422 mov 16(%rsp),%rbx 423 add \$24,%rsp 424.Lepilogue: 425 ret 426.size rc4_internal,.-rc4_internal 427___ 428} 429 430$idx="%r8"; 431$ido="%r9"; 432 433$code.=<<___; 434.globl rc4_set_key_internal 435.type rc4_set_key_internal,\@function,3 436.align 16 437rc4_set_key_internal: 438 _CET_ENDBR 439 lea 8($dat),$dat 440 lea ($inp,$len),$inp 441 neg $len 442 mov $len,%rcx 443 xor %eax,%eax 444 xor $ido,$ido 445 xor %r10,%r10 446 xor %r11,%r11 447 448 mov OPENSSL_ia32cap_P(%rip),$idx#d 449 bt \$IA32CAP_BIT0_INTELP4,$idx#d # RC4_CHAR? 450 jc .Lc1stloop 451 jmp .Lw1stloop 452 453.align 16 454.Lw1stloop: 455 mov %eax,($dat,%rax,4) 456 add \$1,%al 457 jnc .Lw1stloop 458 459 xor $ido,$ido 460 xor $idx,$idx 461.align 16 462.Lw2ndloop: 463 mov ($dat,$ido,4),%r10d 464 add ($inp,$len,1),$idx#b 465 add %r10b,$idx#b 466 add \$1,$len 467 mov ($dat,$idx,4),%r11d 468 cmovz %rcx,$len 469 mov %r10d,($dat,$idx,4) 470 mov %r11d,($dat,$ido,4) 471 add \$1,$ido#b 472 jnc .Lw2ndloop 473 jmp .Lexit_key 474 475.align 16 476.Lc1stloop: 477 mov %al,($dat,%rax) 478 add \$1,%al 479 jnc .Lc1stloop 480 481 xor $ido,$ido 482 xor $idx,$idx 483.align 16 484.Lc2ndloop: 485 mov ($dat,$ido),%r10b 486 add ($inp,$len),$idx#b 487 add %r10b,$idx#b 488 add \$1,$len 489 mov ($dat,$idx),%r11b 490 jnz .Lcnowrap 491 mov %rcx,$len 492.Lcnowrap: 493 mov %r10b,($dat,$idx) 494 mov %r11b,($dat,$ido) 495 add \$1,$ido#b 496 jnc .Lc2ndloop 497 movl \$-1,256($dat) 498 499.align 16 500.Lexit_key: 501 xor %eax,%eax 502 mov %eax,-8($dat) 503 mov %eax,-4($dat) 504 ret 505.size rc4_set_key_internal,.-rc4_set_key_internal 506___ 507 508sub reg_part { 509my ($reg,$conv)=@_; 510 if ($reg =~ /%r[0-9]+/) { $reg .= $conv; } 511 elsif ($conv eq "b") { $reg =~ s/%[er]([^x]+)x?/%$1l/; } 512 elsif ($conv eq "w") { $reg =~ s/%[er](.+)/%$1/; } 513 elsif ($conv eq "d") { $reg =~ s/%[er](.+)/%e$1/; } 514 return $reg; 515} 516 517$code =~ s/(%[a-z0-9]+)#([bwd])/reg_part($1,$2)/gem; 518$code =~ s/\`([^\`]*)\`/eval $1/gem; 519 520print $code; 521 522close STDOUT; 523