1; Options for the SH port of the compiler. 2 3; Copyright (C) 2005 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 2, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15; for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING. If not, write to the Free 19; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 20; 02110-1301, USA. 21 22;; Used for various architecture options. 23Mask(SH_E) 24 25;; Set if the default precision of th FPU is single. 26Mask(FPU_SINGLE) 27 28;; Set if we should generate code using type 2A insns. 29Mask(HARD_SH2A) 30 31;; Set if we should generate code using type 2A DF insns. 32Mask(HARD_SH2A_DOUBLE) 33 34;; Set if compiling for SH4 hardware (to be used for insn costs etc.) 35Mask(HARD_SH4) 36 37;; Set if we should generate code for a SH5 CPU (either ISA). 38Mask(SH5) 39 40;; Set if we should save all target registers. 41Mask(SAVE_ALL_TARGET_REGS) 42 43m1 44Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1) 45Generate SH1 code 46 47m2 48Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2) 49Generate SH2 code 50 51m2a 52Target RejectNegative Condition(SUPPORT_SH2A) 53Generate SH2a code 54 55m2a-nofpu 56Target RejectNegative Condition(SUPPORT_SH2A_NOFPU) 57Generate SH2a FPU-less code 58 59m2a-single 60Target RejectNegative Condition (SUPPORT_SH2A_SINGLE) 61Generate default single-precision SH2a code 62 63m2a-single-only 64Target RejectNegative Condition (SUPPORT_SH2A_SINGLE_ONLY) 65Generate only single-precision SH2a code 66 67m2e 68Target RejectNegative Condition(SUPPORT_SH2E) 69Generate SH2e code 70 71m3 72Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) 73Generate SH3 code 74 75m3e 76Target RejectNegative Condition(SUPPORT_SH3E) 77Generate SH3e code 78 79m4 80Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4) 81Generate SH4 code 82 83m4-100 84Target RejectNegative Condition(SUPPORT_SH4) 85Generate SH4-100 code 86 87m4-200 88Target RejectNegative Condition(SUPPORT_SH4) 89Generate SH4-200 code 90 91m4-nofpu 92Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 93Generate SH4 FPU-less code 94 95m4-400 96Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 97Generate code for SH4 400 series (MMU/FPU-less) 98;; passes -isa=sh4-nommu-nofpu to the assembler. 99 100m4-500 101Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 102Generate code for SH4 500 series (FPU-less). 103;; passes -isa=sh4-nofpu to the assembler. 104 105m4-single 106Target RejectNegative Condition(SUPPORT_SH4_SINGLE) 107Generate default single-precision SH4 code 108 109m4-100-single 110Target RejectNegative Condition(SUPPORT_SH4_SINGLE) 111Generate default single-precision SH4-100 code 112 113m4-200-single 114Target RejectNegative Condition(SUPPORT_SH4_SINGLE) 115Generate default single-precision SH4-200 code 116 117m4-single-only 118Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) 119Generate only single-precision SH4 code 120 121m4-100-single-only 122Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) 123Generate only single-precision SH4-100 code 124 125m4-200-single-only 126Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) 127Generate only single-precision SH4-200 code 128 129m4a 130Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A) 131Generate SH4a code 132 133m4a-nofpu 134Target RejectNegative Condition(SUPPORT_SH4A_NOFPU) 135Generate SH4a FPU-less code 136 137m4a-single 138Target RejectNegative Condition(SUPPORT_SH4A_SINGLE) 139Generate default single-precision SH4a code 140 141m4a-single-only 142Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY) 143Generate only single-precision SH4a code 144 145m4al 146Target RejectNegative Condition(SUPPORT_SH4AL) 147Generate SH4al-dsp code 148 149m5-32media 150Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) 151Generate 32-bit SHmedia code 152 153m5-32media-nofpu 154Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) 155Generate 32-bit FPU-less SHmedia code 156 157m5-64media 158Target RejectNegative Condition(SUPPORT_SH5_64MEDIA) 159Generate 64-bit SHmedia code 160 161m5-64media-nofpu 162Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU) 163Generate 64-bit FPU-less SHmedia code 164 165m5-compact 166Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) 167Generate SHcompact code 168 169m5-compact-nofpu 170Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) 171Generate FPU-less SHcompact code 172 173madjust-unroll 174Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5) 175Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this 176 177mb 178Target Report RejectNegative InverseMask(LITTLE_ENDIAN) 179Generate code in big endian mode 180 181mbigtable 182Target Report RejectNegative Mask(BIGTABLE) 183Generate 32-bit offsets in switch tables 184 185mcut2-workaround 186Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND) 187Enable SH5 cut2 workaround 188 189mdalign 190Target Report RejectNegative Mask(ALIGN_DOUBLE) 191Align doubles at 64-bit boundaries 192 193mdiv= 194Target RejectNegative Joined Var(sh_div_str) Init("") 195Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp 196 197mdivsi3_libfunc= 198Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") 199Specify name for 32 bit signed division function 200 201mfmovd 202Target RejectNegative Mask(FMOVD) Undocumented 203 204mgettrcost= 205Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1) 206Cost to assume for gettr insn 207 208mhitachi 209Target Report RejectNegative Mask(HITACHI) 210Follow Renesas (formerly Hitachi) / SuperH calling conventions 211 212mieee 213Target Report Mask(IEEE) 214Increase the IEEE compliance for floating-point code 215 216mindexed-addressing 217Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA) 218Enable the use of the indexed addressing mode for SHmedia32/SHcompact 219 220minvalid-symbols 221Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5) 222Assume symbols might be invalid 223 224misize 225Target Report RejectNegative Mask(DUMPISIZE) 226Annotate assembler instructions with estimated addresses 227 228ml 229Target Report RejectNegative Mask(LITTLE_ENDIAN) 230Generate code in little endian mode 231 232mnomacsave 233Target Report RejectNegative Mask(NOMACSAVE) 234Mark MAC register as call-clobbered 235 236;; ??? This option is not useful, but is retained in case there are people 237;; who are still relying on it. It may be deleted in the future. 238mpadstruct 239Target Report RejectNegative Mask(PADSTRUCT) 240Make structs a multiple of 4 bytes (warning: ABI altered) 241 242mprefergot 243Target Report RejectNegative Mask(PREFERGOT) 244Emit function-calls using global offset table when generating PIC 245 246mpt-fixed 247Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5) 248Assume pt* instructions won't trap 249 250mrelax 251Target Report RejectNegative Mask(RELAX) 252Shorten address references during linking 253 254mrenesas 255Target Mask(HITACHI) MaskExists 256Follow Renesas (formerly Hitachi) / SuperH calling conventions 257 258mspace 259Target Report RejectNegative Mask(SMALLCODE) 260Deprecated. Use -Os instead 261 262multcost= 263Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1) 264Cost to assume for a multiply insn 265 266musermode 267Target Report RejectNegative Mask(USERMODE) 268Generate library function call to invalidate instruction cache entries after fixing trampoline 269 270;; We might want to enable this by default for TARGET_HARD_SH4, because 271;; zero-offset branches have zero latency. Needs some benchmarking. 272mpretend-cmove 273Target Var(TARGET_PRETEND_CMOVE) 274Pretend a branch-around-a-move is a conditional move. 275