1 /* Definitions of target machine for GNU compiler. 2 Motorola 68HC11 and 68HC12. 3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 4 Free Software Foundation, Inc. 5 Contributed by Stephane Carrez (stcarrez@nerim.fr) 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2, or (at your option) 12 any later version. 13 14 GCC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING. If not, write to 21 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 22 Boston, MA 02110-1301, USA. 23 24 Note: 25 A first 68HC11 port was made by Otto Lind (otto@coactive.com) 26 on gcc 2.6.3. I have used it as a starting point for this port. 27 However, this new port is a complete re-write. Its internal 28 design is completely different. The generated code is not 29 compatible with the gcc 2.6.3 port. 30 31 The gcc 2.6.3 port is available at: 32 33 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz 34 35 */ 36 37 /***************************************************************************** 38 ** 39 ** Controlling the Compilation Driver, `gcc' 40 ** 41 *****************************************************************************/ 42 43 #undef ENDFILE_SPEC 44 45 /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */ 46 #ifndef ASM_SPEC 47 #define ASM_SPEC \ 48 "%{m68hc12:-m68hc12}" \ 49 "%{m68hcs12:-m68hcs12}" \ 50 "%{!m68hc12:%{!m68hcs12:-m68hc11}} " \ 51 "%{mshort:-mshort}%{!mshort:-mlong} " \ 52 "%{fshort-double:-mshort-double}%{!fshort-double:-mlong-double}" 53 #endif 54 55 /* We need to tell the linker the target elf format. Just pass an 56 emulation option. This can be overridden by -Wl option of gcc. */ 57 #ifndef LINK_SPEC 58 #define LINK_SPEC \ 59 "%{m68hc12:-m m68hc12elf}" \ 60 "%{m68hcs12:-m m68hc12elf}" \ 61 "%{!m68hc12:%{!m68hcs12:-m m68hc11elf}} " \ 62 "%{!mnorelax:%{!m68hc12:%{!m68hcs12:-relax}}}" 63 #endif 64 65 #ifndef LIB_SPEC 66 #define LIB_SPEC "" 67 #endif 68 69 #ifndef CC1_SPEC 70 #define CC1_SPEC "" 71 #endif 72 73 #ifndef CPP_SPEC 74 #define CPP_SPEC \ 75 "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\ 76 %{!mshort:-D__INT__=32}\ 77 %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\ 78 %{m68hcs12:-Dmc6812 -DMC6812 -Dmc68hcs12}\ 79 %{!m68hc12:%{!m68hcs12:-Dmc6811 -DMC6811 -Dmc68hc11}}\ 80 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}\ 81 %{mlong-calls:-D__USE_RTC__}" 82 #endif 83 84 #undef STARTFILE_SPEC 85 #define STARTFILE_SPEC "crt1%O%s" 86 87 /* Names to predefine in the preprocessor for this target machine. */ 88 #define TARGET_CPU_CPP_BUILTINS() \ 89 do \ 90 { \ 91 builtin_define_std ("mc68hc1x"); \ 92 } \ 93 while (0) 94 95 /* As an embedded target, we have no libc. */ 96 #ifndef inhibit_libc 97 # define inhibit_libc 98 #endif 99 100 /* Forward type declaration for prototypes definitions. 101 rtx_ptr is equivalent to rtx. Can't use the same name. */ 102 struct rtx_def; 103 typedef struct rtx_def *rtx_ptr; 104 105 union tree_node; 106 typedef union tree_node *tree_ptr; 107 108 /* We can't declare enum machine_mode forward nor include 'machmode.h' here. 109 Prototypes defined here will use an int instead. It's better than no 110 prototype at all. */ 111 typedef int enum_machine_mode; 112 113 /***************************************************************************** 114 ** 115 ** Run-time Target Specification 116 ** 117 *****************************************************************************/ 118 119 /* Run-time compilation parameters selecting different hardware subsets. */ 120 121 extern short *reg_renumber; /* def in local_alloc.c */ 122 123 #define TARGET_OP_TIME (optimize && optimize_size == 0) 124 #define TARGET_RELAX (TARGET_NO_DIRECT_MODE) 125 126 /* Default target_flags if no switches specified. */ 127 #ifndef TARGET_DEFAULT 128 # define TARGET_DEFAULT 0 129 #endif 130 131 /* Define this macro as a C expression for the initializer of an 132 array of string to tell the driver program which options are 133 defaults for this target and thus do not need to be handled 134 specially when using `MULTILIB_OPTIONS'. */ 135 #ifndef MULTILIB_DEFAULTS 136 # if TARGET_DEFAULT & MASK_M6811 137 # define MULTILIB_DEFAULTS { "m68hc11" } 138 # else 139 # define MULTILIB_DEFAULTS { "m68hc12" } 140 # endif 141 #endif 142 143 /* Print subsidiary information on the compiler version in use. */ 144 #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12/MC68HCS12)") 145 146 /* Sometimes certain combinations of command options do not make 147 sense on a particular target machine. You can define a macro 148 `OVERRIDE_OPTIONS' to take account of this. This macro, if 149 defined, is executed once just after all the command options have 150 been parsed. 151 152 Don't use this macro to turn on various extra optimizations for 153 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 154 155 #define OVERRIDE_OPTIONS m68hc11_override_options (); 156 157 158 /* Define cost parameters for a given processor variant. */ 159 struct processor_costs { 160 const int add; /* cost of an add instruction */ 161 const int logical; /* cost of a logical instruction */ 162 const int shift_var; 163 const int shiftQI_const[8]; 164 const int shiftHI_const[16]; 165 const int multQI; 166 const int multHI; 167 const int multSI; 168 const int divQI; 169 const int divHI; 170 const int divSI; 171 }; 172 173 /* Costs for the current processor. */ 174 extern const struct processor_costs *m68hc11_cost; 175 176 177 /* target machine storage layout */ 178 179 /* Define this if most significant byte of a word is the lowest numbered. */ 180 #define BYTES_BIG_ENDIAN 1 181 182 /* Define this if most significant bit is lowest numbered 183 in instructions that operate on numbered bit-fields. */ 184 #define BITS_BIG_ENDIAN 0 185 186 /* Define this if most significant word of a multiword number is numbered. */ 187 #define WORDS_BIG_ENDIAN 1 188 189 /* Width of a word, in units (bytes). */ 190 #define UNITS_PER_WORD 2 191 192 /* Definition of size_t. This is really an unsigned short as the 193 68hc11 only handles a 64K address space. */ 194 #define SIZE_TYPE "short unsigned int" 195 196 /* A C expression for a string describing the name of the data type 197 to use for the result of subtracting two pointers. The typedef 198 name `ptrdiff_t' is defined using the contents of the string. 199 The 68hc11 only has a 64K address space. */ 200 #define PTRDIFF_TYPE "short int" 201 202 /* Allocation boundary (bits) for storing pointers in memory. */ 203 #define POINTER_BOUNDARY 8 204 205 /* Normal alignment required for function parameters on the stack, in bits. 206 This can't be less than BITS_PER_WORD */ 207 #define PARM_BOUNDARY (BITS_PER_WORD) 208 209 /* Boundary (bits) on which stack pointer should be aligned. */ 210 #define STACK_BOUNDARY 8 211 212 /* Allocation boundary (bits) for the code of a function. */ 213 #define FUNCTION_BOUNDARY 8 214 215 #define BIGGEST_ALIGNMENT 8 216 217 /* Alignment of field after `int : 0' in a structure. */ 218 #define EMPTY_FIELD_BOUNDARY 8 219 220 /* Every structure's size must be a multiple of this. */ 221 #define STRUCTURE_SIZE_BOUNDARY 8 222 223 /* Define this if instructions will fail to work if given data not 224 on the nominal alignment. If instructions will merely go slower 225 in that case, do not define this macro. */ 226 #define STRICT_ALIGNMENT 0 227 228 /* An integer expression for the size in bits of the largest integer 229 machine mode that should actually be used. All integer machine modes of 230 this size or smaller can be used for structures and unions with the 231 appropriate sizes. */ 232 #define MAX_FIXED_MODE_SIZE 64 233 234 /* target machine storage layout */ 235 236 /* Size (bits) of the type "int" on target machine 237 (If undefined, default is BITS_PER_WORD). */ 238 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 239 240 /* Size (bits) of the type "short" on target machine */ 241 #define SHORT_TYPE_SIZE 16 242 243 /* Size (bits) of the type "long" on target machine */ 244 #define LONG_TYPE_SIZE 32 245 246 /* Size (bits) of the type "long long" on target machine */ 247 #define LONG_LONG_TYPE_SIZE 64 248 249 /* A C expression for the size in bits of the type `float' on the 250 target machine. If you don't define this, the default is one word. 251 Don't use default: a word is only 16. */ 252 #define FLOAT_TYPE_SIZE 32 253 254 /* A C expression for the size in bits of the type double on the target 255 machine. If you don't define this, the default is two words. 256 Be IEEE compliant. */ 257 #define DOUBLE_TYPE_SIZE 64 258 259 #define LONG_DOUBLE_TYPE_SIZE 64 260 261 /* Define this as 1 if `char' should by default be signed; else as 0. */ 262 #define DEFAULT_SIGNED_CHAR 0 263 264 /* Define these to avoid dependence on meaning of `int'. 265 Note that WCHAR_TYPE_SIZE is used in cexp.y, 266 where TARGET_SHORT is not available. */ 267 #define WCHAR_TYPE "short int" 268 #define WCHAR_TYPE_SIZE 16 269 270 271 /* Standard register usage. */ 272 273 #define HARD_REG_SIZE (UNITS_PER_WORD) 274 275 /* Assign names to real MC68HC11 registers. 276 A and B registers are not really used (A+B = D) 277 X register is first so that GCC allocates X+D for 32-bit integers and 278 the lowpart of that integer will be D. Having the lower part in D is 279 better for 32<->16bit conversions and for many arithmetic operations. */ 280 #define HARD_X_REGNUM 0 281 #define HARD_D_REGNUM 1 282 #define HARD_Y_REGNUM 2 283 #define HARD_SP_REGNUM 3 284 #define HARD_PC_REGNUM 4 285 #define HARD_A_REGNUM 5 286 #define HARD_B_REGNUM 6 287 #define HARD_CCR_REGNUM 7 288 289 /* The Z register does not really exist in the 68HC11. This a fake register 290 for GCC. It is treated exactly as an index register (X or Y). It is only 291 in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this 292 register helps the reload pass of GCC. Otherwise, the reload often dies 293 with register spill failures. 294 295 The Z register is replaced by either X or Y during the machine specific 296 reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register 297 when this is necessary. 298 299 It's possible to tell GCC not to use this register with -ffixed-z. */ 300 #define HARD_Z_REGNUM 8 301 302 /* The frame pointer is a soft-register. It's treated as such by GCC: 303 it is not and must not be part of the BASE_REG_CLASS. */ 304 #define DEFAULT_HARD_FP_REGNUM (9) 305 #define HARD_FP_REGNUM (9) 306 #define HARD_AP_REGNUM (HARD_FP_REGNUM) 307 308 /* Temporary soft-register used in some cases when an operand came 309 up into a bad register class (D, X, Y, SP) and gcc failed to 310 recognize this. This register is never allocated by GCC. */ 311 #define SOFT_TMP_REGNUM 10 312 313 /* The soft-register which is used to save the Z register 314 (see Z register replacement notes in m68hc11.c). */ 315 #define SOFT_Z_REGNUM 11 316 317 /* The soft-register which is used to save either X or Y. */ 318 #define SOFT_SAVED_XY_REGNUM 12 319 320 /* A fake clobber register for 68HC12 patterns. */ 321 #define FAKE_CLOBBER_REGNUM (13) 322 323 /* Define 32 soft-registers of 16-bit each. By default, 324 only 12 of them are enabled and can be used by GCC. The 325 -msoft-reg-count=<n> option allows to control the number of valid 326 soft-registers. GCC can put 32-bit values in them 327 by allocating consecutive registers. The first 3 soft-registers 328 are never allocated by GCC. They are used in case the insn template needs 329 a temporary register, or for the Z register replacement. */ 330 331 #define MAX_SOFT_REG_COUNT (32) 332 #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \ 333 0, 0, 0, 0, 1, 1, 1, 1, \ 334 1, 1, 1, 1, 1, 1, 1, 1, \ 335 1, 1, 1, 1, 1, 1, 1, 1 336 #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \ 337 0, 0, 0, 0, 1, 1, 1, 1, \ 338 1, 1, 1, 1, 1, 1, 1, 1, \ 339 1, 1, 1, 1, 1, 1, 1, 1 340 #define SOFT_REG_ORDER \ 341 SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\ 342 SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\ 343 SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\ 344 SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\ 345 SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\ 346 SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\ 347 SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\ 348 SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31 349 350 #define SOFT_REG_NAMES \ 351 "*_.d1", "*_.d2", "*_.d3", "*_.d4", \ 352 "*_.d5", "*_.d6", "*_.d7", "*_.d8", \ 353 "*_.d9", "*_.d10", "*_.d11", "*_.d12", \ 354 "*_.d13", "*_.d14", "*_.d15", "*_.d16", \ 355 "*_.d17", "*_.d18", "*_.d19", "*_.d20", \ 356 "*_.d21", "*_.d22", "*_.d23", "*_.d24", \ 357 "*_.d25", "*_.d26", "*_.d27", "*_.d28", \ 358 "*_.d29", "*_.d30", "*_.d31", "*_.d32" 359 360 /* First available soft-register for GCC. */ 361 #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2) 362 363 /* Last available soft-register for GCC. */ 364 #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT) 365 #define SOFT_FP_REGNUM (SOFT_REG_LAST) 366 #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1) 367 368 /* Number of actual hardware registers. The hardware registers are assigned 369 numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. 370 All registers that the compiler knows about must be given numbers, even 371 those that are not normally considered general registers. */ 372 #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2) 373 374 /* 1 for registers that have pervasive standard uses and are not available 375 for the register allocator. */ 376 #define FIXED_REGISTERS \ 377 {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1} 378 /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */ 379 380 /* 1 for registers not available across function calls. For our pseudo 381 registers, all are available. */ 382 #define CALL_USED_REGISTERS \ 383 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1} 384 /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */ 385 386 387 /* Define this macro to change register usage conditional on target flags. 388 389 The soft-registers are disabled or enabled according to the 390 -msoft-reg-count=<n> option. */ 391 392 393 #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ()) 394 395 /* List the order in which to allocate registers. Each register must be 396 listed once, even those in FIXED_REGISTERS. */ 397 #define REG_ALLOC_ORDER \ 398 { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \ 399 SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \ 400 HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \ 401 HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \ 402 SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM } 403 404 /* A C expression for the number of consecutive hard registers, 405 starting at register number REGNO, required to hold a value of 406 mode MODE. */ 407 #define HARD_REGNO_NREGS(REGNO, MODE) \ 408 ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \ 409 ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE)) 410 411 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 412 - 8 bit values are stored anywhere (except the SP register). 413 - 16 bit values can be stored in any register whose mode is 16 414 - 32 bit values can be stored in D, X registers or in a soft register 415 (except the last one because we need 2 soft registers) 416 - Values whose size is > 32 bit are not stored in real hard 417 registers. They may be stored in soft registers if there are 418 enough of them. */ 419 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 420 hard_regno_mode_ok (REGNO,MODE) 421 422 /* Value is 1 if it is a good idea to tie two pseudo registers when one has 423 mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce 424 different values for MODE1 and MODE2, for any hard reg, then this must be 425 0 for correct output. 426 427 All modes are tieable except QImode. */ 428 #define MODES_TIEABLE_P(MODE1, MODE2) \ 429 (((MODE1) == (MODE2)) \ 430 || ((MODE1) != QImode && (MODE2) != QImode)) 431 432 433 /* Define the classes of registers for register constraints in the 434 machine description. Also define ranges of constants. 435 436 One of the classes must always be named ALL_REGS and include all hard regs. 437 If there is more than one class, another class must be named NO_REGS 438 and contain no registers. 439 440 The name GENERAL_REGS must be the name of a class (or an alias for 441 another name such as ALL_REGS). This is the class of registers 442 that is allowed by "g" or "r" in a register constraint. 443 Also, registers outside this class are allocated only when 444 instructions express preferences for them. 445 446 The classes must be numbered in nondecreasing order; that is, 447 a larger-numbered class must never be contained completely 448 in a smaller-numbered class. 449 450 For any two classes, it is very desirable that there be another 451 class that represents their union. */ 452 453 /* The M68hc11 has so few registers that it's not possible for GCC to 454 do any register allocation without breaking. We extend the processor 455 registers by having soft registers. These registers are treated as 456 hard registers by GCC but they are located in memory and accessed by page0 457 accesses (IND mode). */ 458 enum reg_class 459 { 460 NO_REGS, 461 D_REGS, /* 16-bit data register */ 462 X_REGS, /* 16-bit X register */ 463 Y_REGS, /* 16-bit Y register */ 464 SP_REGS, /* 16 bit stack pointer */ 465 DA_REGS, /* 8-bit A reg. */ 466 DB_REGS, /* 8-bit B reg. */ 467 Z_REGS, /* 16-bit fake Z register */ 468 D8_REGS, /* 8-bit A or B reg. */ 469 Q_REGS, /* 8-bit (byte (QI)) data (A, B or D) */ 470 D_OR_X_REGS, /* D or X register */ 471 D_OR_Y_REGS, /* D or Y register */ 472 D_OR_SP_REGS, /* D or SP register */ 473 X_OR_Y_REGS, /* IX or Y register */ 474 A_REGS, /* 16-bit address register (X, Y, Z) */ 475 X_OR_SP_REGS, /* X or SP register */ 476 Y_OR_SP_REGS, /* Y or SP register */ 477 X_OR_Y_OR_D_REGS, /* X, Y or D */ 478 A_OR_D_REGS, /* X, Y, Z or D */ 479 A_OR_SP_REGS, /* X, Y, Z or SP */ 480 H_REGS, /* 16-bit hard register (D, X, Y, Z, SP) */ 481 S_REGS, /* 16-bit soft register */ 482 D_OR_S_REGS, /* 16-bit soft register or D register */ 483 X_OR_S_REGS, /* 16-bit soft register or X register */ 484 Y_OR_S_REGS, /* 16-bit soft register or Y register */ 485 Z_OR_S_REGS, /* 16-bit soft register or Z register */ 486 SP_OR_S_REGS, /* 16-bit soft register or SP register */ 487 D_OR_X_OR_S_REGS, /* 16-bit soft register or D or X register */ 488 D_OR_Y_OR_S_REGS, /* 16-bit soft register or D or Y register */ 489 D_OR_SP_OR_S_REGS, /* 16-bit soft register or D or SP register */ 490 A_OR_S_REGS, /* 16-bit soft register or X, Y registers */ 491 D_OR_A_OR_S_REGS, /* 16-bit soft register or D, X, Y registers */ 492 TMP_REGS, /* 16 bit fake scratch register */ 493 D_OR_A_OR_TMP_REGS, /* General scratch register */ 494 G_REGS, /* 16-bit general register 495 (H_REGS + soft registers) */ 496 ALL_REGS, 497 LIM_REG_CLASSES 498 }; 499 500 /* alias GENERAL_REGS to G_REGS. */ 501 #define GENERAL_REGS G_REGS 502 503 #define N_REG_CLASSES (int) LIM_REG_CLASSES 504 505 /* Give names of register classes as strings for dump file. */ 506 #define REG_CLASS_NAMES \ 507 { "NO_REGS", \ 508 "D_REGS", \ 509 "X_REGS", \ 510 "Y_REGS", \ 511 "SP_REGS", \ 512 "DA_REGS", \ 513 "DB_REGS", \ 514 "D8_REGS", \ 515 "Z_REGS", \ 516 "Q_REGS", \ 517 "D_OR_X_REGS", \ 518 "D_OR_Y_REGS", \ 519 "D_OR_SP_REGS", \ 520 "X_OR_Y_REGS", \ 521 "A_REGS", \ 522 "X_OR_SP_REGS", \ 523 "Y_OR_SP_REGS", \ 524 "X_OR_Y_OR_D_REGS", \ 525 "A_OR_D_REGS", \ 526 "A_OR_SP_REGS", \ 527 "H_REGS", \ 528 "S_REGS", \ 529 "D_OR_S_REGS", \ 530 "X_OR_S_REGS", \ 531 "Y_OR_S_REGS", \ 532 "Z_OR_S_REGS", \ 533 "SP_OR_S_REGS", \ 534 "D_OR_X_OR_S_REGS", \ 535 "D_OR_Y_OR_S_REGS", \ 536 "D_OR_SP_OR_S_REGS", \ 537 "A_OR_S_REGS", \ 538 "D_OR_A_OR_S_REGS", \ 539 "TMP_REGS", \ 540 "D_OR_A_OR_TMP_REGS", \ 541 "G_REGS", \ 542 "ALL_REGS" } 543 544 /* An initializer containing the contents of the register classes, 545 as integers which are bit masks. The Nth integer specifies the 546 contents of class N. The way the integer MASK is interpreted is 547 that register R is in the class if `MASK & (1 << R)' is 1. */ 548 549 /*-------------------------------------------------------------- 550 X 0x00000001 551 D 0x00000002 552 Y 0x00000004 553 SP 0x00000008 554 PC 0x00000010 555 A 0x00000020 556 B 0x00000040 557 CCR 0x00000080 558 Z 0x00000100 559 FRAME 0x00000200 560 ZTMP 0x00000400 561 ZREG 0x00000800 562 XYREG 0x00001000 563 FAKE 0x00002000 564 Di 0xFFFFc000, 0x03FFF 565 SFRAME 0x00000000, 0x04000 566 AP 0x00000000, 0x08000 567 568 D_OR_X_REGS represents D+X. It is used for 32-bits numbers. 569 A_REGS represents a valid base register for indexing. It represents 570 X,Y and the Z register. 571 S_REGS represents the soft-registers. This includes the hard frame 572 and soft frame registers. 573 --------------------------------------------------------------*/ 574 575 #define REG_CLASS_CONTENTS \ 576 /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \ 577 /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \ 578 /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \ 579 /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \ 580 /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \ 581 /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \ 582 /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \ 583 /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \ 584 /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \ 585 /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \ 586 /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \ 587 /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \ 588 /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \ 589 /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \ 590 /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \ 591 /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \ 592 /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \ 593 /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \ 594 /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \ 595 /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \ 596 /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \ 597 /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \ 598 /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \ 599 /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \ 600 /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \ 601 /* Z_OR_S_REGS */ { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */ \ 602 /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \ 603 /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \ 604 /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \ 605 /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \ 606 /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \ 607 /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \ 608 /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \ 609 /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \ 610 /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \ 611 /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }} 612 613 614 /* set up a C expression whose value is a register class containing hard 615 register REGNO */ 616 #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \ 617 || (REGNO) == HARD_B_REGNUM) 618 #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X))) 619 620 #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM) 621 #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 622 623 #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM) 624 #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X))) 625 #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM) 626 #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X))) 627 628 #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM) 629 #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X))) 630 631 #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM) 632 #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X))) 633 634 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) 635 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) 636 637 #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM) 638 #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X))) 639 640 /* Address register. */ 641 #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \ 642 || (REGNO) == HARD_Y_REGNUM \ 643 || (REGNO) == HARD_Z_REGNUM) 644 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X))) 645 646 /* M68hc11 hard registers. */ 647 #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \ 648 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO)) 649 #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X))) 650 651 #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM) 652 #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X))) 653 654 /* Soft registers (or register emulation for gcc). The temporary register 655 used by insn template must be part of the S_REGS class so that it 656 matches the 'u' constraint. */ 657 #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \ 658 && (REGNO) <= SOFT_REG_LAST \ 659 && (REGNO) != FAKE_CLOBBER_REGNUM) 660 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X))) 661 662 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) 663 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) 664 665 /* General register. */ 666 #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \ 667 || ((REGNO) == HARD_PC_REGNUM) \ 668 || ((REGNO) == HARD_FP_REGNUM) \ 669 || ((REGNO) == SOFT_FP_REGNUM) \ 670 || ((REGNO) == FAKE_CLOBBER_REGNUM) \ 671 || ((REGNO) == SOFT_AP_REGNUM)) 672 673 #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X))) 674 675 #define REGNO_REG_CLASS(REGNO) \ 676 (D_REGNO_P (REGNO) ? D_REGS : \ 677 (X_REGNO_P (REGNO) ? X_REGS : \ 678 (Y_REGNO_P (REGNO) ? Y_REGS : \ 679 (SP_REGNO_P (REGNO) ? SP_REGS : \ 680 (Z_REGNO_P (REGNO) ? Z_REGS : \ 681 (H_REGNO_P (REGNO) ? H_REGS : \ 682 (FAKE_REGNO_P (REGNO) ? TMP_REGS : \ 683 (S_REGNO_P (REGNO) ? S_REGS : \ 684 (DA_REGNO_P (REGNO) ? DA_REGS: \ 685 (DB_REGNO_P (REGNO) ? DB_REGS: \ 686 (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS))))))))))) 687 688 689 /* Get reg_class from a letter in the machine description. */ 690 691 extern enum reg_class m68hc11_tmp_regs_class; 692 #define REG_CLASS_FROM_LETTER(C) \ 693 ((C) == 'a' ? DA_REGS : \ 694 (C) == 'A' ? A_REGS : \ 695 (C) == 'b' ? DB_REGS : \ 696 (C) == 'B' ? X_OR_Y_REGS : \ 697 (C) == 'd' ? D_REGS : \ 698 (C) == 'D' ? D_OR_X_REGS : \ 699 (C) == 'q' ? Q_REGS : \ 700 (C) == 'h' ? H_REGS : \ 701 (C) == 't' ? TMP_REGS : \ 702 (C) == 'u' ? S_REGS : \ 703 (C) == 'v' ? m68hc11_tmp_regs_class : \ 704 (C) == 'w' ? SP_REGS : \ 705 (C) == 'x' ? X_REGS : \ 706 (C) == 'y' ? Y_REGS : \ 707 (C) == 'z' ? Z_REGS : NO_REGS) 708 709 #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS) 710 711 #define SMALL_REGISTER_CLASSES 1 712 713 /* A C expression that is nonzero if hard register number REGNO2 can be 714 considered for use as a rename register for REGNO1 */ 715 716 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ 717 m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2)) 718 719 /* A C expression whose value is nonzero if pseudos that have been 720 assigned to registers of class CLASS would likely be spilled 721 because registers of CLASS are needed for spill registers. 722 723 The default value of this macro returns 1 if CLASS has exactly one 724 register and zero otherwise. On most machines, this default 725 should be used. Only define this macro to some other expression 726 if pseudo allocated by `local-alloc.c' end up in memory because 727 their hard registers were needed for spill registers. If this 728 macro returns nonzero for those classes, those pseudos will only 729 be allocated by `global.c', which knows how to reallocate the 730 pseudo to another register. If there would not be another 731 register available for reallocation, you should not change the 732 definition of this macro since the only effect of such a 733 definition would be to slow down register allocation. */ 734 735 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 736 (((CLASS) == D_REGS) \ 737 || ((CLASS) == X_REGS) \ 738 || ((CLASS) == Y_REGS) \ 739 || ((CLASS) == A_REGS) \ 740 || ((CLASS) == SP_REGS) \ 741 || ((CLASS) == D_OR_X_REGS) \ 742 || ((CLASS) == D_OR_Y_REGS) \ 743 || ((CLASS) == X_OR_SP_REGS) \ 744 || ((CLASS) == Y_OR_SP_REGS) \ 745 || ((CLASS) == D_OR_SP_REGS)) 746 747 /* Return the maximum number of consecutive registers needed to represent 748 mode MODE in a register of class CLASS. */ 749 #define CLASS_MAX_NREGS(CLASS, MODE) \ 750 (((CLASS) == DA_REGS || (CLASS) == DB_REGS \ 751 || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \ 752 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 753 754 /* The letters I, J, K, L and M in a register constraint string 755 can be used to stand for particular ranges of immediate operands. 756 This macro defines what the ranges are. 757 C is the letter, and VALUE is a constant value. 758 Return 1 if VALUE is in the range specified by C. 759 760 `K' is for 0. 761 `L' is for range -65536 to 65536 762 `M' is for values whose 16-bit low part is 0 763 'N' is for +1 or -1. 764 'O' is for 16 (for rotate using swap). 765 'P' is for range -8 to 2 (used by addhi_sp) 766 767 'I', 'J' are not used. */ 768 769 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 770 ((C) == 'K' ? (VALUE) == 0 : \ 771 (C) == 'L' ? ((VALUE) >= -65536 && (VALUE) <= 65535) : \ 772 (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \ 773 (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1) : \ 774 (C) == 'I' ? ((VALUE) >= -2 && (VALUE) <= 2) : \ 775 (C) == 'O' ? (VALUE) == 16 : \ 776 (C) == 'P' ? ((VALUE) <= 2 && (VALUE) >= -8) : 0) 777 778 /* Similar, but for floating constants, and defining letters G and H. 779 780 `G' is for 0.0. */ 781 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 782 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ 783 && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0) 784 785 /* 'U' represents certain kind of memory indexed operand for 68HC12. 786 and any memory operand for 68HC11. 787 'R' represents indexed addressing mode or access to page0 for 68HC11. 788 For 68HC12, it represents any memory operand. */ 789 #define EXTRA_CONSTRAINT(OP, C) \ 790 ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \ 791 : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \ 792 : (C) == 'R' ? m68hc11_indirect_p (OP, GET_MODE (OP)) \ 793 : (C) == 'S' ? (memory_operand (OP, GET_MODE (OP)) \ 794 && non_push_operand (OP, GET_MODE (OP))) : 0) 795 796 797 /* Stack layout; function entry, exit and calling. */ 798 799 /* Define this if pushing a word on the stack 800 makes the stack pointer a smaller address. */ 801 #define STACK_GROWS_DOWNWARD 802 803 /* Define this to nonzero if the nominal address of the stack frame 804 is at the high-address end of the local variables; 805 that is, each additional local variable allocated 806 goes at a more negative offset in the frame. 807 808 Define to 0 for 68HC11, the frame pointer is the bottom 809 of local variables. */ 810 #define FRAME_GROWS_DOWNWARD 0 811 812 /* Define this if successive arguments to a function occupy decreasing 813 addresses in the stack. */ 814 /* #define ARGS_GROW_DOWNWARD */ 815 816 /* Offset within stack frame to start allocating local variables at. 817 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 818 first local allocated. Otherwise, it is the offset to the BEGINNING 819 of the first local allocated. */ 820 #define STARTING_FRAME_OFFSET 0 821 822 /* Offset of first parameter from the argument pointer register value. */ 823 824 #define FIRST_PARM_OFFSET(FNDECL) 2 825 826 /* After the prologue, RA is at 0(AP) in the current frame. */ 827 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 828 ((COUNT) == 0 \ 829 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ 830 : 0) 831 832 /* Before the prologue, the top of the frame is at 2(sp). */ 833 #define INCOMING_FRAME_SP_OFFSET 2 834 835 /* Define this if functions should assume that stack space has been 836 allocated for arguments even when their values are passed in 837 registers. 838 839 The value of this macro is the size, in bytes, of the area reserved for 840 arguments passed in registers. 841 842 This space can either be allocated by the caller or be a part of the 843 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 844 says which. */ 845 /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */ 846 847 /* Define this macro if REG_PARM_STACK_SPACE is defined but stack 848 parameters don't skip the area specified by REG_PARM_STACK_SPACE. 849 Normally, when a parameter is not passed in registers, it is placed on 850 the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro 851 suppresses this behavior and causes the parameter to be passed on the 852 stack in its natural location. */ 853 /* #define STACK_PARMS_IN_REG_PARM_AREA */ 854 855 /* Register to use for pushing function arguments. */ 856 #define STACK_POINTER_REGNUM HARD_SP_REGNUM 857 858 /* Base register for access to local variables of the function. */ 859 #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM 860 861 #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM 862 863 /* Base register for access to arguments of the function. */ 864 #define ARG_POINTER_REGNUM SOFT_AP_REGNUM 865 866 /* Register in which static-chain is passed to a function. */ 867 #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM 868 869 870 /* Definitions for register eliminations. 871 872 This is an array of structures. Each structure initializes one pair 873 of eliminable registers. The "from" register number is given first, 874 followed by "to". Eliminations of the same "from" register are listed 875 in order of preference. 876 877 We have two registers that are eliminated on the 6811. The pseudo arg 878 pointer and pseudo frame pointer registers can always be eliminated; 879 they are replaced with either the stack or the real frame pointer. */ 880 881 #define ELIMINABLE_REGS \ 882 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 883 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 884 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 885 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 886 887 /* Value should be nonzero if functions must have frame pointers. 888 Zero means the frame pointer need not be set up (and parms may be 889 accessed via the stack pointer) in functions that seem suitable. 890 This is computed in `reload', in reload1.c. */ 891 #define FRAME_POINTER_REQUIRED 0 892 893 /* Given FROM and TO register numbers, say whether this elimination is allowed. 894 Frame pointer elimination is automatically handled. 895 896 All other eliminations are valid. */ 897 898 #define CAN_ELIMINATE(FROM, TO) \ 899 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ 900 ? ! frame_pointer_needed \ 901 : 1) 902 903 904 /* Define the offset between two registers, one to be eliminated, and the other 905 its replacement, at the start of a routine. */ 906 907 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 908 { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); } 909 910 911 /* Passing Function Arguments on the Stack. */ 912 913 /* If we generate an insn to push BYTES bytes, this says how many the 914 stack pointer really advances by. No rounding or alignment needed 915 for MC6811. */ 916 #define PUSH_ROUNDING(BYTES) (BYTES) 917 918 /* Value is 1 if returning from a function call automatically pops the 919 arguments described by the number-of-args field in the call. FUNTYPE is 920 the data type of the function (as a tree), or for a library call it is 921 an identifier node for the subroutine name. 922 923 The standard MC6811 call, with arg count word, includes popping the 924 args as part of the call template. */ 925 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 926 927 /* Passing Arguments in Registers. */ 928 929 /* Define a data type for recording info about an argument list 930 during the scan of that argument list. This data type should 931 hold all necessary information about the function itself 932 and about the args processed so far, enough to enable macros 933 such as FUNCTION_ARG to determine where the next arg should go. */ 934 935 typedef struct m68hc11_args 936 { 937 int words; 938 int nregs; 939 } CUMULATIVE_ARGS; 940 941 /* If defined, a C expression which determines whether, and in which direction, 942 to pad out an argument with extra space. The value should be of type 943 `enum direction': either `upward' to pad above the argument, 944 `downward' to pad below, or `none' to inhibit padding. 945 946 Structures are stored left shifted in their argument slot. */ 947 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 948 m68hc11_function_arg_padding ((MODE), (TYPE)) 949 950 #undef PAD_VARARGS_DOWN 951 #define PAD_VARARGS_DOWN \ 952 (m68hc11_function_arg_padding (TYPE_MODE (type), type) == downward) 953 954 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a 955 function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ 956 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 957 (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 958 959 /* Update the data in CUM to advance over an argument of mode MODE and data 960 type TYPE. (TYPE is null for libcalls where that information may not be 961 available.) */ 962 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 963 (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED)) 964 965 /* Define where to put the arguments to a function. 966 Value is zero to push the argument on the stack, 967 or a hard register in which to store the argument. 968 969 MODE is the argument's machine mode. 970 TYPE is the data type of the argument (as a tree). 971 This is null for libcalls where that information may 972 not be available. 973 CUM is a variable of type CUMULATIVE_ARGS which gives info about 974 the preceding args and about the function being called. 975 NAMED is nonzero if this argument is a named parameter 976 (otherwise it is an extra parameter matching an ellipsis). */ 977 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 978 (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED)) 979 980 /* Define the profitability of saving registers around calls. 981 982 Disable this because the saving instructions generated by 983 caller-save need a reload and the way it is implemented, 984 it forbids all spill registers at that point. Enabling 985 caller saving results in spill failure. */ 986 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 987 988 /* 1 if N is a possible register number for function argument passing. 989 D is for 16-bit values, X is for 32-bit (X+D). */ 990 #define FUNCTION_ARG_REGNO_P(N) \ 991 (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM)) 992 993 /* All return values are in the D or X+D registers: 994 - 8 and 16-bit values are returned in D. 995 BLKmode are passed in D as pointer. 996 - 32-bit values are returned in X + D. 997 The high part is passed in X and the low part in D. 998 For GCC, the register number must be HARD_X_REGNUM. */ 999 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1000 gen_rtx_REG (TYPE_MODE (VALTYPE), \ 1001 ((TYPE_MODE (VALTYPE) == BLKmode \ 1002 || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \ 1003 ? HARD_D_REGNUM : HARD_X_REGNUM)) 1004 1005 #define LIBCALL_VALUE(MODE) \ 1006 gen_rtx_REG (MODE, \ 1007 (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \ 1008 ? HARD_D_REGNUM : HARD_X_REGNUM)) 1009 1010 /* 1 if N is a possible register number for a function value. */ 1011 #define FUNCTION_VALUE_REGNO_P(N) \ 1012 ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM) 1013 1014 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1015 the stack pointer does not matter. The value is tested only in functions 1016 that have frame pointers. No definition is equivalent to always zero. */ 1017 #define EXIT_IGNORE_STACK 0 1018 1019 1020 /* Generating Code for Profiling. */ 1021 1022 /* Output assembler code to FILE to increment profiler label # LABELNO 1023 for profiling a function entry. */ 1024 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1025 fprintf (FILE, "\tldy\t.LP%d\n\tjsr mcount\n", (LABELNO)) 1026 /* Length in units of the trampoline for entering a nested function. */ 1027 #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9) 1028 1029 /* A C statement to initialize the variable parts of a trampoline. 1030 ADDR is an RTX for the address of the trampoline; FNADDR is an 1031 RTX for the address of the nested function; STATIC_CHAIN is an 1032 RTX for the static chain value that should be passed to the 1033 function when it is called. */ 1034 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1035 m68hc11_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1036 1037 1038 /* Addressing modes, and classification of registers for them. */ 1039 1040 #define ADDR_STRICT 0x01 /* Accept only registers in class A_REGS */ 1041 #define ADDR_INCDEC 0x02 /* Post/Pre inc/dec */ 1042 #define ADDR_INDEXED 0x04 /* D-reg index */ 1043 #define ADDR_OFFSET 0x08 1044 #define ADDR_INDIRECT 0x10 /* Accept (mem (mem ...)) for [n,X] */ 1045 #define ADDR_CONST 0x20 /* Accept const and symbol_ref */ 1046 1047 /* The 68HC12 has all the post/pre increment/decrement modes. */ 1048 #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1049 #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1050 #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1051 #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1052 1053 /* The class value for base registers. This depends on the target: 1054 A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value 1055 is stored at init time. */ 1056 extern enum reg_class m68hc11_base_reg_class; 1057 #define BASE_REG_CLASS m68hc11_base_reg_class 1058 1059 /* The class value for index registers. This is NO_REGS for 68HC11. */ 1060 1061 extern enum reg_class m68hc11_index_reg_class; 1062 #define INDEX_REG_CLASS m68hc11_index_reg_class 1063 1064 /* These assume that REGNO is a hard or pseudo reg number. They give nonzero 1065 only if REGNO is a hard reg of the suitable class or a pseudo reg currently 1066 allocated to a suitable hard reg. Since they use reg_renumber, they are 1067 safe only once reg_renumber has been allocated, which happens in 1068 local-alloc.c. */ 1069 1070 1071 /* Internal macro, return 1 if REGNO is a valid base register. */ 1072 #define REG_VALID_P(REGNO) ((REGNO) >= 0) 1073 1074 extern unsigned char m68hc11_reg_valid_for_base[FIRST_PSEUDO_REGISTER]; 1075 #define REG_VALID_FOR_BASE_P(REGNO) \ 1076 (REG_VALID_P (REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER \ 1077 && m68hc11_reg_valid_for_base[REGNO]) 1078 1079 /* Internal macro, return 1 if REGNO is a valid index register. */ 1080 extern unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER]; 1081 #define REG_VALID_FOR_INDEX_P(REGNO) \ 1082 (REG_VALID_P (REGNO) >= 0 && (REGNO) < FIRST_PSEUDO_REGISTER \ 1083 && m68hc11_reg_valid_for_index[REGNO]) 1084 1085 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */ 1086 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ 1087 ((REGNO) >= FIRST_PSEUDO_REGISTER \ 1088 || REG_VALID_FOR_BASE_P (REGNO) \ 1089 || (REGNO) == FRAME_POINTER_REGNUM \ 1090 || (REGNO) == HARD_FRAME_POINTER_REGNUM \ 1091 || (REGNO) == ARG_POINTER_REGNUM \ 1092 || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) 1093 1094 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */ 1095 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ 1096 (TARGET_M6812 \ 1097 && ((REGNO) >= FIRST_PSEUDO_REGISTER \ 1098 || REG_VALID_FOR_INDEX_P (REGNO) \ 1099 || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) 1100 1101 /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */ 1102 #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \ 1103 ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \ 1104 : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) 1105 1106 /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */ 1107 #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \ 1108 (TARGET_M6812 \ 1109 && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \ 1110 : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) 1111 1112 #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \ 1113 ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \ 1114 : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO))) 1115 1116 #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \ 1117 ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \ 1118 : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO))) 1119 1120 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO) 1121 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO) 1122 1123 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X)) 1124 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X)) 1125 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X)) 1126 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X)) 1127 1128 /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */ 1129 #define IS_STACK_PUSH(operand) \ 1130 ((GET_CODE (operand) == MEM) \ 1131 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \ 1132 && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) 1133 1134 #define IS_STACK_POP(operand) \ 1135 ((GET_CODE (operand) == MEM) \ 1136 && (GET_CODE (XEXP (operand, 0)) == POST_INC) \ 1137 && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) 1138 1139 /* 1 if X is an rtx for a constant that is a valid address. */ 1140 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) 1141 1142 /* Maximum number of registers that can appear in a valid memory address */ 1143 #define MAX_REGS_PER_ADDRESS 2 1144 1145 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a 1146 valid memory address for an instruction. The MODE argument is the 1147 machine mode for the MEM expression that wants to use this address. */ 1148 1149 /*-------------------------------------------------------------- 1150 Valid addresses are either direct or indirect (MEM) versions 1151 of the following forms: 1152 constant N 1153 register ,X 1154 indexed N,X 1155 --------------------------------------------------------------*/ 1156 1157 /* The range of index that is allowed by indirect addressing. */ 1158 1159 #define VALID_MIN_OFFSET m68hc11_min_offset 1160 #define VALID_MAX_OFFSET m68hc11_max_offset 1161 1162 /* The offset values which are allowed by the n,x and n,y addressing modes. 1163 Take into account the size of the mode because we may have to add 1164 a mode offset to access the lowest part of the data. 1165 (For example, for an SImode, the last valid offset is 252.) */ 1166 #define VALID_CONSTANT_OFFSET_P(X,MODE) \ 1167 (((GET_CODE (X) == CONST_INT) && \ 1168 ((INTVAL (X) >= VALID_MIN_OFFSET) \ 1169 && ((INTVAL (X) <= VALID_MAX_OFFSET \ 1170 - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1))))) \ 1171 || (TARGET_M6812 \ 1172 && ((GET_CODE (X) == SYMBOL_REF) \ 1173 || GET_CODE (X) == LABEL_REF \ 1174 || GET_CODE (X) == CONST))) 1175 1176 /* This is included to allow stack push/pop operations. Special hacks in the 1177 md and m6811.c files exist to support this. */ 1178 #define PUSH_POP_ADDRESS_P(X) \ 1179 (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \ 1180 && SP_REG_P (XEXP (X, 0))) 1181 1182 /* Go to ADDR if X is a valid address. */ 1183 #ifndef REG_OK_STRICT 1184 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1185 { \ 1186 if (m68hc11_go_if_legitimate_address ((X), (MODE), 0)) goto ADDR; \ 1187 } 1188 #else 1189 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1190 { \ 1191 if (m68hc11_go_if_legitimate_address ((X), (MODE), 1)) goto ADDR; \ 1192 } 1193 #endif 1194 1195 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its 1196 validity for a certain class. We have two alternate definitions for each 1197 of them. The usual definition accepts all pseudo regs; the other rejects 1198 them unless they have been allocated suitable hard regs. The symbol 1199 REG_OK_STRICT causes the latter definition to be used. 1200 1201 Most source files want to accept pseudo regs in the hope that they will 1202 get allocated to the class that the insn wants them to be in. Source files 1203 for reload pass need to be strict. After reload, it makes no difference, 1204 since pseudo regs have been eliminated by then. */ 1205 1206 #ifndef REG_OK_STRICT 1207 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1208 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) 1209 1210 /* Nonzero if X is a hard reg that can be used as an index. */ 1211 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) 1212 #else 1213 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) 1214 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) 1215 #endif 1216 1217 1218 /* Try machine-dependent ways of modifying an illegitimate address 1219 to be legitimate. If we find one, return the new, valid address. 1220 This macro is used in only one place: `memory_address' in explow.c. 1221 1222 OLDX is the address as it was before break_out_memory_refs was called. 1223 In some cases it is useful to look at this to decide what needs to be done. 1224 1225 MODE and WIN are passed so that this macro can use 1226 GO_IF_LEGITIMATE_ADDRESS. 1227 1228 It is always safe for this macro to do nothing. 1229 It exists to recognize opportunities to optimize the output. */ 1230 1231 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1232 { rtx operand = (X); \ 1233 if (m68hc11_legitimize_address (&operand, (OLDX), (MODE))) \ 1234 { \ 1235 (X) = operand; \ 1236 GO_IF_LEGITIMATE_ADDRESS (MODE,X,WIN); \ 1237 } \ 1238 } 1239 1240 /* Go to LABEL if ADDR (a legitimate address expression) 1241 has an effect that depends on the machine mode it is used for. */ 1242 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1243 { \ 1244 if (GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ 1245 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ 1246 goto LABEL; \ 1247 } 1248 1249 /* Nonzero if the constant value X is a legitimate general operand. 1250 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1251 1252 #define LEGITIMATE_CONSTANT_P(X) 1 1253 1254 1255 /* Tell final.c how to eliminate redundant test instructions. */ 1256 1257 #define NOTICE_UPDATE_CC(EXP, INSN) \ 1258 m68hc11_notice_update_cc ((EXP), (INSN)) 1259 1260 /* Move costs between classes of registers */ 1261 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1262 (m68hc11_register_move_cost (MODE, CLASS1, CLASS2)) 1263 1264 /* Move cost between register and memory. 1265 - Move to a 16-bit register is reasonable, 1266 - Move to a soft register can be expensive. */ 1267 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ 1268 m68hc11_memory_move_cost ((MODE),(CLASS),(IN)) 1269 1270 /* A C expression for the cost of a branch instruction. A value of 1 1271 is the default; other values are interpreted relative to that. 1272 1273 Pretend branches are cheap because GCC generates sub-optimal code 1274 for the default value. */ 1275 #define BRANCH_COST 0 1276 1277 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1278 #define SLOW_BYTE_ACCESS 0 1279 1280 /* It is as good to call a constant function address as to call an address 1281 kept in a register. */ 1282 #define NO_FUNCTION_CSE 1283 1284 /* Try a machine-dependent way of reloading an illegitimate address 1285 operand. If we find one, push the reload and jump to WIN. This 1286 macro is used in only one place: `find_reloads_address' in reload.c. 1287 1288 For M68HC11, we handle large displacements of a base register 1289 by splitting the addend across an addhi3 insn. 1290 1291 For M68HC12, the 64K offset range is available. 1292 */ 1293 1294 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1295 do { \ 1296 /* We must recognize output that we have already generated ourselves. */ \ 1297 if (GET_CODE (X) == PLUS \ 1298 && GET_CODE (XEXP (X, 0)) == PLUS \ 1299 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 1300 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ 1301 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1302 { \ 1303 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1304 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 1305 OPNUM, TYPE); \ 1306 goto WIN; \ 1307 } \ 1308 if (GET_CODE (X) == PLUS \ 1309 && GET_CODE (XEXP (X, 0)) == REG \ 1310 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1311 && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \ 1312 { \ 1313 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1314 HOST_WIDE_INT low, high; \ 1315 high = val & (~0x0FF); \ 1316 low = val & 0x00FF; \ 1317 if (low >= 256-15) { high += 16; low -= 16; } \ 1318 /* Reload the high part into a base reg; leave the low part \ 1319 in the mem directly. */ \ 1320 \ 1321 X = gen_rtx_PLUS (Pmode, \ 1322 gen_rtx_PLUS (Pmode, XEXP (X, 0), \ 1323 GEN_INT (high)), \ 1324 GEN_INT (low)); \ 1325 \ 1326 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1327 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 1328 OPNUM, TYPE); \ 1329 goto WIN; \ 1330 } \ 1331 } while (0) 1332 1333 1334 /* Defining the Output Assembler Language. */ 1335 1336 /* A default list of other sections which we might be "in" at any given 1337 time. For targets that use additional sections (e.g. .tdesc) you 1338 should override this definition in the target-specific file which 1339 includes this file. */ 1340 1341 /* Output before read-only data. */ 1342 #define TEXT_SECTION_ASM_OP ("\t.sect\t.text") 1343 1344 /* Output before writable data. */ 1345 #define DATA_SECTION_ASM_OP ("\t.sect\t.data") 1346 1347 /* Output before uninitialized data. */ 1348 #define BSS_SECTION_ASM_OP ("\t.sect\t.bss") 1349 1350 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. 1351 1352 Same as config/elfos.h but don't mark these section SHF_WRITE since 1353 there is no shared library problem. */ 1354 #undef CTORS_SECTION_ASM_OP 1355 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" 1356 1357 #undef DTORS_SECTION_ASM_OP 1358 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" 1359 1360 #define TARGET_ASM_CONSTRUCTOR m68hc11_asm_out_constructor 1361 #define TARGET_ASM_DESTRUCTOR m68hc11_asm_out_destructor 1362 1363 /* Comment character */ 1364 #define ASM_COMMENT_START ";" 1365 1366 /* Output to assembler file text saying following lines 1367 may contain character constants, extra white space, comments, etc. */ 1368 #define ASM_APP_ON "; Begin inline assembler code\n#APP\n" 1369 1370 /* Output to assembler file text saying following lines 1371 no longer contain unusual constructs. */ 1372 #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n" 1373 1374 /* Write the extra assembler code needed to declare a function properly. 1375 Some svr4 assemblers need to also have something extra said about the 1376 function's return value. We allow for that here. 1377 1378 For 68HC12 we mark functions that return with 'rtc'. The linker 1379 will ensure that a 'call' is really made (instead of 'jsr'). 1380 The debugger needs this information to correctly compute the stack frame. 1381 1382 For 68HC11/68HC12 we also mark interrupt handlers for gdb to 1383 compute the correct stack frame. */ 1384 1385 #undef ASM_DECLARE_FUNCTION_NAME 1386 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ 1387 do \ 1388 { \ 1389 fprintf (FILE, "%s", TYPE_ASM_OP); \ 1390 assemble_name (FILE, NAME); \ 1391 putc (',', FILE); \ 1392 fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ 1393 putc ('\n', FILE); \ 1394 \ 1395 if (current_function_far) \ 1396 { \ 1397 fprintf (FILE, "\t.far\t"); \ 1398 assemble_name (FILE, NAME); \ 1399 putc ('\n', FILE); \ 1400 } \ 1401 else if (current_function_interrupt \ 1402 || current_function_trap) \ 1403 { \ 1404 fprintf (FILE, "\t.interrupt\t"); \ 1405 assemble_name (FILE, NAME); \ 1406 putc ('\n', FILE); \ 1407 } \ 1408 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ 1409 ASM_OUTPUT_LABEL(FILE, NAME); \ 1410 } \ 1411 while (0) 1412 1413 /* Output #ident as a .ident. */ 1414 1415 /* output external reference */ 1416 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \ 1417 {fputs ("\t; extern\t", FILE); \ 1418 assemble_name (FILE, NAME); \ 1419 fputs ("\n", FILE);} 1420 1421 /* How to refer to registers in assembler output. This sequence is indexed 1422 by compiler's hard-register-number (see above). */ 1423 #define REGISTER_NAMES \ 1424 { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \ 1425 "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \ 1426 SOFT_REG_NAMES, "*sframe", "*ap"} 1427 1428 /* Print an instruction operand X on file FILE. CODE is the code from the 1429 %-spec for printing this operand. If `%z3' was used to print operand 1430 3, then CODE is 'z'. */ 1431 1432 #define PRINT_OPERAND(FILE, X, CODE) \ 1433 print_operand (FILE, X, CODE) 1434 1435 /* Print a memory operand whose address is X, on file FILE. */ 1436 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1437 print_operand_address (FILE, ADDR) 1438 1439 /* This is how to output an insn to push/pop a register on the stack. 1440 It need not be very fast code. 1441 1442 Don't define because we don't know how to handle that with 1443 the STATIC_CHAIN_REGNUM (soft register). Saving the static 1444 chain must be made inside FUNCTION_PROFILER. */ 1445 1446 #undef ASM_OUTPUT_REG_PUSH 1447 #undef ASM_OUTPUT_REG_POP 1448 1449 /* This is how to output an element of a case-vector that is relative. */ 1450 1451 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1452 fprintf (FILE, "\t%s\tL%d-L%d\n", integer_asm_op (2, TRUE), VALUE, REL) 1453 1454 /* This is how to output an element of a case-vector that is absolute. */ 1455 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1456 fprintf (FILE, "\t%s\t.L%d\n", integer_asm_op (2, TRUE), VALUE) 1457 1458 /* This is how to output an assembler line that says to advance the 1459 location counter to a multiple of 2**LOG bytes. */ 1460 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1461 do { \ 1462 if ((LOG) > 1) \ 1463 fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \ 1464 } while (0) 1465 1466 1467 /* Assembler Commands for Exception Regions. */ 1468 1469 /* Default values provided by GCC should be ok. Assuming that DWARF-2 1470 frame unwind info is ok for this platform. */ 1471 1472 #undef PREFERRED_DEBUGGING_TYPE 1473 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1474 1475 /* For the support of memory banks we need addresses that indicate 1476 the page number. */ 1477 #define DWARF2_ADDR_SIZE 4 1478 1479 /* SCz 2003-07-08: Don't use as dwarf2 .file/.loc directives because 1480 the linker is doing relaxation and it does not adjust the debug_line 1481 sections when it shrinks the code. This results in invalid addresses 1482 when debugging. This does not bless too much the HC11/HC12 as most 1483 applications are embedded and small, hence a reasonable debug info. 1484 This problem is known for binutils 2.13, 2.14 and mainline. */ 1485 #undef HAVE_AS_DWARF2_DEBUG_LINE 1486 1487 /* The prefix for local labels. You should be able to define this as 1488 an empty string, or any arbitrary string (such as ".", ".L%", etc) 1489 without having to make any other changes to account for the specific 1490 definition. Note it is a string literal, not interpreted by printf 1491 and friends. */ 1492 #define LOCAL_LABEL_PREFIX "." 1493 1494 /* The prefix for immediate operands. */ 1495 #define IMMEDIATE_PREFIX "#" 1496 #define GLOBAL_ASM_OP "\t.globl\t" 1497 1498 1499 /* Miscellaneous Parameters. */ 1500 1501 /* Specify the machine mode that this machine uses 1502 for the index in the tablejump instruction. */ 1503 #define CASE_VECTOR_MODE Pmode 1504 1505 /* This flag, if defined, says the same insns that convert to a signed fixnum 1506 also convert validly to an unsigned one. */ 1507 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC 1508 1509 /* Max number of bytes we can move from memory to memory in one 1510 reasonably fast instruction. */ 1511 #define MOVE_MAX 2 1512 1513 /* MOVE_RATIO is the number of move instructions that is better than a 1514 block move. Make this small on 6811, since the code size grows very 1515 large with each move. */ 1516 #define MOVE_RATIO 3 1517 1518 /* Define if shifts truncate the shift count which implies one can omit 1519 a sign-extension or zero-extension of a shift count. */ 1520 #define SHIFT_COUNT_TRUNCATED 1 1521 1522 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1523 is done just by pretending it is already truncated. */ 1524 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1525 1526 /* Specify the machine mode that pointers have. After generation of rtl, the 1527 compiler makes no further distinction between pointers and any other 1528 objects of this machine mode. */ 1529 #define Pmode HImode 1530 1531 /* A function address in a call instruction is a byte address (for indexing 1532 purposes) so give the MEM rtx a byte's mode. */ 1533 #define FUNCTION_MODE QImode 1534 1535 extern int debug_m6811; 1536 extern int z_replacement_completed; 1537 extern int current_function_interrupt; 1538 extern int current_function_trap; 1539 extern int current_function_far; 1540 1541 extern GTY(()) rtx m68hc11_compare_op0; 1542 extern GTY(()) rtx m68hc11_compare_op1; 1543 extern GTY(()) rtx m68hc11_soft_tmp_reg; 1544 extern GTY(()) rtx ix_reg; 1545 extern GTY(()) rtx iy_reg; 1546 extern GTY(()) rtx d_reg; 1547