1;; Predicate definitions for Vitesse IQ2000. 2;; Copyright (C) 2005 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 2, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to 18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19;; Boston, MA 02110-1301, USA. 20 21;; Return 1 if OP can be used as an operand where a register or 16 bit 22;; unsigned integer is needed. 23 24(define_predicate "uns_arith_operand" 25 (match_code "reg,const_int,subreg") 26{ 27 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op)) 28 return 1; 29 30 return register_operand (op, mode); 31}) 32 33;; Return 1 if OP can be used as an operand where a 16 bit integer is 34;; needed. 35 36(define_predicate "arith_operand" 37 (match_code "reg,const_int,subreg") 38{ 39 if (GET_CODE (op) == CONST_INT && SMALL_INT (op)) 40 return 1; 41 42 return register_operand (op, mode); 43}) 44 45;; Return 1 if OP is a integer which fits in 16 bits. 46 47(define_predicate "small_int" 48 (match_code "const_int") 49{ 50 return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); 51}) 52 53;; Return 1 if OP is a 32 bit integer which is too big to be loaded 54;; with one instruction. 55 56(define_predicate "large_int" 57 (match_code "const_int") 58{ 59 HOST_WIDE_INT value; 60 61 if (GET_CODE (op) != CONST_INT) 62 return 0; 63 64 value = INTVAL (op); 65 66 /* IOR reg,$r0,value. */ 67 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0) 68 return 0; 69 70 /* SUBU reg,$r0,value. */ 71 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767) 72 return 0; 73 74 /* LUI reg,value >> 16. */ 75 if ((value & 0x0000ffff) == 0) 76 return 0; 77 78 return 1; 79}) 80 81;; Return 1 if OP is a register or the constant 0. 82 83(define_predicate "reg_or_0_operand" 84 (match_code "reg,const_int,const_double,subreg") 85{ 86 switch (GET_CODE (op)) 87 { 88 case CONST_INT: 89 return INTVAL (op) == 0; 90 91 case CONST_DOUBLE: 92 return op == CONST0_RTX (mode); 93 94 case REG: 95 case SUBREG: 96 return register_operand (op, mode); 97 98 default: 99 break; 100 } 101 102 return 0; 103}) 104 105;; Return 1 if OP is a memory operand that fits in a single 106;; instruction (i.e., register + small offset). 107 108(define_predicate "simple_memory_operand" 109 (match_code "mem,subreg") 110{ 111 rtx addr, plus0, plus1; 112 113 /* Eliminate non-memory operations. */ 114 if (GET_CODE (op) != MEM) 115 return 0; 116 117 /* Dword operations really put out 2 instructions, so eliminate them. */ 118 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD) 119 return 0; 120 121 /* Decode the address now. */ 122 addr = XEXP (op, 0); 123 switch (GET_CODE (addr)) 124 { 125 case REG: 126 case LO_SUM: 127 return 1; 128 129 case CONST_INT: 130 return SMALL_INT (addr); 131 132 case PLUS: 133 plus0 = XEXP (addr, 0); 134 plus1 = XEXP (addr, 1); 135 if (GET_CODE (plus0) == REG 136 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1) 137 && SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */) 138 return 1; 139 140 else if (GET_CODE (plus1) == REG 141 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0) 142 && SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */) 143 return 1; 144 145 else 146 return 0; 147 148 case SYMBOL_REF: 149 return 0; 150 151 default: 152 break; 153 } 154 155 return 0; 156}) 157 158;; Return nonzero if the code of this rtx pattern is EQ or NE. 159 160(define_predicate "equality_op" 161 (match_code "eq,ne") 162{ 163 if (mode != GET_MODE (op)) 164 return 0; 165 166 return GET_CODE (op) == EQ || GET_CODE (op) == NE; 167}) 168 169;; Return nonzero if the code is a relational operations (EQ, LE, 170;; etc). 171 172(define_predicate "cmp_op" 173 (match_code "eq,ne,gt,ge,gtu,geu,lt,le,ltu,leu") 174{ 175 if (mode != GET_MODE (op)) 176 return 0; 177 178 return COMPARISON_P (op); 179}) 180 181;; Return nonzero if the operand is either the PC or a label_ref. 182 183(define_special_predicate "pc_or_label_operand" 184 (match_code "pc,label_ref") 185{ 186 if (op == pc_rtx) 187 return 1; 188 189 if (GET_CODE (op) == LABEL_REF) 190 return 1; 191 192 return 0; 193}) 194 195;; Return nonzero if OP is a valid operand for a call instruction. 196 197(define_predicate "call_insn_operand" 198 (match_code "const_int,const,symbol_ref,reg") 199{ 200 return (CONSTANT_ADDRESS_P (op) 201 || (GET_CODE (op) == REG && op != arg_pointer_rtx 202 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER 203 && REGNO (op) <= LAST_VIRTUAL_REGISTER))); 204}) 205 206;; Return nonzero if OP is valid as a source operand for a move 207;; instruction. 208 209(define_predicate "move_operand" 210 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem") 211{ 212 /* Accept any general operand after reload has started; doing so 213 avoids losing if reload does an in-place replacement of a register 214 with a SYMBOL_REF or CONST. */ 215 return (general_operand (op, mode) 216 && (! (iq2000_check_split (op, mode)) 217 || reload_in_progress || reload_completed)); 218}) 219 220;; Return nonzero if OP is a constant power of 2. 221 222(define_predicate "power_of_2_operand" 223 (match_code "const_int") 224{ 225 int intval; 226 227 if (GET_CODE (op) != CONST_INT) 228 return 0; 229 else 230 intval = INTVAL (op); 231 232 return ((intval & ((unsigned)(intval) - 1)) == 0); 233}) 234