1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
27 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
28 /* All Rights Reserved */
29 /* */
30 /* Copyright (c) 1987, 1988 Microsoft Corporation */
31 /* All Rights Reserved */
32 /* */
33
34 #include <sys/types.h>
35 #include <sys/sysmacros.h>
36 #include <sys/param.h>
37 #include <sys/signal.h>
38 #include <sys/systm.h>
39 #include <sys/user.h>
40 #include <sys/proc.h>
41 #include <sys/disp.h>
42 #include <sys/class.h>
43 #include <sys/core.h>
44 #include <sys/syscall.h>
45 #include <sys/cpuvar.h>
46 #include <sys/vm.h>
47 #include <sys/sysinfo.h>
48 #include <sys/fault.h>
49 #include <sys/stack.h>
50 #include <sys/psw.h>
51 #include <sys/regset.h>
52 #include <sys/fp.h>
53 #include <sys/trap.h>
54 #include <sys/kmem.h>
55 #include <sys/vtrace.h>
56 #include <sys/cmn_err.h>
57 #include <sys/prsystm.h>
58 #include <sys/mutex_impl.h>
59 #include <sys/machsystm.h>
60 #include <sys/archsystm.h>
61 #include <sys/sdt.h>
62 #include <sys/avintr.h>
63 #include <sys/kobj.h>
64
65 #include <vm/hat.h>
66
67 #include <vm/seg_kmem.h>
68 #include <vm/as.h>
69 #include <vm/seg.h>
70 #include <vm/hat_pte.h>
71 #include <vm/hat_i86.h>
72
73 #include <sys/procfs.h>
74
75 #include <sys/reboot.h>
76 #include <sys/debug.h>
77 #include <sys/debugreg.h>
78 #include <sys/modctl.h>
79 #include <sys/aio_impl.h>
80 #include <sys/tnf.h>
81 #include <sys/tnf_probe.h>
82 #include <sys/cred.h>
83 #include <sys/mman.h>
84 #include <sys/x86_archext.h>
85 #include <sys/copyops.h>
86 #include <c2/audit.h>
87 #include <sys/ftrace.h>
88 #include <sys/panic.h>
89 #include <sys/traptrace.h>
90 #include <sys/ontrap.h>
91 #include <sys/cpc_impl.h>
92 #include <sys/bootconf.h>
93 #include <sys/bootinfo.h>
94 #include <sys/promif.h>
95 #include <sys/mach_mmu.h>
96 #if defined(__xpv)
97 #include <sys/hypervisor.h>
98 #endif
99 #include <sys/contract/process_impl.h>
100
101 #define USER 0x10000 /* user-mode flag added to trap type */
102
103 static const char *trap_type_mnemonic[] = {
104 "de", "db", "2", "bp",
105 "of", "br", "ud", "nm",
106 "df", "9", "ts", "np",
107 "ss", "gp", "pf", "15",
108 "mf", "ac", "mc", "xf"
109 };
110
111 static const char *trap_type[] = {
112 "Divide error", /* trap id 0 */
113 "Debug", /* trap id 1 */
114 "NMI interrupt", /* trap id 2 */
115 "Breakpoint", /* trap id 3 */
116 "Overflow", /* trap id 4 */
117 "BOUND range exceeded", /* trap id 5 */
118 "Invalid opcode", /* trap id 6 */
119 "Device not available", /* trap id 7 */
120 "Double fault", /* trap id 8 */
121 "Coprocessor segment overrun", /* trap id 9 */
122 "Invalid TSS", /* trap id 10 */
123 "Segment not present", /* trap id 11 */
124 "Stack segment fault", /* trap id 12 */
125 "General protection", /* trap id 13 */
126 "Page fault", /* trap id 14 */
127 "Reserved", /* trap id 15 */
128 "x87 floating point error", /* trap id 16 */
129 "Alignment check", /* trap id 17 */
130 "Machine check", /* trap id 18 */
131 "SIMD floating point exception", /* trap id 19 */
132 };
133
134 #define TRAP_TYPES (sizeof (trap_type) / sizeof (trap_type[0]))
135
136 #define SLOW_SCALL_SIZE 2
137 #define FAST_SCALL_SIZE 2
138
139 int tudebug = 0;
140 int tudebugbpt = 0;
141 int tudebugfpe = 0;
142 int tudebugsse = 0;
143
144 #if defined(TRAPDEBUG) || defined(lint)
145 int tdebug = 0;
146 int lodebug = 0;
147 int faultdebug = 0;
148 #else
149 #define tdebug 0
150 #define lodebug 0
151 #define faultdebug 0
152 #endif /* defined(TRAPDEBUG) || defined(lint) */
153
154 #if defined(TRAPTRACE)
155 /*
156 * trap trace record for cpu0 is allocated here.
157 * trap trace records for non-boot cpus are allocated in mp_startup_init().
158 */
159 static trap_trace_rec_t trap_tr0[TRAPTR_NENT];
160 trap_trace_ctl_t trap_trace_ctl[NCPU] = {
161 {
162 (uintptr_t)trap_tr0, /* next record */
163 (uintptr_t)trap_tr0, /* first record */
164 (uintptr_t)(trap_tr0 + TRAPTR_NENT), /* limit */
165 (uintptr_t)0 /* current */
166 },
167 };
168
169 /*
170 * default trap buffer size
171 */
172 size_t trap_trace_bufsize = TRAPTR_NENT * sizeof (trap_trace_rec_t);
173 int trap_trace_freeze = 0;
174 int trap_trace_off = 0;
175
176 /*
177 * A dummy TRAPTRACE entry to use after death.
178 */
179 trap_trace_rec_t trap_trace_postmort;
180
181 static void dump_ttrace(void);
182 #endif /* TRAPTRACE */
183 static void dumpregs(struct regs *);
184 static void showregs(uint_t, struct regs *, caddr_t);
185 static int kern_gpfault(struct regs *);
186
187 /*ARGSUSED*/
188 static int
die(uint_t type,struct regs * rp,caddr_t addr,processorid_t cpuid)189 die(uint_t type, struct regs *rp, caddr_t addr, processorid_t cpuid)
190 {
191 struct panic_trap_info ti;
192 const char *trap_name, *trap_mnemonic;
193
194 if (type < TRAP_TYPES) {
195 trap_name = trap_type[type];
196 trap_mnemonic = trap_type_mnemonic[type];
197 } else {
198 trap_name = "trap";
199 trap_mnemonic = "-";
200 }
201
202 #ifdef TRAPTRACE
203 TRAPTRACE_FREEZE;
204 #endif
205
206 ti.trap_regs = rp;
207 ti.trap_type = type & ~USER;
208 ti.trap_addr = addr;
209
210 curthread->t_panic_trap = &ti;
211
212 if (type == T_PGFLT && addr < (caddr_t)KERNELBASE) {
213 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p "
214 "occurred in module \"%s\" due to %s",
215 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr,
216 mod_containing_pc((caddr_t)rp->r_pc),
217 addr < (caddr_t)PAGESIZE ?
218 "a NULL pointer dereference" :
219 "an illegal access to a user address");
220 } else
221 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p",
222 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr);
223 return (0);
224 }
225
226 /*
227 * Rewrite the instruction at pc to be an int $T_SYSCALLINT instruction.
228 *
229 * int <vector> is two bytes: 0xCD <vector>
230 */
231
232 static int
rewrite_syscall(caddr_t pc)233 rewrite_syscall(caddr_t pc)
234 {
235 uchar_t instr[SLOW_SCALL_SIZE] = { 0xCD, T_SYSCALLINT };
236
237 if (uwrite(curthread->t_procp, instr, SLOW_SCALL_SIZE,
238 (uintptr_t)pc) != 0)
239 return (1);
240
241 return (0);
242 }
243
244 /*
245 * Test to see if the instruction at pc is sysenter or syscall. The second
246 * argument should be the x86 feature flag corresponding to the expected
247 * instruction.
248 *
249 * sysenter is two bytes: 0x0F 0x34
250 * syscall is two bytes: 0x0F 0x05
251 * int $T_SYSCALLINT is two bytes: 0xCD 0x91
252 */
253
254 static int
instr_is_other_syscall(caddr_t pc,int which)255 instr_is_other_syscall(caddr_t pc, int which)
256 {
257 uchar_t instr[FAST_SCALL_SIZE];
258
259 ASSERT(which == X86FSET_SEP || which == X86FSET_ASYSC || which == 0xCD);
260
261 if (copyin_nowatch(pc, (caddr_t)instr, FAST_SCALL_SIZE) != 0)
262 return (0);
263
264 switch (which) {
265 case X86FSET_SEP:
266 if (instr[0] == 0x0F && instr[1] == 0x34)
267 return (1);
268 break;
269 case X86FSET_ASYSC:
270 if (instr[0] == 0x0F && instr[1] == 0x05)
271 return (1);
272 break;
273 case 0xCD:
274 if (instr[0] == 0xCD && instr[1] == T_SYSCALLINT)
275 return (1);
276 break;
277 }
278
279 return (0);
280 }
281
282 static const char *
syscall_insn_string(int syscall_insn)283 syscall_insn_string(int syscall_insn)
284 {
285 switch (syscall_insn) {
286 case X86FSET_SEP:
287 return ("sysenter");
288 case X86FSET_ASYSC:
289 return ("syscall");
290 case 0xCD:
291 return ("int");
292 default:
293 return ("Unknown");
294 }
295 }
296
297 static int
ldt_rewrite_syscall(struct regs * rp,proc_t * p,int syscall_insn)298 ldt_rewrite_syscall(struct regs *rp, proc_t *p, int syscall_insn)
299 {
300 caddr_t linearpc;
301 int return_code = 0;
302
303 mutex_enter(&p->p_ldtlock); /* Must be held across linear_pc() */
304
305 if (linear_pc(rp, p, &linearpc) == 0) {
306
307 /*
308 * If another thread beat us here, it already changed
309 * this site to the slower (int) syscall instruction.
310 */
311 if (instr_is_other_syscall(linearpc, 0xCD)) {
312 return_code = 1;
313 } else if (instr_is_other_syscall(linearpc, syscall_insn)) {
314
315 if (rewrite_syscall(linearpc) == 0) {
316 return_code = 1;
317 }
318 #ifdef DEBUG
319 else
320 cmn_err(CE_WARN, "failed to rewrite %s "
321 "instruction in process %d",
322 syscall_insn_string(syscall_insn),
323 p->p_pid);
324 #endif /* DEBUG */
325 }
326 }
327
328 mutex_exit(&p->p_ldtlock); /* Must be held across linear_pc() */
329
330 return (return_code);
331 }
332
333 /*
334 * Test to see if the instruction at pc is a system call instruction.
335 *
336 * The bytes of an lcall instruction used for the syscall trap.
337 * static uchar_t lcall[7] = { 0x9a, 0, 0, 0, 0, 0x7, 0 };
338 * static uchar_t lcallalt[7] = { 0x9a, 0, 0, 0, 0, 0x27, 0 };
339 */
340
341 #define LCALLSIZE 7
342
343 static int
instr_is_lcall_syscall(caddr_t pc)344 instr_is_lcall_syscall(caddr_t pc)
345 {
346 uchar_t instr[LCALLSIZE];
347
348 if (copyin_nowatch(pc, (caddr_t)instr, LCALLSIZE) == 0 &&
349 instr[0] == 0x9a &&
350 instr[1] == 0 &&
351 instr[2] == 0 &&
352 instr[3] == 0 &&
353 instr[4] == 0 &&
354 (instr[5] == 0x7 || instr[5] == 0x27) &&
355 instr[6] == 0)
356 return (1);
357
358 return (0);
359 }
360
361 #ifdef __amd64
362
363 /*
364 * In the first revisions of amd64 CPUs produced by AMD, the LAHF and
365 * SAHF instructions were not implemented in 64-bit mode. Later revisions
366 * did implement these instructions. An extension to the cpuid instruction
367 * was added to check for the capability of executing these instructions
368 * in 64-bit mode.
369 *
370 * Intel originally did not implement these instructions in EM64T either,
371 * but added them in later revisions.
372 *
373 * So, there are different chip revisions by both vendors out there that
374 * may or may not implement these instructions. The easy solution is to
375 * just always emulate these instructions on demand.
376 *
377 * SAHF == store %ah in the lower 8 bits of %rflags (opcode 0x9e)
378 * LAHF == load the lower 8 bits of %rflags into %ah (opcode 0x9f)
379 */
380
381 #define LSAHFSIZE 1
382
383 static int
instr_is_lsahf(caddr_t pc,uchar_t * instr)384 instr_is_lsahf(caddr_t pc, uchar_t *instr)
385 {
386 if (copyin_nowatch(pc, (caddr_t)instr, LSAHFSIZE) == 0 &&
387 (*instr == 0x9e || *instr == 0x9f))
388 return (1);
389 return (0);
390 }
391
392 /*
393 * Emulate the LAHF and SAHF instructions. The reference manuals define
394 * these instructions to always load/store bit 1 as a 1, and bits 3 and 5
395 * as a 0. The other, defined, bits are copied (the PS_ICC bits and PS_P).
396 *
397 * Note that %ah is bits 8-15 of %rax.
398 */
399 static void
emulate_lsahf(struct regs * rp,uchar_t instr)400 emulate_lsahf(struct regs *rp, uchar_t instr)
401 {
402 if (instr == 0x9e) {
403 /* sahf. Copy bits from %ah to flags. */
404 rp->r_ps = (rp->r_ps & ~0xff) |
405 ((rp->r_rax >> 8) & PSL_LSAHFMASK) | PS_MB1;
406 } else {
407 /* lahf. Copy bits from flags to %ah. */
408 rp->r_rax = (rp->r_rax & ~0xff00) |
409 (((rp->r_ps & PSL_LSAHFMASK) | PS_MB1) << 8);
410 }
411 rp->r_pc += LSAHFSIZE;
412 }
413 #endif /* __amd64 */
414
415 #ifdef OPTERON_ERRATUM_91
416
417 /*
418 * Test to see if the instruction at pc is a prefetch instruction.
419 *
420 * The first byte of prefetch instructions is always 0x0F.
421 * The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch.
422 * The third byte (ModRM) contains the register field bits (bits 3-5).
423 * These bits must be between 0 and 3 inclusive for regular prefetch and
424 * 0 and 1 inclusive for AMD 3dnow prefetch.
425 *
426 * In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F).
427 */
428
429 static int
cmp_to_prefetch(uchar_t * p)430 cmp_to_prefetch(uchar_t *p)
431 {
432 #ifdef _LP64
433 if ((p[0] & 0xF0) == 0x40) /* 64-bit REX prefix */
434 p++;
435 #endif
436 return ((p[0] == 0x0F && p[1] == 0x18 && ((p[2] >> 3) & 7) <= 3) ||
437 (p[0] == 0x0F && p[1] == 0x0D && ((p[2] >> 3) & 7) <= 1));
438 }
439
440 static int
instr_is_prefetch(caddr_t pc)441 instr_is_prefetch(caddr_t pc)
442 {
443 uchar_t instr[4]; /* optional REX prefix plus 3-byte opcode */
444
445 return (copyin_nowatch(pc, instr, sizeof (instr)) == 0 &&
446 cmp_to_prefetch(instr));
447 }
448
449 #endif /* OPTERON_ERRATUM_91 */
450
451 /*
452 * Called from the trap handler when a processor trap occurs.
453 *
454 * Note: All user-level traps that might call stop() must exit
455 * trap() by 'goto out' or by falling through.
456 * Note Also: trap() is usually called with interrupts enabled, (PS_IE == 1)
457 * however, there are paths that arrive here with PS_IE == 0 so special care
458 * must be taken in those cases.
459 */
460 void
trap(struct regs * rp,caddr_t addr,processorid_t cpuid)461 trap(struct regs *rp, caddr_t addr, processorid_t cpuid)
462 {
463 kthread_t *ct = curthread;
464 enum seg_rw rw;
465 unsigned type;
466 proc_t *p = ttoproc(ct);
467 klwp_t *lwp = ttolwp(ct);
468 uintptr_t lofault;
469 faultcode_t pagefault(), res, errcode;
470 enum fault_type fault_type;
471 k_siginfo_t siginfo;
472 uint_t fault = 0;
473 int mstate;
474 int sicode = 0;
475 int watchcode;
476 int watchpage;
477 caddr_t vaddr;
478 int singlestep_twiddle;
479 size_t sz;
480 int ta;
481 #ifdef __amd64
482 uchar_t instr;
483 #endif
484
485 ASSERT_STACK_ALIGNED();
486
487 type = rp->r_trapno;
488 CPU_STATS_ADDQ(CPU, sys, trap, 1);
489 ASSERT(ct->t_schedflag & TS_DONT_SWAP);
490
491 if (type == T_PGFLT) {
492
493 errcode = rp->r_err;
494 if (errcode & PF_ERR_WRITE)
495 rw = S_WRITE;
496 else if ((caddr_t)rp->r_pc == addr ||
497 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC)))
498 rw = S_EXEC;
499 else
500 rw = S_READ;
501
502 #if defined(__i386)
503 /*
504 * Pentium Pro work-around
505 */
506 if ((errcode & PF_ERR_PROT) && pentiumpro_bug4046376) {
507 uint_t attr;
508 uint_t priv_violation;
509 uint_t access_violation;
510
511 if (hat_getattr(addr < (caddr_t)kernelbase ?
512 curproc->p_as->a_hat : kas.a_hat, addr, &attr)
513 == -1) {
514 errcode &= ~PF_ERR_PROT;
515 } else {
516 priv_violation = (errcode & PF_ERR_USER) &&
517 !(attr & PROT_USER);
518 access_violation = (errcode & PF_ERR_WRITE) &&
519 !(attr & PROT_WRITE);
520 if (!priv_violation && !access_violation)
521 goto cleanup;
522 }
523 }
524 #endif /* __i386 */
525
526 } else if (type == T_SGLSTP && lwp != NULL)
527 lwp->lwp_pcb.pcb_drstat = (uintptr_t)addr;
528
529 if (tdebug)
530 showregs(type, rp, addr);
531
532 if (USERMODE(rp->r_cs)) {
533 /*
534 * Set up the current cred to use during this trap. u_cred
535 * no longer exists. t_cred is used instead.
536 * The current process credential applies to the thread for
537 * the entire trap. If trapping from the kernel, this
538 * should already be set up.
539 */
540 if (ct->t_cred != p->p_cred) {
541 cred_t *oldcred = ct->t_cred;
542 /*
543 * DTrace accesses t_cred in probe context. t_cred
544 * must always be either NULL, or point to a valid,
545 * allocated cred structure.
546 */
547 ct->t_cred = crgetcred();
548 crfree(oldcred);
549 }
550 ASSERT(lwp != NULL);
551 type |= USER;
552 ASSERT(lwptoregs(lwp) == rp);
553 lwp->lwp_state = LWP_SYS;
554
555 switch (type) {
556 case T_PGFLT + USER:
557 if ((caddr_t)rp->r_pc == addr)
558 mstate = LMS_TFAULT;
559 else
560 mstate = LMS_DFAULT;
561 break;
562 default:
563 mstate = LMS_TRAP;
564 break;
565 }
566 /* Kernel probe */
567 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */,
568 tnf_microstate, state, mstate);
569 mstate = new_mstate(ct, mstate);
570
571 bzero(&siginfo, sizeof (siginfo));
572 }
573
574 switch (type) {
575 case T_PGFLT + USER:
576 case T_SGLSTP:
577 case T_SGLSTP + USER:
578 case T_BPTFLT + USER:
579 break;
580
581 default:
582 FTRACE_2("trap(): type=0x%lx, regs=0x%lx",
583 (ulong_t)type, (ulong_t)rp);
584 break;
585 }
586
587 switch (type) {
588 case T_SIMDFPE:
589 /* Make sure we enable interrupts before die()ing */
590 sti(); /* The SIMD exception comes in via cmninttrap */
591 /*FALLTHROUGH*/
592 default:
593 if (type & USER) {
594 if (tudebug)
595 showregs(type, rp, (caddr_t)0);
596 printf("trap: Unknown trap type %d in user mode\n",
597 type & ~USER);
598 siginfo.si_signo = SIGILL;
599 siginfo.si_code = ILL_ILLTRP;
600 siginfo.si_addr = (caddr_t)rp->r_pc;
601 siginfo.si_trapno = type & ~USER;
602 fault = FLTILL;
603 break;
604 } else {
605 (void) die(type, rp, addr, cpuid);
606 /*NOTREACHED*/
607 }
608
609 case T_PGFLT: /* system page fault */
610 /*
611 * If we're under on_trap() protection (see <sys/ontrap.h>),
612 * set ot_trap and bounce back to the on_trap() call site
613 * via the installed trampoline.
614 */
615 if ((ct->t_ontrap != NULL) &&
616 (ct->t_ontrap->ot_prot & OT_DATA_ACCESS)) {
617 ct->t_ontrap->ot_trap |= OT_DATA_ACCESS;
618 rp->r_pc = ct->t_ontrap->ot_trampoline;
619 goto cleanup;
620 }
621
622 /*
623 * See if we can handle as pagefault. Save lofault
624 * across this. Here we assume that an address
625 * less than KERNELBASE is a user fault.
626 * We can do this as copy.s routines verify that the
627 * starting address is less than KERNELBASE before
628 * starting and because we know that we always have
629 * KERNELBASE mapped as invalid to serve as a "barrier".
630 */
631 lofault = ct->t_lofault;
632 ct->t_lofault = 0;
633
634 mstate = new_mstate(ct, LMS_KFAULT);
635
636 if (addr < (caddr_t)kernelbase) {
637 res = pagefault(addr,
638 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 0);
639 if (res == FC_NOMAP &&
640 addr < p->p_usrstack &&
641 grow(addr))
642 res = 0;
643 } else {
644 res = pagefault(addr,
645 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 1);
646 }
647 (void) new_mstate(ct, mstate);
648
649 /*
650 * Restore lofault. If we resolved the fault, exit.
651 * If we didn't and lofault wasn't set, die.
652 */
653 ct->t_lofault = lofault;
654 if (res == 0)
655 goto cleanup;
656
657 #if defined(OPTERON_ERRATUM_93) && defined(_LP64)
658 if (lofault == 0 && opteron_erratum_93) {
659 /*
660 * Workaround for Opteron Erratum 93. On return from
661 * a System Managment Interrupt at a HLT instruction
662 * the %rip might be truncated to a 32 bit value.
663 * BIOS is supposed to fix this, but some don't.
664 * If this occurs we simply restore the high order bits.
665 * The HLT instruction is 1 byte of 0xf4.
666 */
667 uintptr_t rip = rp->r_pc;
668
669 if ((rip & 0xfffffffful) == rip) {
670 rip |= 0xfffffffful << 32;
671 if (hat_getpfnum(kas.a_hat, (caddr_t)rip) !=
672 PFN_INVALID &&
673 (*(uchar_t *)rip == 0xf4 ||
674 *(uchar_t *)(rip - 1) == 0xf4)) {
675 rp->r_pc = rip;
676 goto cleanup;
677 }
678 }
679 }
680 #endif /* OPTERON_ERRATUM_93 && _LP64 */
681
682 #ifdef OPTERON_ERRATUM_91
683 if (lofault == 0 && opteron_erratum_91) {
684 /*
685 * Workaround for Opteron Erratum 91. Prefetches may
686 * generate a page fault (they're not supposed to do
687 * that!). If this occurs we simply return back to the
688 * instruction.
689 */
690 caddr_t pc = (caddr_t)rp->r_pc;
691
692 /*
693 * If the faulting PC is not mapped, this is a
694 * legitimate kernel page fault that must result in a
695 * panic. If the faulting PC is mapped, it could contain
696 * a prefetch instruction. Check for that here.
697 */
698 if (hat_getpfnum(kas.a_hat, pc) != PFN_INVALID) {
699 if (cmp_to_prefetch((uchar_t *)pc)) {
700 #ifdef DEBUG
701 cmn_err(CE_WARN, "Opteron erratum 91 "
702 "occurred: kernel prefetch"
703 " at %p generated a page fault!",
704 (void *)rp->r_pc);
705 #endif /* DEBUG */
706 goto cleanup;
707 }
708 }
709 (void) die(type, rp, addr, cpuid);
710 }
711 #endif /* OPTERON_ERRATUM_91 */
712
713 if (lofault == 0)
714 (void) die(type, rp, addr, cpuid);
715
716 /*
717 * Cannot resolve fault. Return to lofault.
718 */
719 if (lodebug) {
720 showregs(type, rp, addr);
721 traceregs(rp);
722 }
723 if (FC_CODE(res) == FC_OBJERR)
724 res = FC_ERRNO(res);
725 else
726 res = EFAULT;
727 rp->r_r0 = res;
728 rp->r_pc = ct->t_lofault;
729 goto cleanup;
730
731 case T_PGFLT + USER: /* user page fault */
732 if (faultdebug) {
733 char *fault_str;
734
735 switch (rw) {
736 case S_READ:
737 fault_str = "read";
738 break;
739 case S_WRITE:
740 fault_str = "write";
741 break;
742 case S_EXEC:
743 fault_str = "exec";
744 break;
745 default:
746 fault_str = "";
747 break;
748 }
749 printf("user %s fault: addr=0x%lx errcode=0x%x\n",
750 fault_str, (uintptr_t)addr, errcode);
751 }
752
753 #if defined(OPTERON_ERRATUM_100) && defined(_LP64)
754 /*
755 * Workaround for AMD erratum 100
756 *
757 * A 32-bit process may receive a page fault on a non
758 * 32-bit address by mistake. The range of the faulting
759 * address will be
760 *
761 * 0xffffffff80000000 .. 0xffffffffffffffff or
762 * 0x0000000100000000 .. 0x000000017fffffff
763 *
764 * The fault is always due to an instruction fetch, however
765 * the value of r_pc should be correct (in 32 bit range),
766 * so we ignore the page fault on the bogus address.
767 */
768 if (p->p_model == DATAMODEL_ILP32 &&
769 (0xffffffff80000000 <= (uintptr_t)addr ||
770 (0x100000000 <= (uintptr_t)addr &&
771 (uintptr_t)addr <= 0x17fffffff))) {
772 if (!opteron_erratum_100)
773 panic("unexpected erratum #100");
774 if (rp->r_pc <= 0xffffffff)
775 goto out;
776 }
777 #endif /* OPTERON_ERRATUM_100 && _LP64 */
778
779 ASSERT(!(curthread->t_flag & T_WATCHPT));
780 watchpage = (pr_watch_active(p) && pr_is_watchpage(addr, rw));
781 #ifdef __i386
782 /*
783 * In 32-bit mode, the lcall (system call) instruction fetches
784 * one word from the stack, at the stack pointer, because of the
785 * way the call gate is constructed. This is a bogus
786 * read and should not be counted as a read watchpoint.
787 * We work around the problem here by testing to see if
788 * this situation applies and, if so, simply jumping to
789 * the code in locore.s that fields the system call trap.
790 * The registers on the stack are already set up properly
791 * due to the match between the call gate sequence and the
792 * trap gate sequence. We just have to adjust the pc.
793 */
794 if (watchpage && addr == (caddr_t)rp->r_sp &&
795 rw == S_READ && instr_is_lcall_syscall((caddr_t)rp->r_pc)) {
796 extern void watch_syscall(void);
797
798 rp->r_pc += LCALLSIZE;
799 watch_syscall(); /* never returns */
800 /* NOTREACHED */
801 }
802 #endif /* __i386 */
803 vaddr = addr;
804 if (!watchpage || (sz = instr_size(rp, &vaddr, rw)) <= 0)
805 fault_type = (errcode & PF_ERR_PROT)? F_PROT: F_INVAL;
806 else if ((watchcode = pr_is_watchpoint(&vaddr, &ta,
807 sz, NULL, rw)) != 0) {
808 if (ta) {
809 do_watch_step(vaddr, sz, rw,
810 watchcode, rp->r_pc);
811 fault_type = F_INVAL;
812 } else {
813 bzero(&siginfo, sizeof (siginfo));
814 siginfo.si_signo = SIGTRAP;
815 siginfo.si_code = watchcode;
816 siginfo.si_addr = vaddr;
817 siginfo.si_trapafter = 0;
818 siginfo.si_pc = (caddr_t)rp->r_pc;
819 fault = FLTWATCH;
820 break;
821 }
822 } else {
823 /* XXX pr_watch_emul() never succeeds (for now) */
824 if (rw != S_EXEC && pr_watch_emul(rp, vaddr, rw))
825 goto out;
826 do_watch_step(vaddr, sz, rw, 0, 0);
827 fault_type = F_INVAL;
828 }
829
830 res = pagefault(addr, fault_type, rw, 0);
831
832 /*
833 * If pagefault() succeeded, ok.
834 * Otherwise attempt to grow the stack.
835 */
836 if (res == 0 ||
837 (res == FC_NOMAP &&
838 addr < p->p_usrstack &&
839 grow(addr))) {
840 lwp->lwp_lastfault = FLTPAGE;
841 lwp->lwp_lastfaddr = addr;
842 if (prismember(&p->p_fltmask, FLTPAGE)) {
843 bzero(&siginfo, sizeof (siginfo));
844 siginfo.si_addr = addr;
845 (void) stop_on_fault(FLTPAGE, &siginfo);
846 }
847 goto out;
848 } else if (res == FC_PROT && addr < p->p_usrstack &&
849 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) {
850 report_stack_exec(p, addr);
851 }
852
853 #ifdef OPTERON_ERRATUM_91
854 /*
855 * Workaround for Opteron Erratum 91. Prefetches may generate a
856 * page fault (they're not supposed to do that!). If this
857 * occurs we simply return back to the instruction.
858 *
859 * We rely on copyin to properly fault in the page with r_pc.
860 */
861 if (opteron_erratum_91 &&
862 addr != (caddr_t)rp->r_pc &&
863 instr_is_prefetch((caddr_t)rp->r_pc)) {
864 #ifdef DEBUG
865 cmn_err(CE_WARN, "Opteron erratum 91 occurred: "
866 "prefetch at %p in pid %d generated a trap!",
867 (void *)rp->r_pc, p->p_pid);
868 #endif /* DEBUG */
869 goto out;
870 }
871 #endif /* OPTERON_ERRATUM_91 */
872
873 if (tudebug)
874 showregs(type, rp, addr);
875 /*
876 * In the case where both pagefault and grow fail,
877 * set the code to the value provided by pagefault.
878 * We map all errors returned from pagefault() to SIGSEGV.
879 */
880 bzero(&siginfo, sizeof (siginfo));
881 siginfo.si_addr = addr;
882 switch (FC_CODE(res)) {
883 case FC_HWERR:
884 case FC_NOSUPPORT:
885 siginfo.si_signo = SIGBUS;
886 siginfo.si_code = BUS_ADRERR;
887 fault = FLTACCESS;
888 break;
889 case FC_ALIGN:
890 siginfo.si_signo = SIGBUS;
891 siginfo.si_code = BUS_ADRALN;
892 fault = FLTACCESS;
893 break;
894 case FC_OBJERR:
895 if ((siginfo.si_errno = FC_ERRNO(res)) != EINTR) {
896 siginfo.si_signo = SIGBUS;
897 siginfo.si_code = BUS_OBJERR;
898 fault = FLTACCESS;
899 }
900 break;
901 default: /* FC_NOMAP or FC_PROT */
902 siginfo.si_signo = SIGSEGV;
903 siginfo.si_code =
904 (res == FC_NOMAP)? SEGV_MAPERR : SEGV_ACCERR;
905 fault = FLTBOUNDS;
906 break;
907 }
908 break;
909
910 case T_ILLINST + USER: /* invalid opcode fault */
911 /*
912 * If the syscall instruction is disabled due to LDT usage, a
913 * user program that attempts to execute it will trigger a #ud
914 * trap. Check for that case here. If this occurs on a CPU which
915 * doesn't even support syscall, the result of all of this will
916 * be to emulate that particular instruction.
917 */
918 if (p->p_ldt != NULL &&
919 ldt_rewrite_syscall(rp, p, X86FSET_ASYSC))
920 goto out;
921
922 #ifdef __amd64
923 /*
924 * Emulate the LAHF and SAHF instructions if needed.
925 * See the instr_is_lsahf function for details.
926 */
927 if (p->p_model == DATAMODEL_LP64 &&
928 instr_is_lsahf((caddr_t)rp->r_pc, &instr)) {
929 emulate_lsahf(rp, instr);
930 goto out;
931 }
932 #endif
933
934 /*FALLTHROUGH*/
935
936 if (tudebug)
937 showregs(type, rp, (caddr_t)0);
938 siginfo.si_signo = SIGILL;
939 siginfo.si_code = ILL_ILLOPC;
940 siginfo.si_addr = (caddr_t)rp->r_pc;
941 fault = FLTILL;
942 break;
943
944 case T_ZERODIV + USER: /* integer divide by zero */
945 if (tudebug && tudebugfpe)
946 showregs(type, rp, (caddr_t)0);
947 siginfo.si_signo = SIGFPE;
948 siginfo.si_code = FPE_INTDIV;
949 siginfo.si_addr = (caddr_t)rp->r_pc;
950 fault = FLTIZDIV;
951 break;
952
953 case T_OVFLW + USER: /* integer overflow */
954 if (tudebug && tudebugfpe)
955 showregs(type, rp, (caddr_t)0);
956 siginfo.si_signo = SIGFPE;
957 siginfo.si_code = FPE_INTOVF;
958 siginfo.si_addr = (caddr_t)rp->r_pc;
959 fault = FLTIOVF;
960 break;
961
962 case T_NOEXTFLT + USER: /* math coprocessor not available */
963 if (tudebug && tudebugfpe)
964 showregs(type, rp, addr);
965 if (fpnoextflt(rp)) {
966 siginfo.si_signo = SIGILL;
967 siginfo.si_code = ILL_ILLOPC;
968 siginfo.si_addr = (caddr_t)rp->r_pc;
969 fault = FLTILL;
970 }
971 break;
972
973 case T_EXTOVRFLT: /* extension overrun fault */
974 /* check if we took a kernel trap on behalf of user */
975 {
976 extern void ndptrap_frstor(void);
977 if (rp->r_pc != (uintptr_t)ndptrap_frstor) {
978 sti(); /* T_EXTOVRFLT comes in via cmninttrap */
979 (void) die(type, rp, addr, cpuid);
980 }
981 type |= USER;
982 }
983 /*FALLTHROUGH*/
984 case T_EXTOVRFLT + USER: /* extension overrun fault */
985 if (tudebug && tudebugfpe)
986 showregs(type, rp, addr);
987 if (fpextovrflt(rp)) {
988 siginfo.si_signo = SIGSEGV;
989 siginfo.si_code = SEGV_MAPERR;
990 siginfo.si_addr = (caddr_t)rp->r_pc;
991 fault = FLTBOUNDS;
992 }
993 break;
994
995 case T_EXTERRFLT: /* x87 floating point exception pending */
996 /* check if we took a kernel trap on behalf of user */
997 {
998 extern void ndptrap_frstor(void);
999 if (rp->r_pc != (uintptr_t)ndptrap_frstor) {
1000 sti(); /* T_EXTERRFLT comes in via cmninttrap */
1001 (void) die(type, rp, addr, cpuid);
1002 }
1003 type |= USER;
1004 }
1005 /*FALLTHROUGH*/
1006
1007 case T_EXTERRFLT + USER: /* x87 floating point exception pending */
1008 if (tudebug && tudebugfpe)
1009 showregs(type, rp, addr);
1010 if (sicode = fpexterrflt(rp)) {
1011 siginfo.si_signo = SIGFPE;
1012 siginfo.si_code = sicode;
1013 siginfo.si_addr = (caddr_t)rp->r_pc;
1014 fault = FLTFPE;
1015 }
1016 break;
1017
1018 case T_SIMDFPE + USER: /* SSE and SSE2 exceptions */
1019 if (tudebug && tudebugsse)
1020 showregs(type, rp, addr);
1021 if (!is_x86_feature(x86_featureset, X86FSET_SSE) &&
1022 !is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1023 /*
1024 * There are rumours that some user instructions
1025 * on older CPUs can cause this trap to occur; in
1026 * which case send a SIGILL instead of a SIGFPE.
1027 */
1028 siginfo.si_signo = SIGILL;
1029 siginfo.si_code = ILL_ILLTRP;
1030 siginfo.si_addr = (caddr_t)rp->r_pc;
1031 siginfo.si_trapno = type & ~USER;
1032 fault = FLTILL;
1033 } else if ((sicode = fpsimderrflt(rp)) != 0) {
1034 siginfo.si_signo = SIGFPE;
1035 siginfo.si_code = sicode;
1036 siginfo.si_addr = (caddr_t)rp->r_pc;
1037 fault = FLTFPE;
1038 }
1039
1040 sti(); /* The SIMD exception comes in via cmninttrap */
1041 break;
1042
1043 case T_BPTFLT: /* breakpoint trap */
1044 /*
1045 * Kernel breakpoint traps should only happen when kmdb is
1046 * active, and even then, it'll have interposed on the IDT, so
1047 * control won't get here. If it does, we've hit a breakpoint
1048 * without the debugger, which is very strange, and very
1049 * fatal.
1050 */
1051 if (tudebug && tudebugbpt)
1052 showregs(type, rp, (caddr_t)0);
1053
1054 (void) die(type, rp, addr, cpuid);
1055 break;
1056
1057 case T_SGLSTP: /* single step/hw breakpoint exception */
1058
1059 /* Now evaluate how we got here */
1060 if (lwp != NULL && (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP)) {
1061 /*
1062 * i386 single-steps even through lcalls which
1063 * change the privilege level. So we take a trap at
1064 * the first instruction in privileged mode.
1065 *
1066 * Set a flag to indicate that upon completion of
1067 * the system call, deal with the single-step trap.
1068 *
1069 * The same thing happens for sysenter, too.
1070 */
1071 singlestep_twiddle = 0;
1072 if (rp->r_pc == (uintptr_t)sys_sysenter ||
1073 rp->r_pc == (uintptr_t)brand_sys_sysenter) {
1074 singlestep_twiddle = 1;
1075 #if defined(__amd64)
1076 /*
1077 * Since we are already on the kernel's
1078 * %gs, on 64-bit systems the sysenter case
1079 * needs to adjust the pc to avoid
1080 * executing the swapgs instruction at the
1081 * top of the handler.
1082 */
1083 if (rp->r_pc == (uintptr_t)sys_sysenter)
1084 rp->r_pc = (uintptr_t)
1085 _sys_sysenter_post_swapgs;
1086 else
1087 rp->r_pc = (uintptr_t)
1088 _brand_sys_sysenter_post_swapgs;
1089 #endif
1090 }
1091 #if defined(__i386)
1092 else if (rp->r_pc == (uintptr_t)sys_call ||
1093 rp->r_pc == (uintptr_t)brand_sys_call) {
1094 singlestep_twiddle = 1;
1095 }
1096 #endif
1097 else {
1098 /* not on sysenter/syscall; uregs available */
1099 if (tudebug && tudebugbpt)
1100 showregs(type, rp, (caddr_t)0);
1101 }
1102 if (singlestep_twiddle) {
1103 rp->r_ps &= ~PS_T; /* turn off trace */
1104 lwp->lwp_pcb.pcb_flags |= DEBUG_PENDING;
1105 ct->t_post_sys = 1;
1106 aston(curthread);
1107 goto cleanup;
1108 }
1109 }
1110 /* XXX - needs review on debugger interface? */
1111 if (boothowto & RB_DEBUG)
1112 debug_enter((char *)NULL);
1113 else
1114 (void) die(type, rp, addr, cpuid);
1115 break;
1116
1117 case T_NMIFLT: /* NMI interrupt */
1118 printf("Unexpected NMI in system mode\n");
1119 goto cleanup;
1120
1121 case T_NMIFLT + USER: /* NMI interrupt */
1122 printf("Unexpected NMI in user mode\n");
1123 break;
1124
1125 case T_GPFLT: /* general protection violation */
1126 /*
1127 * Any #GP that occurs during an on_trap .. no_trap bracket
1128 * with OT_DATA_ACCESS or OT_SEGMENT_ACCESS protection,
1129 * or in a on_fault .. no_fault bracket, is forgiven
1130 * and we trampoline. This protection is given regardless
1131 * of whether we are 32/64 bit etc - if a distinction is
1132 * required then define new on_trap protection types.
1133 *
1134 * On amd64, we can get a #gp from referencing addresses
1135 * in the virtual address hole e.g. from a copyin or in
1136 * update_sregs while updating user segment registers.
1137 *
1138 * On the 32-bit hypervisor we could also generate one in
1139 * mfn_to_pfn by reaching around or into where the hypervisor
1140 * lives which is protected by segmentation.
1141 */
1142
1143 /*
1144 * If we're under on_trap() protection (see <sys/ontrap.h>),
1145 * set ot_trap and trampoline back to the on_trap() call site
1146 * for OT_DATA_ACCESS or OT_SEGMENT_ACCESS.
1147 */
1148 if (ct->t_ontrap != NULL) {
1149 int ttype = ct->t_ontrap->ot_prot &
1150 (OT_DATA_ACCESS | OT_SEGMENT_ACCESS);
1151
1152 if (ttype != 0) {
1153 ct->t_ontrap->ot_trap |= ttype;
1154 if (tudebug)
1155 showregs(type, rp, (caddr_t)0);
1156 rp->r_pc = ct->t_ontrap->ot_trampoline;
1157 goto cleanup;
1158 }
1159 }
1160
1161 /*
1162 * If we're under lofault protection (copyin etc.),
1163 * longjmp back to lofault with an EFAULT.
1164 */
1165 if (ct->t_lofault) {
1166 /*
1167 * Fault is not resolvable, so just return to lofault
1168 */
1169 if (lodebug) {
1170 showregs(type, rp, addr);
1171 traceregs(rp);
1172 }
1173 rp->r_r0 = EFAULT;
1174 rp->r_pc = ct->t_lofault;
1175 goto cleanup;
1176 }
1177
1178 /*
1179 * We fall through to the next case, which repeats
1180 * the OT_SEGMENT_ACCESS check which we've already
1181 * done, so we'll always fall through to the
1182 * T_STKFLT case.
1183 */
1184 /*FALLTHROUGH*/
1185 case T_SEGFLT: /* segment not present fault */
1186 /*
1187 * One example of this is #NP in update_sregs while
1188 * attempting to update a user segment register
1189 * that points to a descriptor that is marked not
1190 * present.
1191 */
1192 if (ct->t_ontrap != NULL &&
1193 ct->t_ontrap->ot_prot & OT_SEGMENT_ACCESS) {
1194 ct->t_ontrap->ot_trap |= OT_SEGMENT_ACCESS;
1195 if (tudebug)
1196 showregs(type, rp, (caddr_t)0);
1197 rp->r_pc = ct->t_ontrap->ot_trampoline;
1198 goto cleanup;
1199 }
1200 /*FALLTHROUGH*/
1201 case T_STKFLT: /* stack fault */
1202 case T_TSSFLT: /* invalid TSS fault */
1203 if (tudebug)
1204 showregs(type, rp, (caddr_t)0);
1205 if (kern_gpfault(rp))
1206 (void) die(type, rp, addr, cpuid);
1207 goto cleanup;
1208
1209 /*
1210 * ONLY 32-bit PROCESSES can USE a PRIVATE LDT! 64-bit apps
1211 * should have no need for them, so we put a stop to it here.
1212 *
1213 * So: not-present fault is ONLY valid for 32-bit processes with
1214 * a private LDT trying to do a system call. Emulate it.
1215 *
1216 * #gp fault is ONLY valid for 32-bit processes also, which DO NOT
1217 * have a private LDT, and are trying to do a system call. Emulate it.
1218 */
1219
1220 case T_SEGFLT + USER: /* segment not present fault */
1221 case T_GPFLT + USER: /* general protection violation */
1222 #ifdef _SYSCALL32_IMPL
1223 if (p->p_model != DATAMODEL_NATIVE) {
1224 #endif /* _SYSCALL32_IMPL */
1225 if (instr_is_lcall_syscall((caddr_t)rp->r_pc)) {
1226 if (type == T_SEGFLT + USER)
1227 ASSERT(p->p_ldt != NULL);
1228
1229 if ((p->p_ldt == NULL && type == T_GPFLT + USER) ||
1230 type == T_SEGFLT + USER) {
1231
1232 /*
1233 * The user attempted a system call via the obsolete
1234 * call gate mechanism. Because the process doesn't have
1235 * an LDT (i.e. the ldtr contains 0), a #gp results.
1236 * Emulate the syscall here, just as we do above for a
1237 * #np trap.
1238 */
1239
1240 /*
1241 * Since this is a not-present trap, rp->r_pc points to
1242 * the trapping lcall instruction. We need to bump it
1243 * to the next insn so the app can continue on.
1244 */
1245 rp->r_pc += LCALLSIZE;
1246 lwp->lwp_regs = rp;
1247
1248 /*
1249 * Normally the microstate of the LWP is forced back to
1250 * LMS_USER by the syscall handlers. Emulate that
1251 * behavior here.
1252 */
1253 mstate = LMS_USER;
1254
1255 dosyscall();
1256 goto out;
1257 }
1258 }
1259 #ifdef _SYSCALL32_IMPL
1260 }
1261 #endif /* _SYSCALL32_IMPL */
1262 /*
1263 * If the current process is using a private LDT and the
1264 * trapping instruction is sysenter, the sysenter instruction
1265 * has been disabled on the CPU because it destroys segment
1266 * registers. If this is the case, rewrite the instruction to
1267 * be a safe system call and retry it. If this occurs on a CPU
1268 * which doesn't even support sysenter, the result of all of
1269 * this will be to emulate that particular instruction.
1270 */
1271 if (p->p_ldt != NULL &&
1272 ldt_rewrite_syscall(rp, p, X86FSET_SEP))
1273 goto out;
1274
1275 /*FALLTHROUGH*/
1276
1277 case T_BOUNDFLT + USER: /* bound fault */
1278 case T_STKFLT + USER: /* stack fault */
1279 case T_TSSFLT + USER: /* invalid TSS fault */
1280 if (tudebug)
1281 showregs(type, rp, (caddr_t)0);
1282 siginfo.si_signo = SIGSEGV;
1283 siginfo.si_code = SEGV_MAPERR;
1284 siginfo.si_addr = (caddr_t)rp->r_pc;
1285 fault = FLTBOUNDS;
1286 break;
1287
1288 case T_ALIGNMENT + USER: /* user alignment error (486) */
1289 if (tudebug)
1290 showregs(type, rp, (caddr_t)0);
1291 bzero(&siginfo, sizeof (siginfo));
1292 siginfo.si_signo = SIGBUS;
1293 siginfo.si_code = BUS_ADRALN;
1294 siginfo.si_addr = (caddr_t)rp->r_pc;
1295 fault = FLTACCESS;
1296 break;
1297
1298 case T_SGLSTP + USER: /* single step/hw breakpoint exception */
1299 if (tudebug && tudebugbpt)
1300 showregs(type, rp, (caddr_t)0);
1301
1302 /* Was it single-stepping? */
1303 if (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP) {
1304 pcb_t *pcb = &lwp->lwp_pcb;
1305
1306 rp->r_ps &= ~PS_T;
1307 /*
1308 * If both NORMAL_STEP and WATCH_STEP are in effect,
1309 * give precedence to WATCH_STEP. If neither is set,
1310 * user must have set the PS_T bit in %efl; treat this
1311 * as NORMAL_STEP.
1312 */
1313 if ((fault = undo_watch_step(&siginfo)) == 0 &&
1314 ((pcb->pcb_flags & NORMAL_STEP) ||
1315 !(pcb->pcb_flags & WATCH_STEP))) {
1316 siginfo.si_signo = SIGTRAP;
1317 siginfo.si_code = TRAP_TRACE;
1318 siginfo.si_addr = (caddr_t)rp->r_pc;
1319 fault = FLTTRACE;
1320 }
1321 pcb->pcb_flags &= ~(NORMAL_STEP|WATCH_STEP);
1322 }
1323 break;
1324
1325 case T_BPTFLT + USER: /* breakpoint trap */
1326 if (tudebug && tudebugbpt)
1327 showregs(type, rp, (caddr_t)0);
1328 /*
1329 * int 3 (the breakpoint instruction) leaves the pc referring
1330 * to the address one byte after the breakpointed address.
1331 * If the P_PR_BPTADJ flag has been set via /proc, We adjust
1332 * it back so it refers to the breakpointed address.
1333 */
1334 if (p->p_proc_flag & P_PR_BPTADJ)
1335 rp->r_pc--;
1336 siginfo.si_signo = SIGTRAP;
1337 siginfo.si_code = TRAP_BRKPT;
1338 siginfo.si_addr = (caddr_t)rp->r_pc;
1339 fault = FLTBPT;
1340 break;
1341
1342 case T_AST:
1343 /*
1344 * This occurs only after the cs register has been made to
1345 * look like a kernel selector, either through debugging or
1346 * possibly by functions like setcontext(). The thread is
1347 * about to cause a general protection fault at common_iret()
1348 * in locore. We let that happen immediately instead of
1349 * doing the T_AST processing.
1350 */
1351 goto cleanup;
1352
1353 case T_AST + USER: /* profiling, resched, h/w error pseudo trap */
1354 if (lwp->lwp_pcb.pcb_flags & ASYNC_HWERR) {
1355 proc_t *p = ttoproc(curthread);
1356 extern void print_msg_hwerr(ctid_t ct_id, proc_t *p);
1357
1358 lwp->lwp_pcb.pcb_flags &= ~ASYNC_HWERR;
1359 print_msg_hwerr(p->p_ct_process->conp_contract.ct_id,
1360 p);
1361 contract_process_hwerr(p->p_ct_process, p);
1362 siginfo.si_signo = SIGKILL;
1363 siginfo.si_code = SI_NOINFO;
1364 } else if (lwp->lwp_pcb.pcb_flags & CPC_OVERFLOW) {
1365 lwp->lwp_pcb.pcb_flags &= ~CPC_OVERFLOW;
1366 if (kcpc_overflow_ast()) {
1367 /*
1368 * Signal performance counter overflow
1369 */
1370 if (tudebug)
1371 showregs(type, rp, (caddr_t)0);
1372 bzero(&siginfo, sizeof (siginfo));
1373 siginfo.si_signo = SIGEMT;
1374 siginfo.si_code = EMT_CPCOVF;
1375 siginfo.si_addr = (caddr_t)rp->r_pc;
1376 fault = FLTCPCOVF;
1377 }
1378 }
1379
1380 break;
1381 }
1382
1383 /*
1384 * We can't get here from a system trap
1385 */
1386 ASSERT(type & USER);
1387
1388 if (fault) {
1389 /* We took a fault so abort single step. */
1390 lwp->lwp_pcb.pcb_flags &= ~(NORMAL_STEP|WATCH_STEP);
1391 /*
1392 * Remember the fault and fault adddress
1393 * for real-time (SIGPROF) profiling.
1394 */
1395 lwp->lwp_lastfault = fault;
1396 lwp->lwp_lastfaddr = siginfo.si_addr;
1397
1398 DTRACE_PROC2(fault, int, fault, ksiginfo_t *, &siginfo);
1399
1400 /*
1401 * If a debugger has declared this fault to be an
1402 * event of interest, stop the lwp. Otherwise just
1403 * deliver the associated signal.
1404 */
1405 if (siginfo.si_signo != SIGKILL &&
1406 prismember(&p->p_fltmask, fault) &&
1407 stop_on_fault(fault, &siginfo) == 0)
1408 siginfo.si_signo = 0;
1409 }
1410
1411 if (siginfo.si_signo)
1412 trapsig(&siginfo, (fault != FLTFPE && fault != FLTCPCOVF));
1413
1414 if (lwp->lwp_oweupc)
1415 profil_tick(rp->r_pc);
1416
1417 if (ct->t_astflag | ct->t_sig_check) {
1418 /*
1419 * Turn off the AST flag before checking all the conditions that
1420 * may have caused an AST. This flag is on whenever a signal or
1421 * unusual condition should be handled after the next trap or
1422 * syscall.
1423 */
1424 astoff(ct);
1425 /*
1426 * If a single-step trap occurred on a syscall (see above)
1427 * recognize it now. Do this before checking for signals
1428 * because deferred_singlestep_trap() may generate a SIGTRAP to
1429 * the LWP or may otherwise mark the LWP to call issig(FORREAL).
1430 */
1431 if (lwp->lwp_pcb.pcb_flags & DEBUG_PENDING)
1432 deferred_singlestep_trap((caddr_t)rp->r_pc);
1433
1434 ct->t_sig_check = 0;
1435
1436 mutex_enter(&p->p_lock);
1437 if (curthread->t_proc_flag & TP_CHANGEBIND) {
1438 timer_lwpbind();
1439 curthread->t_proc_flag &= ~TP_CHANGEBIND;
1440 }
1441 mutex_exit(&p->p_lock);
1442
1443 /*
1444 * for kaio requests that are on the per-process poll queue,
1445 * aiop->aio_pollq, they're AIO_POLL bit is set, the kernel
1446 * should copyout their result_t to user memory. by copying
1447 * out the result_t, the user can poll on memory waiting
1448 * for the kaio request to complete.
1449 */
1450 if (p->p_aio)
1451 aio_cleanup(0);
1452 /*
1453 * If this LWP was asked to hold, call holdlwp(), which will
1454 * stop. holdlwps() sets this up and calls pokelwps() which
1455 * sets the AST flag.
1456 *
1457 * Also check TP_EXITLWP, since this is used by fresh new LWPs
1458 * through lwp_rtt(). That flag is set if the lwp_create(2)
1459 * syscall failed after creating the LWP.
1460 */
1461 if (ISHOLD(p))
1462 holdlwp();
1463
1464 /*
1465 * All code that sets signals and makes ISSIG evaluate true must
1466 * set t_astflag afterwards.
1467 */
1468 if (ISSIG_PENDING(ct, lwp, p)) {
1469 if (issig(FORREAL))
1470 psig();
1471 ct->t_sig_check = 1;
1472 }
1473
1474 if (ct->t_rprof != NULL) {
1475 realsigprof(0, 0, 0);
1476 ct->t_sig_check = 1;
1477 }
1478
1479 /*
1480 * /proc can't enable/disable the trace bit itself
1481 * because that could race with the call gate used by
1482 * system calls via "lcall". If that happened, an
1483 * invalid EFLAGS would result. prstep()/prnostep()
1484 * therefore schedule an AST for the purpose.
1485 */
1486 if (lwp->lwp_pcb.pcb_flags & REQUEST_STEP) {
1487 lwp->lwp_pcb.pcb_flags &= ~REQUEST_STEP;
1488 rp->r_ps |= PS_T;
1489 }
1490 if (lwp->lwp_pcb.pcb_flags & REQUEST_NOSTEP) {
1491 lwp->lwp_pcb.pcb_flags &= ~REQUEST_NOSTEP;
1492 rp->r_ps &= ~PS_T;
1493 }
1494 }
1495
1496 out: /* We can't get here from a system trap */
1497 ASSERT(type & USER);
1498
1499 if (ISHOLD(p))
1500 holdlwp();
1501
1502 /*
1503 * Set state to LWP_USER here so preempt won't give us a kernel
1504 * priority if it occurs after this point. Call CL_TRAPRET() to
1505 * restore the user-level priority.
1506 *
1507 * It is important that no locks (other than spinlocks) be entered
1508 * after this point before returning to user mode (unless lwp_state
1509 * is set back to LWP_SYS).
1510 */
1511 lwp->lwp_state = LWP_USER;
1512
1513 if (ct->t_trapret) {
1514 ct->t_trapret = 0;
1515 thread_lock(ct);
1516 CL_TRAPRET(ct);
1517 thread_unlock(ct);
1518 }
1519 if (CPU->cpu_runrun || curthread->t_schedflag & TS_ANYWAITQ)
1520 preempt();
1521 prunstop();
1522 (void) new_mstate(ct, mstate);
1523
1524 /* Kernel probe */
1525 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */,
1526 tnf_microstate, state, LMS_USER);
1527
1528 return;
1529
1530 cleanup: /* system traps end up here */
1531 ASSERT(!(type & USER));
1532 }
1533
1534 /*
1535 * Patch non-zero to disable preemption of threads in the kernel.
1536 */
1537 int IGNORE_KERNEL_PREEMPTION = 0; /* XXX - delete this someday */
1538
1539 struct kpreempt_cnts { /* kernel preemption statistics */
1540 int kpc_idle; /* executing idle thread */
1541 int kpc_intr; /* executing interrupt thread */
1542 int kpc_clock; /* executing clock thread */
1543 int kpc_blocked; /* thread has blocked preemption (t_preempt) */
1544 int kpc_notonproc; /* thread is surrendering processor */
1545 int kpc_inswtch; /* thread has ratified scheduling decision */
1546 int kpc_prilevel; /* processor interrupt level is too high */
1547 int kpc_apreempt; /* asynchronous preemption */
1548 int kpc_spreempt; /* synchronous preemption */
1549 } kpreempt_cnts;
1550
1551 /*
1552 * kernel preemption: forced rescheduling, preempt the running kernel thread.
1553 * the argument is old PIL for an interrupt,
1554 * or the distingished value KPREEMPT_SYNC.
1555 */
1556 void
kpreempt(int asyncspl)1557 kpreempt(int asyncspl)
1558 {
1559 kthread_t *ct = curthread;
1560
1561 if (IGNORE_KERNEL_PREEMPTION) {
1562 aston(CPU->cpu_dispthread);
1563 return;
1564 }
1565
1566 /*
1567 * Check that conditions are right for kernel preemption
1568 */
1569 do {
1570 if (ct->t_preempt) {
1571 /*
1572 * either a privileged thread (idle, panic, interrupt)
1573 * or will check when t_preempt is lowered
1574 * We need to specifically handle the case where
1575 * the thread is in the middle of swtch (resume has
1576 * been called) and has its t_preempt set
1577 * [idle thread and a thread which is in kpreempt
1578 * already] and then a high priority thread is
1579 * available in the local dispatch queue.
1580 * In this case the resumed thread needs to take a
1581 * trap so that it can call kpreempt. We achieve
1582 * this by using siron().
1583 * How do we detect this condition:
1584 * idle thread is running and is in the midst of
1585 * resume: curthread->t_pri == -1 && CPU->dispthread
1586 * != CPU->thread
1587 * Need to ensure that this happens only at high pil
1588 * resume is called at high pil
1589 * Only in resume_from_idle is the pil changed.
1590 */
1591 if (ct->t_pri < 0) {
1592 kpreempt_cnts.kpc_idle++;
1593 if (CPU->cpu_dispthread != CPU->cpu_thread)
1594 siron();
1595 } else if (ct->t_flag & T_INTR_THREAD) {
1596 kpreempt_cnts.kpc_intr++;
1597 if (ct->t_pil == CLOCK_LEVEL)
1598 kpreempt_cnts.kpc_clock++;
1599 } else {
1600 kpreempt_cnts.kpc_blocked++;
1601 if (CPU->cpu_dispthread != CPU->cpu_thread)
1602 siron();
1603 }
1604 aston(CPU->cpu_dispthread);
1605 return;
1606 }
1607 if (ct->t_state != TS_ONPROC ||
1608 ct->t_disp_queue != CPU->cpu_disp) {
1609 /* this thread will be calling swtch() shortly */
1610 kpreempt_cnts.kpc_notonproc++;
1611 if (CPU->cpu_thread != CPU->cpu_dispthread) {
1612 /* already in swtch(), force another */
1613 kpreempt_cnts.kpc_inswtch++;
1614 siron();
1615 }
1616 return;
1617 }
1618 if (getpil() >= DISP_LEVEL) {
1619 /*
1620 * We can't preempt this thread if it is at
1621 * a PIL >= DISP_LEVEL since it may be holding
1622 * a spin lock (like sched_lock).
1623 */
1624 siron(); /* check back later */
1625 kpreempt_cnts.kpc_prilevel++;
1626 return;
1627 }
1628 if (!interrupts_enabled()) {
1629 /*
1630 * Can't preempt while running with ints disabled
1631 */
1632 kpreempt_cnts.kpc_prilevel++;
1633 return;
1634 }
1635 if (asyncspl != KPREEMPT_SYNC)
1636 kpreempt_cnts.kpc_apreempt++;
1637 else
1638 kpreempt_cnts.kpc_spreempt++;
1639
1640 ct->t_preempt++;
1641 preempt();
1642 ct->t_preempt--;
1643 } while (CPU->cpu_kprunrun);
1644 }
1645
1646 /*
1647 * Print out debugging info.
1648 */
1649 static void
showregs(uint_t type,struct regs * rp,caddr_t addr)1650 showregs(uint_t type, struct regs *rp, caddr_t addr)
1651 {
1652 int s;
1653
1654 s = spl7();
1655 type &= ~USER;
1656 if (PTOU(curproc)->u_comm[0])
1657 printf("%s: ", PTOU(curproc)->u_comm);
1658 if (type < TRAP_TYPES)
1659 printf("#%s %s\n", trap_type_mnemonic[type], trap_type[type]);
1660 else
1661 switch (type) {
1662 case T_SYSCALL:
1663 printf("Syscall Trap:\n");
1664 break;
1665 case T_AST:
1666 printf("AST\n");
1667 break;
1668 default:
1669 printf("Bad Trap = %d\n", type);
1670 break;
1671 }
1672 if (type == T_PGFLT) {
1673 printf("Bad %s fault at addr=0x%lx\n",
1674 USERMODE(rp->r_cs) ? "user": "kernel", (uintptr_t)addr);
1675 } else if (addr) {
1676 printf("addr=0x%lx\n", (uintptr_t)addr);
1677 }
1678
1679 printf("pid=%d, pc=0x%lx, sp=0x%lx, eflags=0x%lx\n",
1680 (ttoproc(curthread) && ttoproc(curthread)->p_pidp) ?
1681 ttoproc(curthread)->p_pid : 0, rp->r_pc, rp->r_sp, rp->r_ps);
1682
1683 #if defined(__lint)
1684 /*
1685 * this clause can be deleted when lint bug 4870403 is fixed
1686 * (lint thinks that bit 32 is illegal in a %b format string)
1687 */
1688 printf("cr0: %x cr4: %b\n",
1689 (uint_t)getcr0(), (uint_t)getcr4(), FMT_CR4);
1690 #else
1691 printf("cr0: %b cr4: %b\n",
1692 (uint_t)getcr0(), FMT_CR0, (uint_t)getcr4(), FMT_CR4);
1693 #endif /* __lint */
1694
1695 printf("cr2: %lx", getcr2());
1696 #if !defined(__xpv)
1697 printf("cr3: %lx", getcr3());
1698 #if defined(__amd64)
1699 printf("cr8: %lx\n", getcr8());
1700 #endif
1701 #endif
1702 printf("\n");
1703
1704 dumpregs(rp);
1705 splx(s);
1706 }
1707
1708 static void
dumpregs(struct regs * rp)1709 dumpregs(struct regs *rp)
1710 {
1711 #if defined(__amd64)
1712 const char fmt[] = "\t%3s: %16lx %3s: %16lx %3s: %16lx\n";
1713
1714 printf(fmt, "rdi", rp->r_rdi, "rsi", rp->r_rsi, "rdx", rp->r_rdx);
1715 printf(fmt, "rcx", rp->r_rcx, " r8", rp->r_r8, " r9", rp->r_r9);
1716 printf(fmt, "rax", rp->r_rax, "rbx", rp->r_rbx, "rbp", rp->r_rbp);
1717 printf(fmt, "r10", rp->r_r10, "r11", rp->r_r11, "r12", rp->r_r12);
1718 printf(fmt, "r13", rp->r_r13, "r14", rp->r_r14, "r15", rp->r_r15);
1719
1720 printf(fmt, "fsb", rdmsr(MSR_AMD_FSBASE), "gsb", rdmsr(MSR_AMD_GSBASE),
1721 " ds", rp->r_ds);
1722 printf(fmt, " es", rp->r_es, " fs", rp->r_fs, " gs", rp->r_gs);
1723
1724 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err, "rip", rp->r_rip);
1725 printf(fmt, " cs", rp->r_cs, "rfl", rp->r_rfl, "rsp", rp->r_rsp);
1726
1727 printf("\t%3s: %16lx\n", " ss", rp->r_ss);
1728
1729 #elif defined(__i386)
1730 const char fmt[] = "\t%3s: %8lx %3s: %8lx %3s: %8lx %3s: %8lx\n";
1731
1732 printf(fmt, " gs", rp->r_gs, " fs", rp->r_fs,
1733 " es", rp->r_es, " ds", rp->r_ds);
1734 printf(fmt, "edi", rp->r_edi, "esi", rp->r_esi,
1735 "ebp", rp->r_ebp, "esp", rp->r_esp);
1736 printf(fmt, "ebx", rp->r_ebx, "edx", rp->r_edx,
1737 "ecx", rp->r_ecx, "eax", rp->r_eax);
1738 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err,
1739 "eip", rp->r_eip, " cs", rp->r_cs);
1740 printf("\t%3s: %8lx %3s: %8lx %3s: %8lx\n",
1741 "efl", rp->r_efl, "usp", rp->r_uesp, " ss", rp->r_ss);
1742
1743 #endif /* __i386 */
1744 }
1745
1746 /*
1747 * Test to see if the instruction is iret on i386 or iretq on amd64.
1748 *
1749 * On the hypervisor we can only test for nopop_sys_rtt_syscall. If true
1750 * then we are in the context of hypervisor's failsafe handler because it
1751 * tried to iret and failed due to a bad selector. See xen_failsafe_callback.
1752 */
1753 static int
instr_is_iret(caddr_t pc)1754 instr_is_iret(caddr_t pc)
1755 {
1756
1757 #if defined(__xpv)
1758 extern void nopop_sys_rtt_syscall(void);
1759 return ((pc == (caddr_t)nopop_sys_rtt_syscall) ? 1 : 0);
1760
1761 #else
1762
1763 #if defined(__amd64)
1764 static const uint8_t iret_insn[2] = { 0x48, 0xcf }; /* iretq */
1765
1766 #elif defined(__i386)
1767 static const uint8_t iret_insn[1] = { 0xcf }; /* iret */
1768 #endif /* __i386 */
1769 return (bcmp(pc, iret_insn, sizeof (iret_insn)) == 0);
1770
1771 #endif /* __xpv */
1772 }
1773
1774 #if defined(__i386)
1775
1776 /*
1777 * Test to see if the instruction is part of __SEGREGS_POP
1778 *
1779 * Note carefully the appallingly awful dependency between
1780 * the instruction sequence used in __SEGREGS_POP and these
1781 * instructions encoded here.
1782 */
1783 static int
instr_is_segregs_pop(caddr_t pc)1784 instr_is_segregs_pop(caddr_t pc)
1785 {
1786 static const uint8_t movw_0_esp_gs[4] = { 0x8e, 0x6c, 0x24, 0x0 };
1787 static const uint8_t movw_4_esp_fs[4] = { 0x8e, 0x64, 0x24, 0x4 };
1788 static const uint8_t movw_8_esp_es[4] = { 0x8e, 0x44, 0x24, 0x8 };
1789 static const uint8_t movw_c_esp_ds[4] = { 0x8e, 0x5c, 0x24, 0xc };
1790
1791 if (bcmp(pc, movw_0_esp_gs, sizeof (movw_0_esp_gs)) == 0 ||
1792 bcmp(pc, movw_4_esp_fs, sizeof (movw_4_esp_fs)) == 0 ||
1793 bcmp(pc, movw_8_esp_es, sizeof (movw_8_esp_es)) == 0 ||
1794 bcmp(pc, movw_c_esp_ds, sizeof (movw_c_esp_ds)) == 0)
1795 return (1);
1796
1797 return (0);
1798 }
1799
1800 #endif /* __i386 */
1801
1802 /*
1803 * Test to see if the instruction is part of _sys_rtt.
1804 *
1805 * Again on the hypervisor if we try to IRET to user land with a bad code
1806 * or stack selector we will get vectored through xen_failsafe_callback.
1807 * In which case we assume we got here via _sys_rtt since we only allow
1808 * IRET to user land to take place in _sys_rtt.
1809 */
1810 static int
instr_is_sys_rtt(caddr_t pc)1811 instr_is_sys_rtt(caddr_t pc)
1812 {
1813 extern void _sys_rtt(), _sys_rtt_end();
1814
1815 if ((uintptr_t)pc < (uintptr_t)_sys_rtt ||
1816 (uintptr_t)pc > (uintptr_t)_sys_rtt_end)
1817 return (0);
1818
1819 return (1);
1820 }
1821
1822 /*
1823 * Handle #gp faults in kernel mode.
1824 *
1825 * One legitimate way this can happen is if we attempt to update segment
1826 * registers to naughty values on the way out of the kernel.
1827 *
1828 * This can happen in a couple of ways: someone - either accidentally or
1829 * on purpose - creates (setcontext(2), lwp_create(2)) or modifies
1830 * (signal(2)) a ucontext that contains silly segment register values.
1831 * Or someone - either accidentally or on purpose - modifies the prgregset_t
1832 * of a subject process via /proc to contain silly segment register values.
1833 *
1834 * (The unfortunate part is that we can end up discovering the bad segment
1835 * register value in the middle of an 'iret' after we've popped most of the
1836 * stack. So it becomes quite difficult to associate an accurate ucontext
1837 * with the lwp, because the act of taking the #gp trap overwrites most of
1838 * what we were going to send the lwp.)
1839 *
1840 * OTOH if it turns out that's -not- the problem, and we're -not- an lwp
1841 * trying to return to user mode and we get a #gp fault, then we need
1842 * to die() -- which will happen if we return non-zero from this routine.
1843 */
1844 static int
kern_gpfault(struct regs * rp)1845 kern_gpfault(struct regs *rp)
1846 {
1847 kthread_t *t = curthread;
1848 proc_t *p = ttoproc(t);
1849 klwp_t *lwp = ttolwp(t);
1850 struct regs tmpregs, *trp = NULL;
1851 caddr_t pc = (caddr_t)rp->r_pc;
1852 int v;
1853 uint32_t auditing = AU_AUDITING();
1854
1855 /*
1856 * if we're not an lwp, or in the case of running native the
1857 * pc range is outside _sys_rtt, then we should immediately
1858 * be die()ing horribly.
1859 */
1860 if (lwp == NULL || !instr_is_sys_rtt(pc))
1861 return (1);
1862
1863 /*
1864 * So at least we're in the right part of the kernel.
1865 *
1866 * Disassemble the instruction at the faulting pc.
1867 * Once we know what it is, we carefully reconstruct the stack
1868 * based on the order in which the stack is deconstructed in
1869 * _sys_rtt. Ew.
1870 */
1871 if (instr_is_iret(pc)) {
1872 /*
1873 * We took the #gp while trying to perform the IRET.
1874 * This means that either %cs or %ss are bad.
1875 * All we know for sure is that most of the general
1876 * registers have been restored, including the
1877 * segment registers, and all we have left on the
1878 * topmost part of the lwp's stack are the
1879 * registers that the iretq was unable to consume.
1880 *
1881 * All the rest of the state was crushed by the #gp
1882 * which pushed -its- registers atop our old save area
1883 * (because we had to decrement the stack pointer, sigh) so
1884 * all that we can try and do is to reconstruct the
1885 * crushed frame from the #gp trap frame itself.
1886 */
1887 trp = &tmpregs;
1888 trp->r_ss = lwptoregs(lwp)->r_ss;
1889 trp->r_sp = lwptoregs(lwp)->r_sp;
1890 trp->r_ps = lwptoregs(lwp)->r_ps;
1891 trp->r_cs = lwptoregs(lwp)->r_cs;
1892 trp->r_pc = lwptoregs(lwp)->r_pc;
1893 bcopy(rp, trp, offsetof(struct regs, r_pc));
1894
1895 /*
1896 * Validate simple math
1897 */
1898 ASSERT(trp->r_pc == lwptoregs(lwp)->r_pc);
1899 ASSERT(trp->r_err == rp->r_err);
1900
1901
1902
1903 }
1904
1905 #if defined(__amd64)
1906 if (trp == NULL && lwp->lwp_pcb.pcb_rupdate != 0) {
1907
1908 /*
1909 * This is the common case -- we're trying to load
1910 * a bad segment register value in the only section
1911 * of kernel code that ever loads segment registers.
1912 *
1913 * We don't need to do anything at this point because
1914 * the pcb contains all the pending segment register
1915 * state, and the regs are still intact because we
1916 * didn't adjust the stack pointer yet. Given the fidelity
1917 * of all this, we could conceivably send a signal
1918 * to the lwp, rather than core-ing.
1919 */
1920 trp = lwptoregs(lwp);
1921 ASSERT((caddr_t)trp == (caddr_t)rp->r_sp);
1922 }
1923
1924 #elif defined(__i386)
1925
1926 if (trp == NULL && instr_is_segregs_pop(pc))
1927 trp = lwptoregs(lwp);
1928
1929 #endif /* __i386 */
1930
1931 if (trp == NULL)
1932 return (1);
1933
1934 /*
1935 * If we get to here, we're reasonably confident that we've
1936 * correctly decoded what happened on the way out of the kernel.
1937 * Rewrite the lwp's registers so that we can create a core dump
1938 * the (at least vaguely) represents the mcontext we were
1939 * being asked to restore when things went so terribly wrong.
1940 */
1941
1942 /*
1943 * Make sure that we have a meaningful %trapno and %err.
1944 */
1945 trp->r_trapno = rp->r_trapno;
1946 trp->r_err = rp->r_err;
1947
1948 if ((caddr_t)trp != (caddr_t)lwptoregs(lwp))
1949 bcopy(trp, lwptoregs(lwp), sizeof (*trp));
1950
1951
1952 mutex_enter(&p->p_lock);
1953 lwp->lwp_cursig = SIGSEGV;
1954 mutex_exit(&p->p_lock);
1955
1956 /*
1957 * Terminate all LWPs but don't discard them. If another lwp beat
1958 * us to the punch by calling exit(), evaporate now.
1959 */
1960 proc_is_exiting(p);
1961 if (exitlwps(1) != 0) {
1962 mutex_enter(&p->p_lock);
1963 lwp_exit();
1964 }
1965
1966 if (auditing) /* audit core dump */
1967 audit_core_start(SIGSEGV);
1968 v = core(SIGSEGV, B_FALSE);
1969 if (auditing) /* audit core dump */
1970 audit_core_finish(v ? CLD_KILLED : CLD_DUMPED);
1971 exit(v ? CLD_KILLED : CLD_DUMPED, SIGSEGV);
1972 return (0);
1973 }
1974
1975 /*
1976 * dump_tss() - Display the TSS structure
1977 */
1978
1979 #if !defined(__xpv)
1980 #if defined(__amd64)
1981
1982 static void
dump_tss(void)1983 dump_tss(void)
1984 {
1985 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */
1986 struct tss *tss = CPU->cpu_tss;
1987
1988 printf(tss_fmt, "tss_rsp0", (void *)tss->tss_rsp0);
1989 printf(tss_fmt, "tss_rsp1", (void *)tss->tss_rsp1);
1990 printf(tss_fmt, "tss_rsp2", (void *)tss->tss_rsp2);
1991
1992 printf(tss_fmt, "tss_ist1", (void *)tss->tss_ist1);
1993 printf(tss_fmt, "tss_ist2", (void *)tss->tss_ist2);
1994 printf(tss_fmt, "tss_ist3", (void *)tss->tss_ist3);
1995 printf(tss_fmt, "tss_ist4", (void *)tss->tss_ist4);
1996 printf(tss_fmt, "tss_ist5", (void *)tss->tss_ist5);
1997 printf(tss_fmt, "tss_ist6", (void *)tss->tss_ist6);
1998 printf(tss_fmt, "tss_ist7", (void *)tss->tss_ist7);
1999 }
2000
2001 #elif defined(__i386)
2002
2003 static void
dump_tss(void)2004 dump_tss(void)
2005 {
2006 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */
2007 struct tss *tss = CPU->cpu_tss;
2008
2009 printf(tss_fmt, "tss_link", (void *)(uintptr_t)tss->tss_link);
2010 printf(tss_fmt, "tss_esp0", (void *)(uintptr_t)tss->tss_esp0);
2011 printf(tss_fmt, "tss_ss0", (void *)(uintptr_t)tss->tss_ss0);
2012 printf(tss_fmt, "tss_esp1", (void *)(uintptr_t)tss->tss_esp1);
2013 printf(tss_fmt, "tss_ss1", (void *)(uintptr_t)tss->tss_ss1);
2014 printf(tss_fmt, "tss_esp2", (void *)(uintptr_t)tss->tss_esp2);
2015 printf(tss_fmt, "tss_ss2", (void *)(uintptr_t)tss->tss_ss2);
2016 printf(tss_fmt, "tss_cr3", (void *)(uintptr_t)tss->tss_cr3);
2017 printf(tss_fmt, "tss_eip", (void *)(uintptr_t)tss->tss_eip);
2018 printf(tss_fmt, "tss_eflags", (void *)(uintptr_t)tss->tss_eflags);
2019 printf(tss_fmt, "tss_eax", (void *)(uintptr_t)tss->tss_eax);
2020 printf(tss_fmt, "tss_ebx", (void *)(uintptr_t)tss->tss_ebx);
2021 printf(tss_fmt, "tss_ecx", (void *)(uintptr_t)tss->tss_ecx);
2022 printf(tss_fmt, "tss_edx", (void *)(uintptr_t)tss->tss_edx);
2023 printf(tss_fmt, "tss_esp", (void *)(uintptr_t)tss->tss_esp);
2024 }
2025
2026 #endif /* __amd64 */
2027 #endif /* !__xpv */
2028
2029 #if defined(TRAPTRACE)
2030
2031 int ttrace_nrec = 10; /* number of records to dump out */
2032 int ttrace_dump_nregs = 0; /* dump out this many records with regs too */
2033
2034 /*
2035 * Dump out the last ttrace_nrec traptrace records on each CPU
2036 */
2037 static void
dump_ttrace(void)2038 dump_ttrace(void)
2039 {
2040 trap_trace_ctl_t *ttc;
2041 trap_trace_rec_t *rec;
2042 uintptr_t current;
2043 int i, j, k;
2044 int n = NCPU;
2045 #if defined(__amd64)
2046 const char banner[] =
2047 "\ncpu address timestamp "
2048 "type vc handler pc\n";
2049 const char fmt1[] = "%3d %016lx %12llx ";
2050 #elif defined(__i386)
2051 const char banner[] =
2052 "\ncpu address timestamp type vc handler pc\n";
2053 const char fmt1[] = "%3d %08lx %12llx ";
2054 #endif
2055 const char fmt2[] = "%4s %3x ";
2056 const char fmt3[] = "%8s ";
2057
2058 if (ttrace_nrec == 0)
2059 return;
2060
2061 printf(banner);
2062
2063 for (i = 0; i < n; i++) {
2064 ttc = &trap_trace_ctl[i];
2065 if (ttc->ttc_first == NULL)
2066 continue;
2067
2068 current = ttc->ttc_next - sizeof (trap_trace_rec_t);
2069 for (j = 0; j < ttrace_nrec; j++) {
2070 struct sysent *sys;
2071 struct autovec *vec;
2072 extern struct av_head autovect[];
2073 int type;
2074 ulong_t off;
2075 char *sym, *stype;
2076
2077 if (current < ttc->ttc_first)
2078 current =
2079 ttc->ttc_limit - sizeof (trap_trace_rec_t);
2080
2081 if (current == NULL)
2082 continue;
2083
2084 rec = (trap_trace_rec_t *)current;
2085
2086 if (rec->ttr_stamp == 0)
2087 break;
2088
2089 printf(fmt1, i, (uintptr_t)rec, rec->ttr_stamp);
2090
2091 switch (rec->ttr_marker) {
2092 case TT_SYSCALL:
2093 case TT_SYSENTER:
2094 case TT_SYSC:
2095 case TT_SYSC64:
2096 #if defined(__amd64)
2097 sys = &sysent32[rec->ttr_sysnum];
2098 switch (rec->ttr_marker) {
2099 case TT_SYSC64:
2100 sys = &sysent[rec->ttr_sysnum];
2101 /*FALLTHROUGH*/
2102 #elif defined(__i386)
2103 sys = &sysent[rec->ttr_sysnum];
2104 switch (rec->ttr_marker) {
2105 case TT_SYSC64:
2106 #endif
2107 case TT_SYSC:
2108 stype = "sysc"; /* syscall */
2109 break;
2110 case TT_SYSCALL:
2111 stype = "lcal"; /* lcall */
2112 break;
2113 case TT_SYSENTER:
2114 stype = "syse"; /* sysenter */
2115 break;
2116 default:
2117 break;
2118 }
2119 printf(fmt2, "sysc", rec->ttr_sysnum);
2120 if (sys != NULL) {
2121 sym = kobj_getsymname(
2122 (uintptr_t)sys->sy_callc,
2123 &off);
2124 if (sym != NULL)
2125 printf(fmt3, sym);
2126 else
2127 printf("%p ", sys->sy_callc);
2128 } else {
2129 printf(fmt3, "unknown");
2130 }
2131 break;
2132
2133 case TT_INTERRUPT:
2134 printf(fmt2, "intr", rec->ttr_vector);
2135 if (get_intr_handler != NULL)
2136 vec = (struct autovec *)
2137 (*get_intr_handler)
2138 (rec->ttr_cpuid, rec->ttr_vector);
2139 else
2140 vec =
2141 autovect[rec->ttr_vector].avh_link;
2142
2143 if (vec != NULL) {
2144 sym = kobj_getsymname(
2145 (uintptr_t)vec->av_vector, &off);
2146 if (sym != NULL)
2147 printf(fmt3, sym);
2148 else
2149 printf("%p ", vec->av_vector);
2150 } else {
2151 printf(fmt3, "unknown ");
2152 }
2153 break;
2154
2155 case TT_TRAP:
2156 case TT_EVENT:
2157 type = rec->ttr_regs.r_trapno;
2158 printf(fmt2, "trap", type);
2159 if (type < TRAP_TYPES)
2160 printf(" #%s ",
2161 trap_type_mnemonic[type]);
2162 else
2163 switch (type) {
2164 case T_AST:
2165 printf(fmt3, "ast");
2166 break;
2167 default:
2168 printf(fmt3, "");
2169 break;
2170 }
2171 break;
2172
2173 default:
2174 break;
2175 }
2176
2177 sym = kobj_getsymname(rec->ttr_regs.r_pc, &off);
2178 if (sym != NULL)
2179 printf("%s+%lx\n", sym, off);
2180 else
2181 printf("%lx\n", rec->ttr_regs.r_pc);
2182
2183 if (ttrace_dump_nregs-- > 0) {
2184 int s;
2185
2186 if (rec->ttr_marker == TT_INTERRUPT)
2187 printf(
2188 "\t\tipl %x spl %x pri %x\n",
2189 rec->ttr_ipl,
2190 rec->ttr_spl,
2191 rec->ttr_pri);
2192
2193 dumpregs(&rec->ttr_regs);
2194
2195 printf("\t%3s: %p\n\n", " ct",
2196 (void *)rec->ttr_curthread);
2197
2198 /*
2199 * print out the pc stack that we recorded
2200 * at trap time (if any)
2201 */
2202 for (s = 0; s < rec->ttr_sdepth; s++) {
2203 uintptr_t fullpc;
2204
2205 if (s >= TTR_STACK_DEPTH) {
2206 printf("ttr_sdepth corrupt\n");
2207 break;
2208 }
2209
2210 fullpc = (uintptr_t)rec->ttr_stack[s];
2211
2212 sym = kobj_getsymname(fullpc, &off);
2213 if (sym != NULL)
2214 printf("-> %s+0x%lx()\n",
2215 sym, off);
2216 else
2217 printf("-> 0x%lx()\n", fullpc);
2218 }
2219 printf("\n");
2220 }
2221 current -= sizeof (trap_trace_rec_t);
2222 }
2223 }
2224 }
2225
2226 #endif /* TRAPTRACE */
2227
2228 void
2229 panic_showtrap(struct panic_trap_info *tip)
2230 {
2231 showregs(tip->trap_type, tip->trap_regs, tip->trap_addr);
2232
2233 #if defined(TRAPTRACE)
2234 dump_ttrace();
2235 #endif
2236
2237 #if !defined(__xpv)
2238 if (tip->trap_type == T_DBLFLT)
2239 dump_tss();
2240 #endif
2241 }
2242
2243 void
2244 panic_savetrap(panic_data_t *pdp, struct panic_trap_info *tip)
2245 {
2246 panic_saveregs(pdp, tip->trap_regs);
2247 }
2248