1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * This file contains various support routines. 28 */ 29 30 #include <sys/scsi/adapters/pmcs/pmcs.h> 31 32 /* 33 * Local static data 34 */ 35 static int tgtmap_usec = MICROSEC; 36 37 /* 38 * SAS Topology Configuration 39 */ 40 static void pmcs_new_tport(pmcs_hw_t *, pmcs_phy_t *); 41 static void pmcs_configure_expander(pmcs_hw_t *, pmcs_phy_t *, pmcs_iport_t *); 42 43 static void pmcs_check_expanders(pmcs_hw_t *, pmcs_phy_t *); 44 static void pmcs_check_expander(pmcs_hw_t *, pmcs_phy_t *); 45 static void pmcs_clear_expander(pmcs_hw_t *, pmcs_phy_t *, int); 46 47 static int pmcs_expander_get_nphy(pmcs_hw_t *, pmcs_phy_t *); 48 static int pmcs_expander_content_discover(pmcs_hw_t *, pmcs_phy_t *, 49 pmcs_phy_t *); 50 51 static int pmcs_smp_function_result(pmcs_hw_t *, smp_response_frame_t *); 52 static boolean_t pmcs_validate_devid(pmcs_phy_t *, pmcs_phy_t *, uint32_t); 53 static void pmcs_clear_phys(pmcs_hw_t *, pmcs_phy_t *); 54 static int pmcs_configure_new_devices(pmcs_hw_t *, pmcs_phy_t *); 55 static void pmcs_begin_observations(pmcs_hw_t *); 56 static boolean_t pmcs_report_observations(pmcs_hw_t *); 57 static boolean_t pmcs_report_iport_observations(pmcs_hw_t *, pmcs_iport_t *, 58 pmcs_phy_t *); 59 static pmcs_phy_t *pmcs_find_phy_needing_work(pmcs_hw_t *, pmcs_phy_t *); 60 static int pmcs_kill_devices(pmcs_hw_t *, pmcs_phy_t *); 61 static void pmcs_lock_phy_impl(pmcs_phy_t *, int); 62 static void pmcs_unlock_phy_impl(pmcs_phy_t *, int); 63 static pmcs_phy_t *pmcs_clone_phy(pmcs_phy_t *); 64 static boolean_t pmcs_configure_phy(pmcs_hw_t *, pmcs_phy_t *); 65 static void pmcs_reap_dead_phy(pmcs_phy_t *); 66 static pmcs_iport_t *pmcs_get_iport_by_ua(pmcs_hw_t *, char *); 67 static boolean_t pmcs_phy_target_match(pmcs_phy_t *); 68 static void pmcs_iport_active(pmcs_iport_t *); 69 static void pmcs_tgtmap_activate_cb(void *, char *, scsi_tgtmap_tgt_type_t, 70 void **); 71 static boolean_t pmcs_tgtmap_deactivate_cb(void *, char *, 72 scsi_tgtmap_tgt_type_t, void *, scsi_tgtmap_deact_rsn_t); 73 static void pmcs_add_dead_phys(pmcs_hw_t *, pmcs_phy_t *); 74 75 /* 76 * Often used strings 77 */ 78 const char pmcs_nowrk[] = "%s: unable to get work structure"; 79 const char pmcs_nomsg[] = "%s: unable to get Inbound Message entry"; 80 const char pmcs_timeo[] = "%s: command timed out"; 81 82 extern const ddi_dma_attr_t pmcs_dattr; 83 84 /* 85 * Some Initial setup steps. 86 */ 87 88 int 89 pmcs_setup(pmcs_hw_t *pwp) 90 { 91 uint32_t barval = pwp->mpibar; 92 uint32_t i, scratch, regbar, regoff, barbar, baroff; 93 uint32_t new_ioq_depth, ferr = 0; 94 95 /* 96 * Check current state. If we're not at READY state, 97 * we can't go further. 98 */ 99 scratch = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1); 100 if ((scratch & PMCS_MSGU_AAP_STATE_MASK) == PMCS_MSGU_AAP_STATE_ERROR) { 101 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 102 "%s: AAP Error State (0x%x)", 103 __func__, pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1) & 104 PMCS_MSGU_AAP_ERROR_MASK); 105 pmcs_fm_ereport(pwp, DDI_FM_DEVICE_INVAL_STATE); 106 ddi_fm_service_impact(pwp->dip, DDI_SERVICE_LOST); 107 return (-1); 108 } 109 if ((scratch & PMCS_MSGU_AAP_STATE_MASK) != PMCS_MSGU_AAP_STATE_READY) { 110 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 111 "%s: AAP unit not ready (state 0x%x)", 112 __func__, scratch & PMCS_MSGU_AAP_STATE_MASK); 113 pmcs_fm_ereport(pwp, DDI_FM_DEVICE_INVAL_STATE); 114 ddi_fm_service_impact(pwp->dip, DDI_SERVICE_LOST); 115 return (-1); 116 } 117 118 /* 119 * Read the offset from the Message Unit scratchpad 0 register. 120 * This allows us to read the MPI Configuration table. 121 * 122 * Check its signature for validity. 123 */ 124 baroff = barval; 125 barbar = barval >> PMCS_MSGU_MPI_BAR_SHIFT; 126 baroff &= PMCS_MSGU_MPI_OFFSET_MASK; 127 128 regoff = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH0); 129 regbar = regoff >> PMCS_MSGU_MPI_BAR_SHIFT; 130 regoff &= PMCS_MSGU_MPI_OFFSET_MASK; 131 132 if (regoff > baroff) { 133 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 134 "%s: bad MPI Table Length (register offset=0x%08x, " 135 "passed offset=0x%08x)", __func__, regoff, baroff); 136 return (-1); 137 } 138 if (regbar != barbar) { 139 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 140 "%s: bad MPI BAR (register BAROFF=0x%08x, " 141 "passed BAROFF=0x%08x)", __func__, regbar, barbar); 142 return (-1); 143 } 144 pwp->mpi_offset = regoff; 145 if (pmcs_rd_mpi_tbl(pwp, PMCS_MPI_AS) != PMCS_SIGNATURE) { 146 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 147 "%s: Bad MPI Configuration Table Signature 0x%x", __func__, 148 pmcs_rd_mpi_tbl(pwp, PMCS_MPI_AS)); 149 return (-1); 150 } 151 152 if (pmcs_rd_mpi_tbl(pwp, PMCS_MPI_IR) != PMCS_MPI_REVISION1) { 153 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 154 "%s: Bad MPI Configuration Revision 0x%x", __func__, 155 pmcs_rd_mpi_tbl(pwp, PMCS_MPI_IR)); 156 return (-1); 157 } 158 159 /* 160 * Generate offsets for the General System, Inbound Queue Configuration 161 * and Outbound Queue configuration tables. This way the macros to 162 * access those tables will work correctly. 163 */ 164 pwp->mpi_gst_offset = 165 pwp->mpi_offset + pmcs_rd_mpi_tbl(pwp, PMCS_MPI_GSTO); 166 pwp->mpi_iqc_offset = 167 pwp->mpi_offset + pmcs_rd_mpi_tbl(pwp, PMCS_MPI_IQCTO); 168 pwp->mpi_oqc_offset = 169 pwp->mpi_offset + pmcs_rd_mpi_tbl(pwp, PMCS_MPI_OQCTO); 170 171 pwp->fw = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_FW); 172 173 pwp->max_cmd = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_MOIO); 174 pwp->max_dev = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO0) >> 16; 175 176 pwp->max_iq = PMCS_MNIQ(pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO1)); 177 pwp->max_oq = PMCS_MNOQ(pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO1)); 178 pwp->nphy = PMCS_NPHY(pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO1)); 179 if (pwp->max_iq <= PMCS_NIQ) { 180 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 181 "%s: not enough Inbound Queues supported " 182 "(need %d, max_oq=%d)", __func__, pwp->max_iq, PMCS_NIQ); 183 return (-1); 184 } 185 if (pwp->max_oq <= PMCS_NOQ) { 186 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 187 "%s: not enough Outbound Queues supported " 188 "(need %d, max_oq=%d)", __func__, pwp->max_oq, PMCS_NOQ); 189 return (-1); 190 } 191 if (pwp->nphy == 0) { 192 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 193 "%s: zero phys reported", __func__); 194 return (-1); 195 } 196 if (PMCS_HPIQ(pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO1))) { 197 pwp->hipri_queue = (1 << PMCS_IQ_OTHER); 198 } 199 200 201 for (i = 0; i < pwp->nphy; i++) { 202 PMCS_MPI_EVQSET(pwp, PMCS_OQ_EVENTS, i); 203 PMCS_MPI_NCQSET(pwp, PMCS_OQ_EVENTS, i); 204 } 205 206 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_INFO2, 207 (PMCS_OQ_EVENTS << GENERAL_EVENT_OQ_SHIFT) | 208 (PMCS_OQ_EVENTS << DEVICE_HANDLE_REMOVED_SHIFT)); 209 210 /* 211 * Verify that ioq_depth is valid (> 0 and not so high that it 212 * would cause us to overrun the chip with commands). 213 */ 214 if (pwp->ioq_depth == 0) { 215 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 216 "%s: I/O queue depth set to 0. Setting to %d", 217 __func__, PMCS_NQENTRY); 218 pwp->ioq_depth = PMCS_NQENTRY; 219 } 220 221 if (pwp->ioq_depth < PMCS_MIN_NQENTRY) { 222 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 223 "%s: I/O queue depth set too low (%d). Setting to %d", 224 __func__, pwp->ioq_depth, PMCS_MIN_NQENTRY); 225 pwp->ioq_depth = PMCS_MIN_NQENTRY; 226 } 227 228 if (pwp->ioq_depth > (pwp->max_cmd / (PMCS_IO_IQ_MASK + 1))) { 229 new_ioq_depth = pwp->max_cmd / (PMCS_IO_IQ_MASK + 1); 230 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 231 "%s: I/O queue depth set too high (%d). Setting to %d", 232 __func__, pwp->ioq_depth, new_ioq_depth); 233 pwp->ioq_depth = new_ioq_depth; 234 } 235 236 /* 237 * Allocate consistent memory for OQs and IQs. 238 */ 239 pwp->iqp_dma_attr = pwp->oqp_dma_attr = pmcs_dattr; 240 pwp->iqp_dma_attr.dma_attr_align = 241 pwp->oqp_dma_attr.dma_attr_align = PMCS_QENTRY_SIZE; 242 243 /* 244 * The Rev C chip has the ability to do PIO to or from consistent 245 * memory anywhere in a 64 bit address space, but the firmware is 246 * not presently set up to do so. 247 */ 248 pwp->iqp_dma_attr.dma_attr_addr_hi = 249 pwp->oqp_dma_attr.dma_attr_addr_hi = 0x000000FFFFFFFFFFull; 250 251 for (i = 0; i < PMCS_NIQ; i++) { 252 if (pmcs_dma_setup(pwp, &pwp->iqp_dma_attr, 253 &pwp->iqp_acchdls[i], 254 &pwp->iqp_handles[i], PMCS_QENTRY_SIZE * pwp->ioq_depth, 255 (caddr_t *)&pwp->iqp[i], &pwp->iqaddr[i]) == B_FALSE) { 256 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 257 "Failed to setup DMA for iqp[%d]", i); 258 return (-1); 259 } 260 bzero(pwp->iqp[i], PMCS_QENTRY_SIZE * pwp->ioq_depth); 261 } 262 263 for (i = 0; i < PMCS_NOQ; i++) { 264 if (pmcs_dma_setup(pwp, &pwp->oqp_dma_attr, 265 &pwp->oqp_acchdls[i], 266 &pwp->oqp_handles[i], PMCS_QENTRY_SIZE * pwp->ioq_depth, 267 (caddr_t *)&pwp->oqp[i], &pwp->oqaddr[i]) == B_FALSE) { 268 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 269 "Failed to setup DMA for oqp[%d]", i); 270 return (-1); 271 } 272 bzero(pwp->oqp[i], PMCS_QENTRY_SIZE * pwp->ioq_depth); 273 } 274 275 /* 276 * Install the IQ and OQ addresses (and null out the rest). 277 */ 278 for (i = 0; i < pwp->max_iq; i++) { 279 pwp->iqpi_offset[i] = pmcs_rd_iqc_tbl(pwp, PMCS_IQPIOFFX(i)); 280 if (i < PMCS_NIQ) { 281 if (i != PMCS_IQ_OTHER) { 282 pmcs_wr_iqc_tbl(pwp, PMCS_IQC_PARMX(i), 283 pwp->ioq_depth | (PMCS_QENTRY_SIZE << 16)); 284 } else { 285 pmcs_wr_iqc_tbl(pwp, PMCS_IQC_PARMX(i), 286 (1 << 30) | pwp->ioq_depth | 287 (PMCS_QENTRY_SIZE << 16)); 288 } 289 pmcs_wr_iqc_tbl(pwp, PMCS_IQBAHX(i), 290 DWORD1(pwp->iqaddr[i])); 291 pmcs_wr_iqc_tbl(pwp, PMCS_IQBALX(i), 292 DWORD0(pwp->iqaddr[i])); 293 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBAHX(i), 294 DWORD1(pwp->ciaddr+IQ_OFFSET(i))); 295 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBALX(i), 296 DWORD0(pwp->ciaddr+IQ_OFFSET(i))); 297 } else { 298 pmcs_wr_iqc_tbl(pwp, PMCS_IQC_PARMX(i), 0); 299 pmcs_wr_iqc_tbl(pwp, PMCS_IQBAHX(i), 0); 300 pmcs_wr_iqc_tbl(pwp, PMCS_IQBALX(i), 0); 301 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBAHX(i), 0); 302 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBALX(i), 0); 303 } 304 } 305 306 for (i = 0; i < pwp->max_oq; i++) { 307 pwp->oqci_offset[i] = pmcs_rd_oqc_tbl(pwp, PMCS_OQCIOFFX(i)); 308 if (i < PMCS_NOQ) { 309 pmcs_wr_oqc_tbl(pwp, PMCS_OQC_PARMX(i), pwp->ioq_depth | 310 (PMCS_QENTRY_SIZE << 16) | OQIEX); 311 pmcs_wr_oqc_tbl(pwp, PMCS_OQBAHX(i), 312 DWORD1(pwp->oqaddr[i])); 313 pmcs_wr_oqc_tbl(pwp, PMCS_OQBALX(i), 314 DWORD0(pwp->oqaddr[i])); 315 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBAHX(i), 316 DWORD1(pwp->ciaddr+OQ_OFFSET(i))); 317 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBALX(i), 318 DWORD0(pwp->ciaddr+OQ_OFFSET(i))); 319 pmcs_wr_oqc_tbl(pwp, PMCS_OQIPARM(i), 320 pwp->oqvec[i] << 24); 321 pmcs_wr_oqc_tbl(pwp, PMCS_OQDICX(i), 0); 322 } else { 323 pmcs_wr_oqc_tbl(pwp, PMCS_OQC_PARMX(i), 0); 324 pmcs_wr_oqc_tbl(pwp, PMCS_OQBAHX(i), 0); 325 pmcs_wr_oqc_tbl(pwp, PMCS_OQBALX(i), 0); 326 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBAHX(i), 0); 327 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBALX(i), 0); 328 pmcs_wr_oqc_tbl(pwp, PMCS_OQIPARM(i), 0); 329 pmcs_wr_oqc_tbl(pwp, PMCS_OQDICX(i), 0); 330 } 331 } 332 333 /* 334 * Set up logging, if defined. 335 */ 336 if (pwp->fwlog) { 337 uint64_t logdma = pwp->fwaddr; 338 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_MELBAH, DWORD1(logdma)); 339 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_MELBAL, DWORD0(logdma)); 340 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_MELBS, PMCS_FWLOG_SIZE >> 1); 341 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_MELSEV, pwp->fwlog); 342 logdma += (PMCS_FWLOG_SIZE >> 1); 343 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_IELBAH, DWORD1(logdma)); 344 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_IELBAL, DWORD0(logdma)); 345 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_IELBS, PMCS_FWLOG_SIZE >> 1); 346 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_IELSEV, pwp->fwlog); 347 } 348 349 /* 350 * Interrupt vectors, outbound queues, and odb_auto_clear 351 * 352 * MSI/MSI-X: 353 * If we got 4 interrupt vectors, we'll assign one to each outbound 354 * queue as well as the fatal interrupt, and auto clear can be set 355 * for each. 356 * 357 * If we only got 2 vectors, one will be used for I/O completions 358 * and the other for the other two vectors. In this case, auto_ 359 * clear can only be set for I/Os, which is fine. The fatal 360 * interrupt will be mapped to the PMCS_FATAL_INTERRUPT bit, which 361 * is not an interrupt vector. 362 * 363 * MSI/MSI-X/INT-X: 364 * If we only got 1 interrupt vector, auto_clear must be set to 0, 365 * and again the fatal interrupt will be mapped to the 366 * PMCS_FATAL_INTERRUPT bit (again, not an interrupt vector). 367 */ 368 369 switch (pwp->int_type) { 370 case PMCS_INT_MSIX: 371 case PMCS_INT_MSI: 372 switch (pwp->intr_cnt) { 373 case 1: 374 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, PMCS_FERRIE | 375 (PMCS_FATAL_INTERRUPT << PMCS_FERIV_SHIFT)); 376 pwp->odb_auto_clear = 0; 377 break; 378 case 2: 379 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, PMCS_FERRIE | 380 (PMCS_FATAL_INTERRUPT << PMCS_FERIV_SHIFT)); 381 pwp->odb_auto_clear = (1 << PMCS_FATAL_INTERRUPT) | 382 (1 << PMCS_MSIX_IODONE); 383 break; 384 case 4: 385 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, PMCS_FERRIE | 386 (PMCS_MSIX_FATAL << PMCS_FERIV_SHIFT)); 387 pwp->odb_auto_clear = (1 << PMCS_MSIX_FATAL) | 388 (1 << PMCS_MSIX_GENERAL) | (1 << PMCS_MSIX_IODONE) | 389 (1 << PMCS_MSIX_EVENTS); 390 break; 391 } 392 break; 393 394 case PMCS_INT_FIXED: 395 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, 396 PMCS_FERRIE | (PMCS_FATAL_INTERRUPT << PMCS_FERIV_SHIFT)); 397 pwp->odb_auto_clear = 0; 398 break; 399 } 400 401 /* 402 * Enable Interrupt Reassertion 403 * Default Delay 1000us 404 */ 405 ferr = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_FERR); 406 if ((ferr & PMCS_MPI_IRAE) == 0) { 407 ferr &= ~(PMCS_MPI_IRAU | PMCS_MPI_IRAD_MASK); 408 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, ferr | PMCS_MPI_IRAE); 409 } 410 411 pmcs_wr_topunit(pwp, PMCS_OBDB_AUTO_CLR, pwp->odb_auto_clear); 412 pwp->mpi_table_setup = 1; 413 return (0); 414 } 415 416 /* 417 * Start the Message Passing protocol with the PMC chip. 418 */ 419 int 420 pmcs_start_mpi(pmcs_hw_t *pwp) 421 { 422 int i; 423 424 pmcs_wr_msgunit(pwp, PMCS_MSGU_IBDB, PMCS_MSGU_IBDB_MPIINI); 425 for (i = 0; i < 1000; i++) { 426 if ((pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB) & 427 PMCS_MSGU_IBDB_MPIINI) == 0) { 428 break; 429 } 430 drv_usecwait(1000); 431 } 432 if (pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB) & PMCS_MSGU_IBDB_MPIINI) { 433 return (-1); 434 } 435 drv_usecwait(500000); 436 437 /* 438 * Check to make sure we got to INIT state. 439 */ 440 if (PMCS_MPI_S(pmcs_rd_gst_tbl(pwp, PMCS_GST_BASE)) != 441 PMCS_MPI_STATE_INIT) { 442 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 443 "%s: MPI launch failed (GST 0x%x DBCLR 0x%x)", __func__, 444 pmcs_rd_gst_tbl(pwp, PMCS_GST_BASE), 445 pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB_CLEAR)); 446 return (-1); 447 } 448 return (0); 449 } 450 451 /* 452 * Stop the Message Passing protocol with the PMC chip. 453 */ 454 int 455 pmcs_stop_mpi(pmcs_hw_t *pwp) 456 { 457 int i; 458 459 for (i = 0; i < pwp->max_iq; i++) { 460 pmcs_wr_iqc_tbl(pwp, PMCS_IQC_PARMX(i), 0); 461 pmcs_wr_iqc_tbl(pwp, PMCS_IQBAHX(i), 0); 462 pmcs_wr_iqc_tbl(pwp, PMCS_IQBALX(i), 0); 463 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBAHX(i), 0); 464 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBALX(i), 0); 465 } 466 for (i = 0; i < pwp->max_oq; i++) { 467 pmcs_wr_oqc_tbl(pwp, PMCS_OQC_PARMX(i), 0); 468 pmcs_wr_oqc_tbl(pwp, PMCS_OQBAHX(i), 0); 469 pmcs_wr_oqc_tbl(pwp, PMCS_OQBALX(i), 0); 470 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBAHX(i), 0); 471 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBALX(i), 0); 472 pmcs_wr_oqc_tbl(pwp, PMCS_OQIPARM(i), 0); 473 pmcs_wr_oqc_tbl(pwp, PMCS_OQDICX(i), 0); 474 } 475 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, 0); 476 pmcs_wr_msgunit(pwp, PMCS_MSGU_IBDB, PMCS_MSGU_IBDB_MPICTU); 477 for (i = 0; i < 2000; i++) { 478 if ((pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB) & 479 PMCS_MSGU_IBDB_MPICTU) == 0) { 480 break; 481 } 482 drv_usecwait(1000); 483 } 484 if (pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB) & PMCS_MSGU_IBDB_MPICTU) { 485 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 486 "%s: MPI stop failed", __func__); 487 return (-1); 488 } 489 return (0); 490 } 491 492 /* 493 * Do a sequence of ECHO messages to test for MPI functionality, 494 * all inbound and outbound queue functionality and interrupts. 495 */ 496 int 497 pmcs_echo_test(pmcs_hw_t *pwp) 498 { 499 echo_test_t fred; 500 struct pmcwork *pwrk; 501 uint32_t *msg, count; 502 int iqe = 0, iqo = 0, result, rval = 0; 503 int iterations; 504 hrtime_t echo_start, echo_end, echo_total; 505 506 ASSERT(pwp->max_cmd > 0); 507 508 /* 509 * We want iterations to be max_cmd * 3 to ensure that we run the 510 * echo test enough times to iterate through every inbound queue 511 * at least twice. 512 */ 513 iterations = pwp->max_cmd * 3; 514 515 echo_total = 0; 516 count = 0; 517 518 while (count < iterations) { 519 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, NULL); 520 if (pwrk == NULL) { 521 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, 522 pmcs_nowrk, __func__); 523 rval = -1; 524 break; 525 } 526 527 mutex_enter(&pwp->iqp_lock[iqe]); 528 msg = GET_IQ_ENTRY(pwp, iqe); 529 if (msg == NULL) { 530 mutex_exit(&pwp->iqp_lock[iqe]); 531 pmcs_pwork(pwp, pwrk); 532 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, 533 pmcs_nomsg, __func__); 534 rval = -1; 535 break; 536 } 537 538 bzero(msg, PMCS_QENTRY_SIZE); 539 540 if (iqe == PMCS_IQ_OTHER) { 541 /* This is on the high priority queue */ 542 msg[0] = LE_32(PMCS_HIPRI(pwp, iqo, PMCIN_ECHO)); 543 } else { 544 msg[0] = LE_32(PMCS_IOMB_IN_SAS(iqo, PMCIN_ECHO)); 545 } 546 msg[1] = LE_32(pwrk->htag); 547 fred.signature = 0xdeadbeef; 548 fred.count = count; 549 fred.ptr = &count; 550 (void) memcpy(&msg[2], &fred, sizeof (fred)); 551 pwrk->state = PMCS_WORK_STATE_ONCHIP; 552 553 INC_IQ_ENTRY(pwp, iqe); 554 555 echo_start = gethrtime(); 556 DTRACE_PROBE2(pmcs__echo__test__wait__start, 557 hrtime_t, echo_start, uint32_t, pwrk->htag); 558 559 if (++iqe == PMCS_NIQ) { 560 iqe = 0; 561 } 562 if (++iqo == PMCS_NOQ) { 563 iqo = 0; 564 } 565 566 WAIT_FOR(pwrk, 250, result); 567 568 echo_end = gethrtime(); 569 DTRACE_PROBE2(pmcs__echo__test__wait__end, 570 hrtime_t, echo_end, int, result); 571 572 echo_total += (echo_end - echo_start); 573 574 pmcs_pwork(pwp, pwrk); 575 if (result) { 576 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 577 "%s: command timed out on echo test #%d", 578 __func__, count); 579 rval = -1; 580 break; 581 } 582 } 583 584 /* 585 * The intr_threshold is adjusted by PMCS_INTR_THRESHOLD in order to 586 * remove the overhead of things like the delay in getting signaled 587 * for completion. 588 */ 589 if (echo_total != 0) { 590 pwp->io_intr_coal.intr_latency = 591 (echo_total / iterations) / 2; 592 pwp->io_intr_coal.intr_threshold = 593 PMCS_INTR_THRESHOLD(PMCS_QUANTUM_TIME_USECS * 1000 / 594 pwp->io_intr_coal.intr_latency); 595 } 596 597 return (rval); 598 } 599 600 /* 601 * Start the (real) phys 602 */ 603 int 604 pmcs_start_phy(pmcs_hw_t *pwp, int phynum, int linkmode, int speed) 605 { 606 int result; 607 uint32_t *msg; 608 struct pmcwork *pwrk; 609 pmcs_phy_t *pptr; 610 sas_identify_af_t sap; 611 612 mutex_enter(&pwp->lock); 613 pptr = pwp->root_phys + phynum; 614 if (pptr == NULL) { 615 mutex_exit(&pwp->lock); 616 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 617 "%s: cannot find port %d", __func__, phynum); 618 return (0); 619 } 620 621 pmcs_lock_phy(pptr); 622 mutex_exit(&pwp->lock); 623 624 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 625 if (pwrk == NULL) { 626 pmcs_unlock_phy(pptr); 627 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nowrk, __func__); 628 return (-1); 629 } 630 631 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 632 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 633 634 if (msg == NULL) { 635 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 636 pmcs_unlock_phy(pptr); 637 pmcs_pwork(pwp, pwrk); 638 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nomsg, __func__); 639 return (-1); 640 } 641 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_EVENTS, PMCIN_PHY_START)); 642 msg[1] = LE_32(pwrk->htag); 643 msg[2] = LE_32(linkmode | speed | phynum); 644 bzero(&sap, sizeof (sap)); 645 sap.device_type = SAS_IF_DTYPE_ENDPOINT; 646 sap.ssp_ini_port = 1; 647 648 if (pwp->separate_ports) { 649 pmcs_wwn2barray(pwp->sas_wwns[phynum], sap.sas_address); 650 } else { 651 pmcs_wwn2barray(pwp->sas_wwns[0], sap.sas_address); 652 } 653 654 ASSERT(phynum < SAS2_PHYNUM_MAX); 655 sap.phy_identifier = phynum & SAS2_PHYNUM_MASK; 656 (void) memcpy(&msg[3], &sap, sizeof (sas_identify_af_t)); 657 pwrk->state = PMCS_WORK_STATE_ONCHIP; 658 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 659 660 pptr->state.prog_min_rate = (lowbit((ulong_t)speed) - 1); 661 pptr->state.prog_max_rate = (highbit((ulong_t)speed) - 1); 662 pptr->state.hw_min_rate = PMCS_HW_MIN_LINK_RATE; 663 pptr->state.hw_max_rate = PMCS_HW_MAX_LINK_RATE; 664 665 pmcs_unlock_phy(pptr); 666 WAIT_FOR(pwrk, 1000, result); 667 pmcs_pwork(pwp, pwrk); 668 669 if (result) { 670 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, pmcs_timeo, __func__); 671 } else { 672 mutex_enter(&pwp->lock); 673 pwp->phys_started |= (1 << phynum); 674 mutex_exit(&pwp->lock); 675 } 676 677 return (0); 678 } 679 680 int 681 pmcs_start_phys(pmcs_hw_t *pwp) 682 { 683 int i; 684 685 for (i = 0; i < pwp->nphy; i++) { 686 if ((pwp->phyid_block_mask & (1 << i)) == 0) { 687 if (pmcs_start_phy(pwp, i, 688 (pwp->phymode << PHY_MODE_SHIFT), 689 pwp->physpeed << PHY_LINK_SHIFT)) { 690 return (-1); 691 } 692 if (pmcs_clear_diag_counters(pwp, i)) { 693 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 694 "%s: failed to reset counters on PHY (%d)", 695 __func__, i); 696 } 697 } 698 } 699 return (0); 700 } 701 702 /* 703 * Called with PHY locked 704 */ 705 int 706 pmcs_reset_phy(pmcs_hw_t *pwp, pmcs_phy_t *pptr, uint8_t type) 707 { 708 uint32_t *msg; 709 uint32_t iomb[(PMCS_QENTRY_SIZE << 1) >> 2]; 710 const char *mbar; 711 uint32_t amt; 712 uint32_t pdevid; 713 uint32_t stsoff; 714 uint32_t status; 715 int result, level, phynum; 716 struct pmcwork *pwrk; 717 uint32_t htag; 718 719 ASSERT(mutex_owned(&pptr->phy_lock)); 720 721 bzero(iomb, PMCS_QENTRY_SIZE); 722 phynum = pptr->phynum; 723 level = pptr->level; 724 if (level > 0) { 725 pdevid = pptr->parent->device_id; 726 } else if ((level == 0) && (pptr->dtype == EXPANDER)) { 727 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, pptr->target, 728 "%s: Not resetting HBA PHY @ %s", __func__, pptr->path); 729 return (0); 730 } 731 732 if (!pptr->iport || !pptr->valid_device_id) { 733 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, pptr->target, 734 "%s: Can't reach PHY %s", __func__, pptr->path); 735 return (0); 736 } 737 738 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 739 740 if (pwrk == NULL) { 741 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nowrk, __func__); 742 return (ENOMEM); 743 } 744 745 pwrk->arg = iomb; 746 747 /* 748 * If level > 0, we need to issue an SMP_REQUEST with a PHY_CONTROL 749 * function to do either a link reset or hard reset. If level == 0, 750 * then we do a LOCAL_PHY_CONTROL IOMB to do link/hard reset to the 751 * root (local) PHY 752 */ 753 if (level) { 754 stsoff = 2; 755 iomb[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 756 PMCIN_SMP_REQUEST)); 757 iomb[1] = LE_32(pwrk->htag); 758 iomb[2] = LE_32(pdevid); 759 iomb[3] = LE_32(40 << SMP_REQUEST_LENGTH_SHIFT); 760 /* 761 * Send SMP PHY CONTROL/HARD or LINK RESET 762 */ 763 iomb[4] = BE_32(0x40910000); 764 iomb[5] = 0; 765 766 if (type == PMCS_PHYOP_HARD_RESET) { 767 mbar = "SMP PHY CONTROL/HARD RESET"; 768 iomb[6] = BE_32((phynum << 24) | 769 (PMCS_PHYOP_HARD_RESET << 16)); 770 } else { 771 mbar = "SMP PHY CONTROL/LINK RESET"; 772 iomb[6] = BE_32((phynum << 24) | 773 (PMCS_PHYOP_LINK_RESET << 16)); 774 } 775 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 776 "%s: sending %s to %s for phy 0x%x", 777 __func__, mbar, pptr->parent->path, pptr->phynum); 778 amt = 7; 779 } else { 780 /* 781 * Unlike most other Outbound messages, status for 782 * a local phy operation is in DWORD 3. 783 */ 784 stsoff = 3; 785 iomb[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 786 PMCIN_LOCAL_PHY_CONTROL)); 787 iomb[1] = LE_32(pwrk->htag); 788 if (type == PMCS_PHYOP_LINK_RESET) { 789 mbar = "LOCAL PHY LINK RESET"; 790 iomb[2] = LE_32((PMCS_PHYOP_LINK_RESET << 8) | phynum); 791 } else { 792 mbar = "LOCAL PHY HARD RESET"; 793 iomb[2] = LE_32((PMCS_PHYOP_HARD_RESET << 8) | phynum); 794 } 795 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 796 "%s: sending %s to %s", __func__, mbar, pptr->path); 797 amt = 3; 798 } 799 800 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 801 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 802 if (msg == NULL) { 803 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 804 pmcs_pwork(pwp, pwrk); 805 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nomsg, __func__); 806 return (ENOMEM); 807 } 808 COPY_MESSAGE(msg, iomb, amt); 809 htag = pwrk->htag; 810 811 /* SMP serialization */ 812 pmcs_smp_acquire(pptr->iport); 813 814 pwrk->state = PMCS_WORK_STATE_ONCHIP; 815 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 816 817 pmcs_unlock_phy(pptr); 818 WAIT_FOR(pwrk, 1000, result); 819 pmcs_pwork(pwp, pwrk); 820 /* Release SMP lock before reacquiring PHY lock */ 821 pmcs_smp_release(pptr->iport); 822 pmcs_lock_phy(pptr); 823 824 if (result) { 825 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, pmcs_timeo, __func__); 826 827 if (pmcs_abort(pwp, pptr, htag, 0, 0)) { 828 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 829 "%s: Unable to issue SMP abort for htag 0x%08x", 830 __func__, htag); 831 } else { 832 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 833 "%s: Issuing SMP ABORT for htag 0x%08x", 834 __func__, htag); 835 } 836 return (EIO); 837 } 838 status = LE_32(iomb[stsoff]); 839 840 if (status != PMCOUT_STATUS_OK) { 841 char buf[32]; 842 const char *es = pmcs_status_str(status); 843 if (es == NULL) { 844 (void) snprintf(buf, sizeof (buf), "Status 0x%x", 845 status); 846 es = buf; 847 } 848 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 849 "%s: %s action returned %s for %s", __func__, mbar, es, 850 pptr->path); 851 return (status); 852 } 853 854 return (0); 855 } 856 857 /* 858 * Stop the (real) phys. No PHY or softstate locks are required as this only 859 * happens during detach. 860 */ 861 void 862 pmcs_stop_phy(pmcs_hw_t *pwp, int phynum) 863 { 864 int result; 865 pmcs_phy_t *pptr; 866 uint32_t *msg; 867 struct pmcwork *pwrk; 868 869 pptr = pwp->root_phys + phynum; 870 if (pptr == NULL) { 871 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 872 "%s: unable to find port %d", __func__, phynum); 873 return; 874 } 875 876 if (pwp->phys_started & (1 << phynum)) { 877 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 878 879 if (pwrk == NULL) { 880 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, 881 pmcs_nowrk, __func__); 882 return; 883 } 884 885 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 886 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 887 888 if (msg == NULL) { 889 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 890 pmcs_pwork(pwp, pwrk); 891 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, 892 pmcs_nomsg, __func__); 893 return; 894 } 895 896 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_EVENTS, PMCIN_PHY_STOP)); 897 msg[1] = LE_32(pwrk->htag); 898 msg[2] = LE_32(phynum); 899 pwrk->state = PMCS_WORK_STATE_ONCHIP; 900 /* 901 * Make this unconfigured now. 902 */ 903 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 904 WAIT_FOR(pwrk, 1000, result); 905 906 pmcs_pwork(pwp, pwrk); 907 if (result) { 908 pmcs_prt(pwp, PMCS_PRT_DEBUG, 909 pptr, NULL, pmcs_timeo, __func__); 910 } 911 912 pwp->phys_started &= ~(1 << phynum); 913 } 914 915 pptr->configured = 0; 916 } 917 918 /* 919 * No locks should be required as this is only called during detach 920 */ 921 void 922 pmcs_stop_phys(pmcs_hw_t *pwp) 923 { 924 int i; 925 for (i = 0; i < pwp->nphy; i++) { 926 if ((pwp->phyid_block_mask & (1 << i)) == 0) { 927 pmcs_stop_phy(pwp, i); 928 } 929 } 930 } 931 932 /* 933 * Run SAS_DIAG_EXECUTE with cmd and cmd_desc passed. 934 * ERR_CNT_RESET: return status of cmd 935 * DIAG_REPORT_GET: return value of the counter 936 */ 937 int 938 pmcs_sas_diag_execute(pmcs_hw_t *pwp, uint32_t cmd, uint32_t cmd_desc, 939 uint8_t phynum) 940 { 941 uint32_t htag, *ptr, status, msg[PMCS_MSG_SIZE << 1]; 942 int result; 943 struct pmcwork *pwrk; 944 945 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, NULL); 946 if (pwrk == NULL) { 947 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, pmcs_nowrk, __func__); 948 return (DDI_FAILURE); 949 } 950 pwrk->arg = msg; 951 htag = pwrk->htag; 952 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_EVENTS, PMCIN_SAS_DIAG_EXECUTE)); 953 msg[1] = LE_32(htag); 954 msg[2] = LE_32((cmd << PMCS_DIAG_CMD_SHIFT) | 955 (cmd_desc << PMCS_DIAG_CMD_DESC_SHIFT) | phynum); 956 957 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 958 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 959 if (ptr == NULL) { 960 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 961 pmcs_pwork(pwp, pwrk); 962 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, pmcs_nomsg, __func__); 963 return (DDI_FAILURE); 964 } 965 COPY_MESSAGE(ptr, msg, 3); 966 pwrk->state = PMCS_WORK_STATE_ONCHIP; 967 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 968 969 WAIT_FOR(pwrk, 1000, result); 970 971 pmcs_pwork(pwp, pwrk); 972 973 if (result) { 974 pmcs_timed_out(pwp, htag, __func__); 975 return (DDI_FAILURE); 976 } 977 978 status = LE_32(msg[3]); 979 980 /* Return for counter reset */ 981 if (cmd == PMCS_ERR_CNT_RESET) 982 return (status); 983 984 /* Return for counter value */ 985 if (status) { 986 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 987 "%s: failed, status (0x%x)", __func__, status); 988 return (DDI_FAILURE); 989 } 990 return (LE_32(msg[4])); 991 } 992 993 /* Get the current value of the counter for desc on phynum and return it. */ 994 int 995 pmcs_get_diag_report(pmcs_hw_t *pwp, uint32_t desc, uint8_t phynum) 996 { 997 return (pmcs_sas_diag_execute(pwp, PMCS_DIAG_REPORT_GET, desc, phynum)); 998 } 999 1000 /* Clear all of the counters for phynum. Returns the status of the command. */ 1001 int 1002 pmcs_clear_diag_counters(pmcs_hw_t *pwp, uint8_t phynum) 1003 { 1004 uint32_t cmd = PMCS_ERR_CNT_RESET; 1005 uint32_t cmd_desc; 1006 1007 cmd_desc = PMCS_INVALID_DWORD_CNT; 1008 if (pmcs_sas_diag_execute(pwp, cmd, cmd_desc, phynum)) 1009 return (DDI_FAILURE); 1010 1011 cmd_desc = PMCS_DISPARITY_ERR_CNT; 1012 if (pmcs_sas_diag_execute(pwp, cmd, cmd_desc, phynum)) 1013 return (DDI_FAILURE); 1014 1015 cmd_desc = PMCS_LOST_DWORD_SYNC_CNT; 1016 if (pmcs_sas_diag_execute(pwp, cmd, cmd_desc, phynum)) 1017 return (DDI_FAILURE); 1018 1019 cmd_desc = PMCS_RESET_FAILED_CNT; 1020 if (pmcs_sas_diag_execute(pwp, cmd, cmd_desc, phynum)) 1021 return (DDI_FAILURE); 1022 1023 return (DDI_SUCCESS); 1024 } 1025 1026 /* 1027 * Get firmware timestamp 1028 */ 1029 int 1030 pmcs_get_time_stamp(pmcs_hw_t *pwp, uint64_t *ts) 1031 { 1032 uint32_t htag, *ptr, msg[PMCS_MSG_SIZE << 1]; 1033 int result; 1034 struct pmcwork *pwrk; 1035 1036 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, NULL); 1037 if (pwrk == NULL) { 1038 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, pmcs_nowrk, __func__); 1039 return (-1); 1040 } 1041 pwrk->arg = msg; 1042 htag = pwrk->htag; 1043 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_EVENTS, PMCIN_GET_TIME_STAMP)); 1044 msg[1] = LE_32(pwrk->htag); 1045 1046 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1047 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1048 if (ptr == NULL) { 1049 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1050 pmcs_pwork(pwp, pwrk); 1051 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, pmcs_nomsg, __func__); 1052 return (-1); 1053 } 1054 COPY_MESSAGE(ptr, msg, 2); 1055 pwrk->state = PMCS_WORK_STATE_ONCHIP; 1056 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1057 1058 WAIT_FOR(pwrk, 1000, result); 1059 1060 pmcs_pwork(pwp, pwrk); 1061 1062 if (result) { 1063 pmcs_timed_out(pwp, htag, __func__); 1064 return (-1); 1065 } 1066 *ts = LE_32(msg[2]) | (((uint64_t)LE_32(msg[3])) << 32); 1067 return (0); 1068 } 1069 1070 /* 1071 * Dump all pertinent registers 1072 */ 1073 1074 void 1075 pmcs_register_dump(pmcs_hw_t *pwp) 1076 { 1077 int i; 1078 uint32_t val; 1079 1080 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "pmcs%d: Register dump start", 1081 ddi_get_instance(pwp->dip)); 1082 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 1083 "OBDB (intr): 0x%08x (mask): 0x%08x (clear): 0x%08x", 1084 pmcs_rd_msgunit(pwp, PMCS_MSGU_OBDB), 1085 pmcs_rd_msgunit(pwp, PMCS_MSGU_OBDB_MASK), 1086 pmcs_rd_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR)); 1087 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "SCRATCH0: 0x%08x", 1088 pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH0)); 1089 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "SCRATCH1: 0x%08x", 1090 pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1)); 1091 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "SCRATCH2: 0x%08x", 1092 pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2)); 1093 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "SCRATCH3: 0x%08x", 1094 pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH3)); 1095 for (i = 0; i < PMCS_NIQ; i++) { 1096 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "IQ %d: CI %u PI %u", 1097 i, pmcs_rd_iqci(pwp, i), pmcs_rd_iqpi(pwp, i)); 1098 } 1099 for (i = 0; i < PMCS_NOQ; i++) { 1100 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "OQ %d: CI %u PI %u", 1101 i, pmcs_rd_oqci(pwp, i), pmcs_rd_oqpi(pwp, i)); 1102 } 1103 val = pmcs_rd_gst_tbl(pwp, PMCS_GST_BASE); 1104 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 1105 "GST TABLE BASE: 0x%08x (STATE=0x%x QF=%d GSTLEN=%d HMI_ERR=0x%x)", 1106 val, PMCS_MPI_S(val), PMCS_QF(val), PMCS_GSTLEN(val) * 4, 1107 PMCS_HMI_ERR(val)); 1108 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "GST TABLE IQFRZ0: 0x%08x", 1109 pmcs_rd_gst_tbl(pwp, PMCS_GST_IQFRZ0)); 1110 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "GST TABLE IQFRZ1: 0x%08x", 1111 pmcs_rd_gst_tbl(pwp, PMCS_GST_IQFRZ1)); 1112 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "GST TABLE MSGU TICK: 0x%08x", 1113 pmcs_rd_gst_tbl(pwp, PMCS_GST_MSGU_TICK)); 1114 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "GST TABLE IOP TICK: 0x%08x", 1115 pmcs_rd_gst_tbl(pwp, PMCS_GST_IOP_TICK)); 1116 for (i = 0; i < pwp->nphy; i++) { 1117 uint32_t rerrf, pinfo, started = 0, link = 0; 1118 pinfo = pmcs_rd_gst_tbl(pwp, PMCS_GST_PHY_INFO(i)); 1119 if (pinfo & 1) { 1120 started = 1; 1121 link = pinfo & 2; 1122 } 1123 rerrf = pmcs_rd_gst_tbl(pwp, PMCS_GST_RERR_INFO(i)); 1124 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 1125 "GST TABLE PHY%d STARTED=%d LINK=%d RERR=0x%08x", 1126 i, started, link, rerrf); 1127 } 1128 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "pmcs%d: Register dump end", 1129 ddi_get_instance(pwp->dip)); 1130 } 1131 1132 /* 1133 * Handle SATA Abort and other error processing 1134 */ 1135 int 1136 pmcs_abort_handler(pmcs_hw_t *pwp) 1137 { 1138 pmcs_phy_t *pptr, *pnext, *pnext_uplevel[PMCS_MAX_XPND]; 1139 pmcs_xscsi_t *tgt; 1140 int r, level = 0; 1141 1142 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "%s", __func__); 1143 1144 mutex_enter(&pwp->lock); 1145 pptr = pwp->root_phys; 1146 mutex_exit(&pwp->lock); 1147 1148 while (pptr) { 1149 /* 1150 * XXX: Need to make sure this doesn't happen 1151 * XXX: when non-NCQ commands are running. 1152 */ 1153 pmcs_lock_phy(pptr); 1154 if (pptr->need_rl_ext) { 1155 ASSERT(pptr->dtype == SATA); 1156 if (pmcs_acquire_scratch(pwp, B_FALSE)) { 1157 goto next_phy; 1158 } 1159 r = pmcs_sata_abort_ncq(pwp, pptr); 1160 pmcs_release_scratch(pwp); 1161 if (r == ENOMEM) { 1162 goto next_phy; 1163 } 1164 if (r) { 1165 r = pmcs_reset_phy(pwp, pptr, 1166 PMCS_PHYOP_LINK_RESET); 1167 if (r == ENOMEM) { 1168 goto next_phy; 1169 } 1170 /* what if other failures happened? */ 1171 pptr->abort_pending = 1; 1172 pptr->abort_sent = 0; 1173 } 1174 } 1175 if (pptr->abort_pending == 0 || pptr->abort_sent) { 1176 goto next_phy; 1177 } 1178 pptr->abort_pending = 0; 1179 if (pmcs_abort(pwp, pptr, pptr->device_id, 1, 1) == ENOMEM) { 1180 pptr->abort_pending = 1; 1181 goto next_phy; 1182 } 1183 pptr->abort_sent = 1; 1184 1185 /* 1186 * If the iport is no longer active, flush the queues 1187 */ 1188 if ((pptr->iport == NULL) || 1189 (pptr->iport->ua_state != UA_ACTIVE)) { 1190 tgt = pptr->target; 1191 if (tgt) { 1192 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, tgt, 1193 "%s: Clearing target 0x%p, inactive iport", 1194 __func__, (void *) tgt); 1195 mutex_enter(&tgt->statlock); 1196 pmcs_clear_xp(pwp, tgt); 1197 mutex_exit(&tgt->statlock); 1198 } 1199 } 1200 1201 next_phy: 1202 if (pptr->children) { 1203 pnext = pptr->children; 1204 pnext_uplevel[level++] = pptr->sibling; 1205 } else { 1206 pnext = pptr->sibling; 1207 while ((pnext == NULL) && (level > 0)) { 1208 pnext = pnext_uplevel[--level]; 1209 } 1210 } 1211 1212 pmcs_unlock_phy(pptr); 1213 pptr = pnext; 1214 } 1215 1216 return (0); 1217 } 1218 1219 /* 1220 * Register a device (get a device handle for it). 1221 * Called with PHY lock held. 1222 */ 1223 int 1224 pmcs_register_device(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 1225 { 1226 struct pmcwork *pwrk; 1227 int result = 0; 1228 uint32_t *msg; 1229 uint32_t tmp, status; 1230 uint32_t iomb[(PMCS_QENTRY_SIZE << 1) >> 2]; 1231 1232 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1233 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1234 1235 if (msg == NULL || 1236 (pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr)) == NULL) { 1237 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1238 result = ENOMEM; 1239 goto out; 1240 } 1241 1242 pwrk->arg = iomb; 1243 pwrk->dtype = pptr->dtype; 1244 1245 msg[1] = LE_32(pwrk->htag); 1246 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, PMCIN_REGISTER_DEVICE)); 1247 tmp = PMCS_DEVREG_TLR | 1248 (pptr->link_rate << PMCS_DEVREG_LINK_RATE_SHIFT); 1249 if (IS_ROOT_PHY(pptr)) { 1250 msg[2] = LE_32(pptr->portid | 1251 (pptr->phynum << PMCS_PHYID_SHIFT)); 1252 } else { 1253 msg[2] = LE_32(pptr->portid); 1254 } 1255 if (pptr->dtype == SATA) { 1256 if (IS_ROOT_PHY(pptr)) { 1257 tmp |= PMCS_DEVREG_TYPE_SATA_DIRECT; 1258 } else { 1259 tmp |= PMCS_DEVREG_TYPE_SATA; 1260 } 1261 } else { 1262 tmp |= PMCS_DEVREG_TYPE_SAS; 1263 } 1264 msg[3] = LE_32(tmp); 1265 msg[4] = LE_32(PMCS_DEVREG_IT_NEXUS_TIMEOUT); 1266 (void) memcpy(&msg[5], pptr->sas_address, 8); 1267 1268 CLEAN_MESSAGE(msg, 7); 1269 pwrk->state = PMCS_WORK_STATE_ONCHIP; 1270 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1271 1272 pmcs_unlock_phy(pptr); 1273 WAIT_FOR(pwrk, 250, result); 1274 pmcs_lock_phy(pptr); 1275 pmcs_pwork(pwp, pwrk); 1276 1277 if (result) { 1278 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, pmcs_timeo, __func__); 1279 result = ETIMEDOUT; 1280 goto out; 1281 } 1282 status = LE_32(iomb[2]); 1283 tmp = LE_32(iomb[3]); 1284 switch (status) { 1285 case PMCS_DEVREG_OK: 1286 case PMCS_DEVREG_DEVICE_ALREADY_REGISTERED: 1287 case PMCS_DEVREG_PHY_ALREADY_REGISTERED: 1288 if (pmcs_validate_devid(pwp->root_phys, pptr, tmp) == B_FALSE) { 1289 result = EEXIST; 1290 goto out; 1291 } else if (status != PMCS_DEVREG_OK) { 1292 if (tmp == 0xffffffff) { /* F/W bug */ 1293 pmcs_prt(pwp, PMCS_PRT_INFO, pptr, NULL, 1294 "%s: phy %s already has bogus devid 0x%x", 1295 __func__, pptr->path, tmp); 1296 result = EIO; 1297 goto out; 1298 } else { 1299 pmcs_prt(pwp, PMCS_PRT_INFO, pptr, NULL, 1300 "%s: phy %s already has a device id 0x%x", 1301 __func__, pptr->path, tmp); 1302 } 1303 } 1304 break; 1305 default: 1306 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 1307 "%s: status 0x%x when trying to register device %s", 1308 __func__, status, pptr->path); 1309 result = EIO; 1310 goto out; 1311 } 1312 pptr->device_id = tmp; 1313 pptr->valid_device_id = 1; 1314 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "Phy %s/" SAS_ADDR_FMT 1315 " registered with device_id 0x%x (portid %d)", pptr->path, 1316 SAS_ADDR_PRT(pptr->sas_address), tmp, pptr->portid); 1317 out: 1318 return (result); 1319 } 1320 1321 /* 1322 * Deregister a device (remove a device handle). 1323 * Called with PHY locked. 1324 */ 1325 void 1326 pmcs_deregister_device(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 1327 { 1328 struct pmcwork *pwrk; 1329 uint32_t msg[PMCS_MSG_SIZE], *ptr, status; 1330 uint32_t iomb[(PMCS_QENTRY_SIZE << 1) >> 2]; 1331 int result; 1332 1333 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 1334 if (pwrk == NULL) { 1335 return; 1336 } 1337 1338 pwrk->arg = iomb; 1339 pwrk->dtype = pptr->dtype; 1340 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1341 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1342 if (ptr == NULL) { 1343 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1344 pmcs_pwork(pwp, pwrk); 1345 return; 1346 } 1347 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 1348 PMCIN_DEREGISTER_DEVICE_HANDLE)); 1349 msg[1] = LE_32(pwrk->htag); 1350 msg[2] = LE_32(pptr->device_id); 1351 pwrk->state = PMCS_WORK_STATE_ONCHIP; 1352 COPY_MESSAGE(ptr, msg, 3); 1353 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1354 1355 pmcs_unlock_phy(pptr); 1356 WAIT_FOR(pwrk, 250, result); 1357 pmcs_pwork(pwp, pwrk); 1358 pmcs_lock_phy(pptr); 1359 1360 if (result) { 1361 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, pmcs_timeo, __func__); 1362 return; 1363 } 1364 status = LE_32(iomb[2]); 1365 if (status != PMCOUT_STATUS_OK) { 1366 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 1367 "%s: status 0x%x when trying to deregister device %s", 1368 __func__, status, pptr->path); 1369 } else { 1370 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 1371 "%s: device %s deregistered", __func__, pptr->path); 1372 pptr->valid_device_id = 0; 1373 pptr->device_id = PMCS_INVALID_DEVICE_ID; 1374 pptr->configured = 0; 1375 pptr->deregister_wait = 0; 1376 } 1377 } 1378 1379 /* 1380 * Deregister all registered devices. 1381 */ 1382 void 1383 pmcs_deregister_devices(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 1384 { 1385 /* 1386 * Start at the maximum level and walk back to level 0. This only 1387 * gets done during detach after all threads and timers have been 1388 * destroyed, so there's no need to hold the softstate or PHY lock. 1389 */ 1390 while (phyp) { 1391 if (phyp->children) { 1392 pmcs_deregister_devices(pwp, phyp->children); 1393 } 1394 if (phyp->valid_device_id) { 1395 pmcs_deregister_device(pwp, phyp); 1396 } 1397 phyp = phyp->sibling; 1398 } 1399 } 1400 1401 /* 1402 * Perform a 'soft' reset on the PMC chip 1403 */ 1404 int 1405 pmcs_soft_reset(pmcs_hw_t *pwp, boolean_t no_restart) 1406 { 1407 uint32_t s2, sfrbits, gsm, rapchk, wapchk, wdpchk, spc, tsmode; 1408 pmcs_phy_t *pptr; 1409 char *msg = NULL; 1410 int i; 1411 1412 /* 1413 * Disable interrupts 1414 */ 1415 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_MASK, 0xffffffff); 1416 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR, 0xffffffff); 1417 1418 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "%s", __func__); 1419 1420 if (pwp->locks_initted) { 1421 mutex_enter(&pwp->lock); 1422 } 1423 pwp->blocked = 1; 1424 1425 /* 1426 * Clear our softstate copies of the MSGU and IOP heartbeats. 1427 */ 1428 pwp->last_msgu_tick = pwp->last_iop_tick = 0; 1429 1430 /* 1431 * Step 1 1432 */ 1433 s2 = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2); 1434 if ((s2 & PMCS_MSGU_HOST_SOFT_RESET_READY) == 0) { 1435 pmcs_wr_gsm_reg(pwp, RB6_ACCESS, RB6_NMI_SIGNATURE); 1436 pmcs_wr_gsm_reg(pwp, RB6_ACCESS, RB6_NMI_SIGNATURE); 1437 for (i = 0; i < 100; i++) { 1438 s2 = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2) & 1439 PMCS_MSGU_HOST_SOFT_RESET_READY; 1440 if (s2) { 1441 break; 1442 } 1443 drv_usecwait(10000); 1444 } 1445 s2 = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2) & 1446 PMCS_MSGU_HOST_SOFT_RESET_READY; 1447 if (s2 == 0) { 1448 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1449 "%s: PMCS_MSGU_HOST_SOFT_RESET_READY never came " 1450 "ready", __func__); 1451 pmcs_register_dump(pwp); 1452 if ((pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1) & 1453 PMCS_MSGU_CPU_SOFT_RESET_READY) == 0 || 1454 (pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2) & 1455 PMCS_MSGU_CPU_SOFT_RESET_READY) == 0) { 1456 pwp->state = STATE_DEAD; 1457 pwp->blocked = 0; 1458 if (pwp->locks_initted) { 1459 mutex_exit(&pwp->lock); 1460 } 1461 return (-1); 1462 } 1463 } 1464 } 1465 1466 /* 1467 * Step 2 1468 */ 1469 pmcs_wr_gsm_reg(pwp, NMI_EN_VPE0_IOP, 0); 1470 drv_usecwait(10); 1471 pmcs_wr_gsm_reg(pwp, NMI_EN_VPE0_AAP1, 0); 1472 drv_usecwait(10); 1473 pmcs_wr_topunit(pwp, PMCS_EVENT_INT_ENABLE, 0); 1474 drv_usecwait(10); 1475 pmcs_wr_topunit(pwp, PMCS_EVENT_INT_STAT, 1476 pmcs_rd_topunit(pwp, PMCS_EVENT_INT_STAT)); 1477 drv_usecwait(10); 1478 pmcs_wr_topunit(pwp, PMCS_ERROR_INT_ENABLE, 0); 1479 drv_usecwait(10); 1480 pmcs_wr_topunit(pwp, PMCS_ERROR_INT_STAT, 1481 pmcs_rd_topunit(pwp, PMCS_ERROR_INT_STAT)); 1482 drv_usecwait(10); 1483 1484 sfrbits = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1) & 1485 PMCS_MSGU_AAP_SFR_PROGRESS; 1486 sfrbits ^= PMCS_MSGU_AAP_SFR_PROGRESS; 1487 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "PMCS_MSGU_HOST_SCRATCH0 " 1488 "%08x -> %08x", pmcs_rd_msgunit(pwp, PMCS_MSGU_HOST_SCRATCH0), 1489 HST_SFT_RESET_SIG); 1490 pmcs_wr_msgunit(pwp, PMCS_MSGU_HOST_SCRATCH0, HST_SFT_RESET_SIG); 1491 1492 /* 1493 * Step 3 1494 */ 1495 gsm = pmcs_rd_gsm_reg(pwp, GSM_CFG_AND_RESET); 1496 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "GSM %08x -> %08x", gsm, 1497 gsm & ~PMCS_SOFT_RESET_BITS); 1498 pmcs_wr_gsm_reg(pwp, GSM_CFG_AND_RESET, gsm & ~PMCS_SOFT_RESET_BITS); 1499 1500 /* 1501 * Step 4 1502 */ 1503 rapchk = pmcs_rd_gsm_reg(pwp, READ_ADR_PARITY_CHK_EN); 1504 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "READ_ADR_PARITY_CHK_EN " 1505 "%08x -> %08x", rapchk, 0); 1506 pmcs_wr_gsm_reg(pwp, READ_ADR_PARITY_CHK_EN, 0); 1507 wapchk = pmcs_rd_gsm_reg(pwp, WRITE_ADR_PARITY_CHK_EN); 1508 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "WRITE_ADR_PARITY_CHK_EN " 1509 "%08x -> %08x", wapchk, 0); 1510 pmcs_wr_gsm_reg(pwp, WRITE_ADR_PARITY_CHK_EN, 0); 1511 wdpchk = pmcs_rd_gsm_reg(pwp, WRITE_DATA_PARITY_CHK_EN); 1512 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "WRITE_DATA_PARITY_CHK_EN " 1513 "%08x -> %08x", wdpchk, 0); 1514 pmcs_wr_gsm_reg(pwp, WRITE_DATA_PARITY_CHK_EN, 0); 1515 1516 /* 1517 * Step 5 1518 */ 1519 drv_usecwait(100); 1520 1521 /* 1522 * Step 5.5 (Temporary workaround for 1.07.xx Beta) 1523 */ 1524 tsmode = pmcs_rd_gsm_reg(pwp, PMCS_GPIO_TRISTATE_MODE_ADDR); 1525 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "GPIO TSMODE %08x -> %08x", 1526 tsmode, tsmode & ~(PMCS_GPIO_TSMODE_BIT0|PMCS_GPIO_TSMODE_BIT1)); 1527 pmcs_wr_gsm_reg(pwp, PMCS_GPIO_TRISTATE_MODE_ADDR, 1528 tsmode & ~(PMCS_GPIO_TSMODE_BIT0|PMCS_GPIO_TSMODE_BIT1)); 1529 drv_usecwait(10); 1530 1531 /* 1532 * Step 6 1533 */ 1534 spc = pmcs_rd_topunit(pwp, PMCS_SPC_RESET); 1535 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "SPC_RESET %08x -> %08x", 1536 spc, spc & ~(PCS_IOP_SS_RSTB|PCS_AAP1_SS_RSTB)); 1537 pmcs_wr_topunit(pwp, PMCS_SPC_RESET, 1538 spc & ~(PCS_IOP_SS_RSTB|PCS_AAP1_SS_RSTB)); 1539 drv_usecwait(10); 1540 1541 /* 1542 * Step 7 1543 */ 1544 spc = pmcs_rd_topunit(pwp, PMCS_SPC_RESET); 1545 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "SPC_RESET %08x -> %08x", 1546 spc, spc & ~(BDMA_CORE_RSTB|OSSP_RSTB)); 1547 pmcs_wr_topunit(pwp, PMCS_SPC_RESET, spc & ~(BDMA_CORE_RSTB|OSSP_RSTB)); 1548 1549 /* 1550 * Step 8 1551 */ 1552 drv_usecwait(100); 1553 1554 /* 1555 * Step 9 1556 */ 1557 spc = pmcs_rd_topunit(pwp, PMCS_SPC_RESET); 1558 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "SPC_RESET %08x -> %08x", 1559 spc, spc | (BDMA_CORE_RSTB|OSSP_RSTB)); 1560 pmcs_wr_topunit(pwp, PMCS_SPC_RESET, spc | (BDMA_CORE_RSTB|OSSP_RSTB)); 1561 1562 /* 1563 * Step 10 1564 */ 1565 drv_usecwait(100); 1566 1567 /* 1568 * Step 11 1569 */ 1570 gsm = pmcs_rd_gsm_reg(pwp, GSM_CFG_AND_RESET); 1571 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "GSM %08x -> %08x", gsm, 1572 gsm | PMCS_SOFT_RESET_BITS); 1573 pmcs_wr_gsm_reg(pwp, GSM_CFG_AND_RESET, gsm | PMCS_SOFT_RESET_BITS); 1574 drv_usecwait(10); 1575 1576 /* 1577 * Step 12 1578 */ 1579 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "READ_ADR_PARITY_CHK_EN " 1580 "%08x -> %08x", pmcs_rd_gsm_reg(pwp, READ_ADR_PARITY_CHK_EN), 1581 rapchk); 1582 pmcs_wr_gsm_reg(pwp, READ_ADR_PARITY_CHK_EN, rapchk); 1583 drv_usecwait(10); 1584 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "WRITE_ADR_PARITY_CHK_EN " 1585 "%08x -> %08x", pmcs_rd_gsm_reg(pwp, WRITE_ADR_PARITY_CHK_EN), 1586 wapchk); 1587 pmcs_wr_gsm_reg(pwp, WRITE_ADR_PARITY_CHK_EN, wapchk); 1588 drv_usecwait(10); 1589 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "WRITE_DATA_PARITY_CHK_EN " 1590 "%08x -> %08x", pmcs_rd_gsm_reg(pwp, WRITE_DATA_PARITY_CHK_EN), 1591 wapchk); 1592 pmcs_wr_gsm_reg(pwp, WRITE_DATA_PARITY_CHK_EN, wdpchk); 1593 drv_usecwait(10); 1594 1595 /* 1596 * Step 13 1597 */ 1598 spc = pmcs_rd_topunit(pwp, PMCS_SPC_RESET); 1599 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "SPC_RESET %08x -> %08x", 1600 spc, spc | (PCS_IOP_SS_RSTB|PCS_AAP1_SS_RSTB)); 1601 pmcs_wr_topunit(pwp, PMCS_SPC_RESET, 1602 spc | (PCS_IOP_SS_RSTB|PCS_AAP1_SS_RSTB)); 1603 1604 /* 1605 * Step 14 1606 */ 1607 drv_usecwait(100); 1608 1609 /* 1610 * Step 15 1611 */ 1612 for (spc = 0, i = 0; i < 1000; i++) { 1613 drv_usecwait(1000); 1614 spc = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1); 1615 if ((spc & PMCS_MSGU_AAP_SFR_PROGRESS) == sfrbits) { 1616 break; 1617 } 1618 } 1619 1620 if ((spc & PMCS_MSGU_AAP_SFR_PROGRESS) != sfrbits) { 1621 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1622 "SFR didn't toggle (sfr 0x%x)", spc); 1623 pwp->state = STATE_DEAD; 1624 pwp->blocked = 0; 1625 if (pwp->locks_initted) { 1626 mutex_exit(&pwp->lock); 1627 } 1628 return (-1); 1629 } 1630 1631 /* 1632 * Step 16 1633 */ 1634 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_MASK, 0xffffffff); 1635 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR, 0xffffffff); 1636 1637 /* 1638 * Wait for up to 5 seconds for AAP state to come either ready or error. 1639 */ 1640 for (i = 0; i < 50; i++) { 1641 spc = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1) & 1642 PMCS_MSGU_AAP_STATE_MASK; 1643 if (spc == PMCS_MSGU_AAP_STATE_ERROR || 1644 spc == PMCS_MSGU_AAP_STATE_READY) { 1645 break; 1646 } 1647 drv_usecwait(100000); 1648 } 1649 spc = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1); 1650 if ((spc & PMCS_MSGU_AAP_STATE_MASK) != PMCS_MSGU_AAP_STATE_READY) { 1651 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1652 "soft reset failed (state 0x%x)", spc); 1653 pwp->state = STATE_DEAD; 1654 pwp->blocked = 0; 1655 if (pwp->locks_initted) { 1656 mutex_exit(&pwp->lock); 1657 } 1658 return (-1); 1659 } 1660 1661 /* Clear the firmware log */ 1662 if (pwp->fwlogp) { 1663 bzero(pwp->fwlogp, PMCS_FWLOG_SIZE); 1664 } 1665 1666 /* Reset our queue indices and entries */ 1667 bzero(pwp->shadow_iqpi, sizeof (pwp->shadow_iqpi)); 1668 bzero(pwp->last_iqci, sizeof (pwp->last_iqci)); 1669 for (i = 0; i < PMCS_NIQ; i++) { 1670 if (pwp->iqp[i]) { 1671 bzero(pwp->iqp[i], PMCS_QENTRY_SIZE * pwp->ioq_depth); 1672 pmcs_wr_iqpi(pwp, i, 0); 1673 pmcs_wr_iqci(pwp, i, 0); 1674 } 1675 } 1676 for (i = 0; i < PMCS_NOQ; i++) { 1677 if (pwp->oqp[i]) { 1678 bzero(pwp->oqp[i], PMCS_QENTRY_SIZE * pwp->ioq_depth); 1679 pmcs_wr_oqpi(pwp, i, 0); 1680 pmcs_wr_oqci(pwp, i, 0); 1681 } 1682 1683 } 1684 1685 if (pwp->state == STATE_DEAD || pwp->state == STATE_UNPROBING || 1686 pwp->state == STATE_PROBING || pwp->locks_initted == 0) { 1687 pwp->blocked = 0; 1688 if (pwp->locks_initted) { 1689 mutex_exit(&pwp->lock); 1690 } 1691 return (0); 1692 } 1693 1694 /* 1695 * Return at this point if we dont need to startup. 1696 */ 1697 if (no_restart) { 1698 return (0); 1699 } 1700 1701 ASSERT(pwp->locks_initted != 0); 1702 1703 /* 1704 * Flush the target queues and clear each target's PHY 1705 */ 1706 if (pwp->targets) { 1707 for (i = 0; i < pwp->max_dev; i++) { 1708 pmcs_xscsi_t *xp = pwp->targets[i]; 1709 1710 if (xp == NULL) { 1711 continue; 1712 } 1713 1714 mutex_enter(&xp->statlock); 1715 pmcs_flush_target_queues(pwp, xp, PMCS_TGT_ALL_QUEUES); 1716 xp->phy = NULL; 1717 mutex_exit(&xp->statlock); 1718 } 1719 } 1720 1721 /* 1722 * Zero out the ports list, free non root phys, clear root phys 1723 */ 1724 bzero(pwp->ports, sizeof (pwp->ports)); 1725 pmcs_free_all_phys(pwp, pwp->root_phys); 1726 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 1727 pmcs_lock_phy(pptr); 1728 pmcs_clear_phy(pwp, pptr); 1729 pptr->target = NULL; 1730 pmcs_unlock_phy(pptr); 1731 } 1732 1733 /* 1734 * Restore Interrupt Mask 1735 */ 1736 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_MASK, pwp->intr_mask); 1737 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR, 0xffffffff); 1738 1739 pwp->mpi_table_setup = 0; 1740 mutex_exit(&pwp->lock); 1741 1742 /* 1743 * Set up MPI again. 1744 */ 1745 if (pmcs_setup(pwp)) { 1746 msg = "unable to setup MPI tables again"; 1747 goto fail_restart; 1748 } 1749 pmcs_report_fwversion(pwp); 1750 1751 /* 1752 * Restart MPI 1753 */ 1754 if (pmcs_start_mpi(pwp)) { 1755 msg = "unable to restart MPI again"; 1756 goto fail_restart; 1757 } 1758 1759 mutex_enter(&pwp->lock); 1760 SCHEDULE_WORK(pwp, PMCS_WORK_RUN_QUEUES); 1761 mutex_exit(&pwp->lock); 1762 1763 /* 1764 * Run any completions 1765 */ 1766 PMCS_CQ_RUN(pwp); 1767 1768 /* 1769 * Delay 1770 */ 1771 drv_usecwait(1000000); 1772 return (0); 1773 1774 fail_restart: 1775 mutex_enter(&pwp->lock); 1776 pwp->state = STATE_DEAD; 1777 mutex_exit(&pwp->lock); 1778 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, 1779 "%s: Failed: %s", __func__, msg); 1780 return (-1); 1781 } 1782 1783 1784 /* 1785 * Perform a 'hot' reset, which will soft reset the chip and 1786 * restore the state back to pre-reset context. Called with pwp 1787 * lock held. 1788 */ 1789 int 1790 pmcs_hot_reset(pmcs_hw_t *pwp) 1791 { 1792 pmcs_iport_t *iport; 1793 1794 ASSERT(mutex_owned(&pwp->lock)); 1795 pwp->state = STATE_IN_RESET; 1796 1797 /* 1798 * For any iports on this HBA, report empty target sets and 1799 * then tear them down. 1800 */ 1801 rw_enter(&pwp->iports_lock, RW_READER); 1802 for (iport = list_head(&pwp->iports); iport != NULL; 1803 iport = list_next(&pwp->iports, iport)) { 1804 mutex_enter(&iport->lock); 1805 (void) scsi_hba_tgtmap_set_begin(iport->iss_tgtmap); 1806 (void) scsi_hba_tgtmap_set_end(iport->iss_tgtmap, 0); 1807 pmcs_iport_teardown_phys(iport); 1808 mutex_exit(&iport->lock); 1809 } 1810 rw_exit(&pwp->iports_lock); 1811 1812 /* Grab a register dump, in the event that reset fails */ 1813 pmcs_register_dump_int(pwp); 1814 mutex_exit(&pwp->lock); 1815 1816 /* Issue soft reset and clean up related softstate */ 1817 if (pmcs_soft_reset(pwp, B_FALSE)) { 1818 /* 1819 * Disable interrupts, in case we got far enough along to 1820 * enable them, then fire off ereport and service impact. 1821 */ 1822 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1823 "%s: failed soft reset", __func__); 1824 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_MASK, 0xffffffff); 1825 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR, 0xffffffff); 1826 pmcs_fm_ereport(pwp, DDI_FM_DEVICE_NO_RESPONSE); 1827 ddi_fm_service_impact(pwp->dip, DDI_SERVICE_LOST); 1828 mutex_enter(&pwp->lock); 1829 pwp->state = STATE_DEAD; 1830 return (DDI_FAILURE); 1831 } 1832 1833 mutex_enter(&pwp->lock); 1834 pwp->state = STATE_RUNNING; 1835 mutex_exit(&pwp->lock); 1836 1837 /* 1838 * Finally, restart the phys, which will bring the iports back 1839 * up and eventually result in discovery running. 1840 */ 1841 if (pmcs_start_phys(pwp)) { 1842 /* We should be up and running now, so retry */ 1843 if (pmcs_start_phys(pwp)) { 1844 /* Apparently unable to restart PHYs, fail */ 1845 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1846 "%s: failed to restart PHYs after soft reset", 1847 __func__); 1848 mutex_enter(&pwp->lock); 1849 return (DDI_FAILURE); 1850 } 1851 } 1852 1853 mutex_enter(&pwp->lock); 1854 return (DDI_SUCCESS); 1855 } 1856 1857 /* 1858 * Reset a device or a logical unit. 1859 */ 1860 int 1861 pmcs_reset_dev(pmcs_hw_t *pwp, pmcs_phy_t *pptr, uint64_t lun) 1862 { 1863 int rval = 0; 1864 1865 if (pptr == NULL) { 1866 return (ENXIO); 1867 } 1868 1869 pmcs_lock_phy(pptr); 1870 if (pptr->dtype == SAS) { 1871 /* 1872 * Some devices do not support SAS_I_T_NEXUS_RESET as 1873 * it is not a mandatory (in SAM4) task management 1874 * function, while LOGIC_UNIT_RESET is mandatory. 1875 * 1876 * The problem here is that we need to iterate over 1877 * all known LUNs to emulate the semantics of 1878 * "RESET_TARGET". 1879 * 1880 * XXX: FIX ME 1881 */ 1882 if (lun == (uint64_t)-1) { 1883 lun = 0; 1884 } 1885 rval = pmcs_ssp_tmf(pwp, pptr, SAS_LOGICAL_UNIT_RESET, 0, lun, 1886 NULL); 1887 } else if (pptr->dtype == SATA) { 1888 if (lun != 0ull) { 1889 pmcs_unlock_phy(pptr); 1890 return (EINVAL); 1891 } 1892 rval = pmcs_reset_phy(pwp, pptr, PMCS_PHYOP_LINK_RESET); 1893 } else { 1894 pmcs_unlock_phy(pptr); 1895 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 1896 "%s: cannot reset a SMP device yet (%s)", 1897 __func__, pptr->path); 1898 return (EINVAL); 1899 } 1900 1901 /* 1902 * Now harvest any commands killed by this action 1903 * by issuing an ABORT for all commands on this device. 1904 * 1905 * We do this even if the the tmf or reset fails (in case there 1906 * are any dead commands around to be harvested *anyway*). 1907 * We don't have to await for the abort to complete. 1908 */ 1909 if (pmcs_abort(pwp, pptr, 0, 1, 0)) { 1910 pptr->abort_pending = 1; 1911 SCHEDULE_WORK(pwp, PMCS_WORK_ABORT_HANDLE); 1912 } 1913 1914 pmcs_unlock_phy(pptr); 1915 return (rval); 1916 } 1917 1918 /* 1919 * Called with PHY locked. 1920 */ 1921 static int 1922 pmcs_get_device_handle(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 1923 { 1924 if (pptr->valid_device_id == 0) { 1925 int result = pmcs_register_device(pwp, pptr); 1926 1927 /* 1928 * If we changed while registering, punt 1929 */ 1930 if (pptr->changed) { 1931 RESTART_DISCOVERY(pwp); 1932 return (-1); 1933 } 1934 1935 /* 1936 * If we had a failure to register, check against errors. 1937 * An ENOMEM error means we just retry (temp resource shortage). 1938 */ 1939 if (result == ENOMEM) { 1940 PHY_CHANGED(pwp, pptr); 1941 RESTART_DISCOVERY(pwp); 1942 return (-1); 1943 } 1944 1945 /* 1946 * An ETIMEDOUT error means we retry (if our counter isn't 1947 * exhausted) 1948 */ 1949 if (result == ETIMEDOUT) { 1950 if (ddi_get_lbolt() < pptr->config_stop) { 1951 PHY_CHANGED(pwp, pptr); 1952 RESTART_DISCOVERY(pwp); 1953 } else { 1954 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 1955 "%s: Retries exhausted for %s, killing", 1956 __func__, pptr->path); 1957 pptr->config_stop = 0; 1958 pmcs_kill_changed(pwp, pptr, 0); 1959 } 1960 return (-1); 1961 } 1962 /* 1963 * Other errors or no valid device id is fatal, but don't 1964 * preclude a future action. 1965 */ 1966 if (result || pptr->valid_device_id == 0) { 1967 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 1968 "%s: %s could not be registered", __func__, 1969 pptr->path); 1970 return (-1); 1971 } 1972 } 1973 return (0); 1974 } 1975 1976 int 1977 pmcs_iport_tgtmap_create(pmcs_iport_t *iport) 1978 { 1979 ASSERT(iport); 1980 if (iport == NULL) 1981 return (B_FALSE); 1982 1983 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s", __func__); 1984 1985 /* create target map */ 1986 if (scsi_hba_tgtmap_create(iport->dip, SCSI_TM_FULLSET, tgtmap_usec, 1987 (void *)iport, pmcs_tgtmap_activate_cb, pmcs_tgtmap_deactivate_cb, 1988 &iport->iss_tgtmap) != DDI_SUCCESS) { 1989 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG, NULL, NULL, 1990 "%s: failed to create tgtmap", __func__); 1991 return (B_FALSE); 1992 } 1993 return (B_TRUE); 1994 } 1995 1996 int 1997 pmcs_iport_tgtmap_destroy(pmcs_iport_t *iport) 1998 { 1999 ASSERT(iport && iport->iss_tgtmap); 2000 if ((iport == NULL) || (iport->iss_tgtmap == NULL)) 2001 return (B_FALSE); 2002 2003 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s", __func__); 2004 2005 /* destroy target map */ 2006 scsi_hba_tgtmap_destroy(iport->iss_tgtmap); 2007 return (B_TRUE); 2008 } 2009 2010 /* 2011 * Remove all phys from an iport's phymap and empty it's phylist. 2012 * Called when a port has been reset by the host (see pmcs_intr.c) 2013 * or prior to issuing a soft reset if we detect a stall on the chip 2014 * (see pmcs_attach.c). 2015 */ 2016 void 2017 pmcs_iport_teardown_phys(pmcs_iport_t *iport) 2018 { 2019 pmcs_hw_t *pwp; 2020 sas_phymap_phys_t *phys; 2021 int phynum; 2022 2023 ASSERT(iport); 2024 ASSERT(mutex_owned(&iport->lock)); 2025 pwp = iport->pwp; 2026 ASSERT(pwp); 2027 2028 /* 2029 * Remove all phys from the iport handle's phy list, unset its 2030 * primary phy and update its state. 2031 */ 2032 pmcs_remove_phy_from_iport(iport, NULL); 2033 iport->pptr = NULL; 2034 iport->ua_state = UA_PEND_DEACTIVATE; 2035 2036 /* Remove all phys from the phymap */ 2037 phys = sas_phymap_ua2phys(pwp->hss_phymap, iport->ua); 2038 if (phys) { 2039 while ((phynum = sas_phymap_phys_next(phys)) != -1) { 2040 (void) sas_phymap_phy_rem(pwp->hss_phymap, phynum); 2041 } 2042 sas_phymap_phys_free(phys); 2043 } 2044 } 2045 2046 /* 2047 * Query the phymap and populate the iport handle passed in. 2048 * Called with iport lock held. 2049 */ 2050 int 2051 pmcs_iport_configure_phys(pmcs_iport_t *iport) 2052 { 2053 pmcs_hw_t *pwp; 2054 pmcs_phy_t *pptr; 2055 sas_phymap_phys_t *phys; 2056 int phynum; 2057 int inst; 2058 2059 ASSERT(iport); 2060 ASSERT(mutex_owned(&iport->lock)); 2061 pwp = iport->pwp; 2062 ASSERT(pwp); 2063 inst = ddi_get_instance(iport->dip); 2064 2065 mutex_enter(&pwp->lock); 2066 ASSERT(pwp->root_phys != NULL); 2067 2068 /* 2069 * Query the phymap regarding the phys in this iport and populate 2070 * the iport's phys list. Hereafter this list is maintained via 2071 * port up and down events in pmcs_intr.c 2072 */ 2073 ASSERT(list_is_empty(&iport->phys)); 2074 phys = sas_phymap_ua2phys(pwp->hss_phymap, iport->ua); 2075 ASSERT(phys != NULL); 2076 while ((phynum = sas_phymap_phys_next(phys)) != -1) { 2077 /* Grab the phy pointer from root_phys */ 2078 pptr = pwp->root_phys + phynum; 2079 ASSERT(pptr); 2080 pmcs_lock_phy(pptr); 2081 ASSERT(pptr->phynum == phynum); 2082 2083 /* 2084 * Set a back pointer in the phy to this iport. 2085 */ 2086 pptr->iport = iport; 2087 2088 /* 2089 * If this phy is the primary, set a pointer to it on our 2090 * iport handle, and set our portid from it. 2091 */ 2092 if (!pptr->subsidiary) { 2093 iport->pptr = pptr; 2094 iport->portid = pptr->portid; 2095 } 2096 2097 /* 2098 * Finally, insert the phy into our list 2099 */ 2100 pmcs_unlock_phy(pptr); 2101 pmcs_add_phy_to_iport(iport, pptr); 2102 2103 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "%s: found " 2104 "phy %d [0x%p] on iport%d, refcnt(%d)", __func__, phynum, 2105 (void *)pptr, inst, iport->refcnt); 2106 } 2107 mutex_exit(&pwp->lock); 2108 sas_phymap_phys_free(phys); 2109 RESTART_DISCOVERY(pwp); 2110 return (DDI_SUCCESS); 2111 } 2112 2113 /* 2114 * Return the iport that ua is associated with, or NULL. If an iport is 2115 * returned, it will be held and the caller must release the hold. 2116 */ 2117 static pmcs_iport_t * 2118 pmcs_get_iport_by_ua(pmcs_hw_t *pwp, char *ua) 2119 { 2120 pmcs_iport_t *iport = NULL; 2121 2122 rw_enter(&pwp->iports_lock, RW_READER); 2123 for (iport = list_head(&pwp->iports); 2124 iport != NULL; 2125 iport = list_next(&pwp->iports, iport)) { 2126 mutex_enter(&iport->lock); 2127 if (strcmp(iport->ua, ua) == 0) { 2128 mutex_exit(&iport->lock); 2129 mutex_enter(&iport->refcnt_lock); 2130 iport->refcnt++; 2131 mutex_exit(&iport->refcnt_lock); 2132 break; 2133 } 2134 mutex_exit(&iport->lock); 2135 } 2136 rw_exit(&pwp->iports_lock); 2137 2138 return (iport); 2139 } 2140 2141 /* 2142 * Return the iport that pptr is associated with, or NULL. 2143 * If an iport is returned, there is a hold that the caller must release. 2144 */ 2145 pmcs_iport_t * 2146 pmcs_get_iport_by_wwn(pmcs_hw_t *pwp, uint64_t wwn) 2147 { 2148 pmcs_iport_t *iport = NULL; 2149 char *ua; 2150 2151 ua = sas_phymap_lookup_ua(pwp->hss_phymap, pwp->sas_wwns[0], wwn); 2152 if (ua) { 2153 iport = pmcs_get_iport_by_ua(pwp, ua); 2154 if (iport) { 2155 mutex_enter(&iport->lock); 2156 pmcs_iport_active(iport); 2157 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "%s: " 2158 "found iport [0x%p] on ua (%s), refcnt (%d)", 2159 __func__, (void *)iport, ua, iport->refcnt); 2160 mutex_exit(&iport->lock); 2161 } 2162 } 2163 2164 return (iport); 2165 } 2166 2167 /* 2168 * Promote the next phy on this port to primary, and return it. 2169 * Called when the primary PHY on a port is going down, but the port 2170 * remains up (see pmcs_intr.c). 2171 */ 2172 pmcs_phy_t * 2173 pmcs_promote_next_phy(pmcs_phy_t *prev_primary) 2174 { 2175 pmcs_hw_t *pwp; 2176 pmcs_iport_t *iport; 2177 pmcs_phy_t *pptr, *child; 2178 int portid; 2179 2180 pmcs_lock_phy(prev_primary); 2181 portid = prev_primary->portid; 2182 iport = prev_primary->iport; 2183 pwp = prev_primary->pwp; 2184 2185 /* Use the first available phy in this port */ 2186 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 2187 if ((pptr->portid == portid) && (pptr != prev_primary)) { 2188 mutex_enter(&pptr->phy_lock); 2189 break; 2190 } 2191 } 2192 2193 if (pptr == NULL) { 2194 pmcs_unlock_phy(prev_primary); 2195 return (NULL); 2196 } 2197 2198 if (iport) { 2199 mutex_enter(&iport->lock); 2200 iport->pptr = pptr; 2201 mutex_exit(&iport->lock); 2202 } 2203 2204 /* Update the phy handle with the data from the previous primary */ 2205 pptr->children = prev_primary->children; 2206 child = pptr->children; 2207 while (child) { 2208 child->parent = pptr; 2209 child = child->sibling; 2210 } 2211 pptr->ncphy = prev_primary->ncphy; 2212 pptr->width = prev_primary->width; 2213 pptr->dtype = prev_primary->dtype; 2214 pptr->pend_dtype = prev_primary->pend_dtype; 2215 pptr->tolerates_sas2 = prev_primary->tolerates_sas2; 2216 pptr->atdt = prev_primary->atdt; 2217 pptr->portid = prev_primary->portid; 2218 pptr->link_rate = prev_primary->link_rate; 2219 pptr->configured = prev_primary->configured; 2220 pptr->iport = prev_primary->iport; 2221 pptr->target = prev_primary->target; 2222 if (pptr->target) { 2223 pptr->target->phy = pptr; 2224 } 2225 2226 /* Update the phy mask properties for the affected PHYs */ 2227 /* Clear the current values... */ 2228 pmcs_update_phy_pm_props(pptr, pptr->att_port_pm_tmp, 2229 pptr->tgt_port_pm_tmp, B_FALSE); 2230 /* ...replace with the values from prev_primary... */ 2231 pmcs_update_phy_pm_props(pptr, prev_primary->att_port_pm_tmp, 2232 prev_primary->tgt_port_pm_tmp, B_TRUE); 2233 /* ...then clear prev_primary's PHY values from the new primary */ 2234 pmcs_update_phy_pm_props(pptr, prev_primary->att_port_pm, 2235 prev_primary->tgt_port_pm, B_FALSE); 2236 /* Clear the prev_primary's values */ 2237 pmcs_update_phy_pm_props(prev_primary, prev_primary->att_port_pm_tmp, 2238 prev_primary->tgt_port_pm_tmp, B_FALSE); 2239 2240 pptr->subsidiary = 0; 2241 2242 prev_primary->subsidiary = 1; 2243 prev_primary->children = NULL; 2244 prev_primary->target = NULL; 2245 pptr->device_id = prev_primary->device_id; 2246 pptr->valid_device_id = 1; 2247 pmcs_unlock_phy(prev_primary); 2248 2249 /* 2250 * We call pmcs_unlock_phy() on pptr because it now contains the 2251 * list of children. 2252 */ 2253 pmcs_unlock_phy(pptr); 2254 2255 return (pptr); 2256 } 2257 2258 void 2259 pmcs_rele_iport(pmcs_iport_t *iport) 2260 { 2261 /* 2262 * Release a refcnt on this iport. If this is the last reference, 2263 * signal the potential waiter in pmcs_iport_unattach(). 2264 */ 2265 ASSERT(iport->refcnt > 0); 2266 mutex_enter(&iport->refcnt_lock); 2267 iport->refcnt--; 2268 mutex_exit(&iport->refcnt_lock); 2269 if (iport->refcnt == 0) { 2270 cv_signal(&iport->refcnt_cv); 2271 } 2272 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "%s: iport " 2273 "[0x%p] refcnt (%d)", __func__, (void *)iport, iport->refcnt); 2274 } 2275 2276 void 2277 pmcs_phymap_activate(void *arg, char *ua, void **privp) 2278 { 2279 _NOTE(ARGUNUSED(privp)); 2280 pmcs_hw_t *pwp = arg; 2281 pmcs_iport_t *iport = NULL; 2282 2283 mutex_enter(&pwp->lock); 2284 if ((pwp->state == STATE_UNPROBING) || (pwp->state == STATE_DEAD)) { 2285 mutex_exit(&pwp->lock); 2286 return; 2287 } 2288 pwp->phymap_active++; 2289 mutex_exit(&pwp->lock); 2290 2291 if (scsi_hba_iportmap_iport_add(pwp->hss_iportmap, ua, NULL) != 2292 DDI_SUCCESS) { 2293 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s: failed to " 2294 "add iport handle on unit address [%s]", __func__, ua); 2295 } else { 2296 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s: " 2297 "phymap_active count (%d), added iport handle on unit " 2298 "address [%s]", __func__, pwp->phymap_active, ua); 2299 } 2300 2301 /* Set the HBA softstate as our private data for this unit address */ 2302 *privp = (void *)pwp; 2303 2304 /* 2305 * We are waiting on attach for this iport node, unless it is still 2306 * attached. This can happen if a consumer has an outstanding open 2307 * on our iport node, but the port is down. If this is the case, we 2308 * need to configure our iport here for reuse. 2309 */ 2310 iport = pmcs_get_iport_by_ua(pwp, ua); 2311 if (iport) { 2312 mutex_enter(&iport->lock); 2313 if (pmcs_iport_configure_phys(iport) != DDI_SUCCESS) { 2314 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "%s: " 2315 "failed to configure phys on iport [0x%p] at " 2316 "unit address (%s)", __func__, (void *)iport, ua); 2317 } 2318 pmcs_iport_active(iport); 2319 pmcs_smhba_add_iport_prop(iport, DATA_TYPE_INT32, PMCS_NUM_PHYS, 2320 &iport->nphy); 2321 mutex_exit(&iport->lock); 2322 pmcs_rele_iport(iport); 2323 } 2324 2325 } 2326 2327 void 2328 pmcs_phymap_deactivate(void *arg, char *ua, void *privp) 2329 { 2330 _NOTE(ARGUNUSED(privp)); 2331 pmcs_hw_t *pwp = arg; 2332 pmcs_iport_t *iport; 2333 2334 mutex_enter(&pwp->lock); 2335 pwp->phymap_active--; 2336 mutex_exit(&pwp->lock); 2337 2338 if (scsi_hba_iportmap_iport_remove(pwp->hss_iportmap, ua) != 2339 DDI_SUCCESS) { 2340 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s: failed to " 2341 "remove iport handle on unit address [%s]", __func__, ua); 2342 } else { 2343 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s: " 2344 "phymap_active count (%d), removed iport handle on unit " 2345 "address [%s]", __func__, pwp->phymap_active, ua); 2346 } 2347 2348 iport = pmcs_get_iport_by_ua(pwp, ua); 2349 2350 if (iport == NULL) { 2351 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "%s: failed " 2352 "lookup of iport handle on unit addr (%s)", __func__, ua); 2353 return; 2354 } 2355 2356 mutex_enter(&iport->lock); 2357 iport->ua_state = UA_INACTIVE; 2358 iport->portid = PMCS_IPORT_INVALID_PORT_ID; 2359 pmcs_remove_phy_from_iport(iport, NULL); 2360 mutex_exit(&iport->lock); 2361 pmcs_rele_iport(iport); 2362 } 2363 2364 /* 2365 * Top-level discovery function 2366 */ 2367 void 2368 pmcs_discover(pmcs_hw_t *pwp) 2369 { 2370 pmcs_phy_t *pptr; 2371 pmcs_phy_t *root_phy; 2372 int phymap_active; 2373 2374 DTRACE_PROBE2(pmcs__discover__entry, ulong_t, pwp->work_flags, 2375 boolean_t, pwp->config_changed); 2376 2377 mutex_enter(&pwp->lock); 2378 2379 if (pwp->state != STATE_RUNNING) { 2380 mutex_exit(&pwp->lock); 2381 return; 2382 } 2383 2384 /* Ensure we have at least one phymap active */ 2385 if (pwp->phymap_active == 0) { 2386 mutex_exit(&pwp->lock); 2387 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2388 "%s: phymap inactive, exiting", __func__); 2389 return; 2390 } 2391 2392 phymap_active = pwp->phymap_active; 2393 mutex_exit(&pwp->lock); 2394 2395 /* 2396 * If no iports have attached, but we have PHYs that are up, we 2397 * are waiting for iport attach to complete. Restart discovery. 2398 */ 2399 rw_enter(&pwp->iports_lock, RW_READER); 2400 if (!pwp->iports_attached) { 2401 rw_exit(&pwp->iports_lock); 2402 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2403 "%s: no iports attached, retry discovery", __func__); 2404 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 2405 return; 2406 } 2407 if (pwp->num_iports != phymap_active) { 2408 rw_exit(&pwp->iports_lock); 2409 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2410 "%s: phymaps or iport maps not stable; retry discovery", 2411 __func__); 2412 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 2413 return; 2414 } 2415 rw_exit(&pwp->iports_lock); 2416 2417 mutex_enter(&pwp->config_lock); 2418 if (pwp->configuring) { 2419 mutex_exit(&pwp->config_lock); 2420 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2421 "%s: configuration already in progress", __func__); 2422 return; 2423 } 2424 2425 if (pmcs_acquire_scratch(pwp, B_FALSE)) { 2426 mutex_exit(&pwp->config_lock); 2427 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2428 "%s: cannot allocate scratch", __func__); 2429 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 2430 return; 2431 } 2432 2433 pwp->configuring = 1; 2434 pwp->config_changed = B_FALSE; 2435 mutex_exit(&pwp->config_lock); 2436 2437 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "Discovery begin"); 2438 2439 /* 2440 * First, tell SCSA that we're beginning set operations. 2441 */ 2442 pmcs_begin_observations(pwp); 2443 2444 /* 2445 * The order of the following traversals is important. 2446 * 2447 * The first one checks for changed expanders. 2448 * 2449 * The second one aborts commands for dead devices and deregisters them. 2450 * 2451 * The third one clears the contents of dead expanders from the tree 2452 * 2453 * The fourth one clears now dead devices in expanders that remain. 2454 */ 2455 2456 /* 2457 * 1. Check expanders marked changed (but not dead) to see if they still 2458 * have the same number of phys and the same SAS address. Mark them, 2459 * their subsidiary phys (if wide) and their descendents dead if 2460 * anything has changed. Check the devices they contain to see if 2461 * *they* have changed. If they've changed from type NOTHING we leave 2462 * them marked changed to be configured later (picking up a new SAS 2463 * address and link rate if possible). Otherwise, any change in type, 2464 * SAS address or removal of target role will cause us to mark them 2465 * (and their descendents) as dead (and cause any pending commands 2466 * and associated devices to be removed). 2467 * 2468 * NOTE: We don't want to bail on discovery if the config has 2469 * changed until *after* we run pmcs_kill_devices. 2470 */ 2471 root_phy = pwp->root_phys; 2472 pmcs_check_expanders(pwp, root_phy); 2473 2474 /* 2475 * 2. Descend the tree looking for dead devices and kill them 2476 * by aborting all active commands and then deregistering them. 2477 */ 2478 if (pmcs_kill_devices(pwp, root_phy)) { 2479 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2480 "%s: pmcs_kill_devices failed!", __func__); 2481 } 2482 2483 /* 2484 * 3. Check for dead expanders and remove their children from the tree. 2485 * By the time we get here, the devices and commands for them have 2486 * already been terminated and removed. 2487 * 2488 * We do this independent of the configuration count changing so we can 2489 * free any dead device PHYs that were discovered while checking 2490 * expanders. We ignore any subsidiary phys as pmcs_clear_expander 2491 * will take care of those. 2492 * 2493 * NOTE: pmcs_clear_expander requires softstate lock 2494 */ 2495 mutex_enter(&pwp->lock); 2496 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 2497 /* 2498 * Call pmcs_clear_expander for every root PHY. It will 2499 * recurse and determine which (if any) expanders actually 2500 * need to be cleared. 2501 */ 2502 pmcs_lock_phy(pptr); 2503 pmcs_clear_expander(pwp, pptr, 0); 2504 pmcs_unlock_phy(pptr); 2505 } 2506 mutex_exit(&pwp->lock); 2507 2508 /* 2509 * 4. Check for dead devices and nullify them. By the time we get here, 2510 * the devices and commands for them have already been terminated 2511 * and removed. This is different from step 2 in that this just nulls 2512 * phys that are part of expanders that are still here but used to 2513 * be something but are no longer something (e.g., after a pulled 2514 * disk drive). Note that dead expanders had their contained phys 2515 * removed from the tree- here, the expanders themselves are 2516 * nullified (unless they were removed by being contained in another 2517 * expander phy). 2518 */ 2519 pmcs_clear_phys(pwp, root_phy); 2520 2521 /* 2522 * 5. Now check for and configure new devices. 2523 */ 2524 if (pmcs_configure_new_devices(pwp, root_phy)) { 2525 goto restart; 2526 } 2527 2528 out: 2529 DTRACE_PROBE2(pmcs__discover__exit, ulong_t, pwp->work_flags, 2530 boolean_t, pwp->config_changed); 2531 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "Discovery end"); 2532 2533 mutex_enter(&pwp->config_lock); 2534 2535 if (pwp->config_changed == B_FALSE) { 2536 /* 2537 * Observation is stable, report what we currently see to 2538 * the tgtmaps for delta processing. Start by setting 2539 * BEGIN on all tgtmaps. 2540 */ 2541 mutex_exit(&pwp->config_lock); 2542 if (pmcs_report_observations(pwp) == B_FALSE) { 2543 goto restart; 2544 } 2545 mutex_enter(&pwp->config_lock); 2546 } else { 2547 /* 2548 * If config_changed is TRUE, we need to reschedule 2549 * discovery now. 2550 */ 2551 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2552 "%s: Config has changed, will re-run discovery", __func__); 2553 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 2554 } 2555 2556 pmcs_release_scratch(pwp); 2557 if (!pwp->quiesced) { 2558 pwp->blocked = 0; 2559 } 2560 pwp->configuring = 0; 2561 mutex_exit(&pwp->config_lock); 2562 2563 #ifdef DEBUG 2564 pptr = pmcs_find_phy_needing_work(pwp, pwp->root_phys); 2565 if (pptr != NULL) { 2566 if (!WORK_IS_SCHEDULED(pwp, PMCS_WORK_DISCOVER)) { 2567 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 2568 "PHY %s dead=%d changed=%d configured=%d " 2569 "but no work scheduled", pptr->path, pptr->dead, 2570 pptr->changed, pptr->configured); 2571 } 2572 pmcs_unlock_phy(pptr); 2573 } 2574 #endif 2575 2576 return; 2577 2578 restart: 2579 /* Clean up and restart discovery */ 2580 pmcs_release_scratch(pwp); 2581 mutex_enter(&pwp->config_lock); 2582 pwp->configuring = 0; 2583 RESTART_DISCOVERY_LOCKED(pwp); 2584 mutex_exit(&pwp->config_lock); 2585 } 2586 2587 /* 2588 * Return any PHY that needs to have scheduled work done. The PHY is returned 2589 * locked. 2590 */ 2591 static pmcs_phy_t * 2592 pmcs_find_phy_needing_work(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 2593 { 2594 pmcs_phy_t *cphyp, *pnext; 2595 2596 while (pptr) { 2597 pmcs_lock_phy(pptr); 2598 2599 if (pptr->changed || (pptr->dead && pptr->valid_device_id)) { 2600 return (pptr); 2601 } 2602 2603 pnext = pptr->sibling; 2604 2605 if (pptr->children) { 2606 cphyp = pptr->children; 2607 pmcs_unlock_phy(pptr); 2608 cphyp = pmcs_find_phy_needing_work(pwp, cphyp); 2609 if (cphyp) { 2610 return (cphyp); 2611 } 2612 } else { 2613 pmcs_unlock_phy(pptr); 2614 } 2615 2616 pptr = pnext; 2617 } 2618 2619 return (NULL); 2620 } 2621 2622 /* 2623 * We may (or may not) report observations to SCSA. This is prefaced by 2624 * issuing a set_begin for each iport target map. 2625 */ 2626 static void 2627 pmcs_begin_observations(pmcs_hw_t *pwp) 2628 { 2629 pmcs_iport_t *iport; 2630 scsi_hba_tgtmap_t *tgtmap; 2631 2632 rw_enter(&pwp->iports_lock, RW_READER); 2633 for (iport = list_head(&pwp->iports); iport != NULL; 2634 iport = list_next(&pwp->iports, iport)) { 2635 /* 2636 * Unless we have at least one phy up, skip this iport. 2637 * Note we don't need to lock the iport for report_skip 2638 * since it is only used here. We are doing the skip so that 2639 * the phymap and iportmap stabilization times are honored - 2640 * giving us the ability to recover port operation within the 2641 * stabilization time without unconfiguring targets using the 2642 * port. 2643 */ 2644 if (!sas_phymap_uahasphys(pwp->hss_phymap, iport->ua)) { 2645 iport->report_skip = 1; 2646 continue; /* skip set_begin */ 2647 } 2648 iport->report_skip = 0; 2649 2650 tgtmap = iport->iss_tgtmap; 2651 ASSERT(tgtmap); 2652 if (scsi_hba_tgtmap_set_begin(tgtmap) != DDI_SUCCESS) { 2653 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2654 "%s: cannot set_begin tgtmap ", __func__); 2655 rw_exit(&pwp->iports_lock); 2656 return; 2657 } 2658 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2659 "%s: set begin on tgtmap [0x%p]", __func__, (void *)tgtmap); 2660 } 2661 rw_exit(&pwp->iports_lock); 2662 } 2663 2664 /* 2665 * Report current observations to SCSA. 2666 */ 2667 static boolean_t 2668 pmcs_report_observations(pmcs_hw_t *pwp) 2669 { 2670 pmcs_iport_t *iport; 2671 scsi_hba_tgtmap_t *tgtmap; 2672 char *ap; 2673 pmcs_phy_t *pptr; 2674 uint64_t wwn; 2675 2676 /* 2677 * Observation is stable, report what we currently see to the tgtmaps 2678 * for delta processing. 2679 */ 2680 pptr = pwp->root_phys; 2681 2682 while (pptr) { 2683 pmcs_lock_phy(pptr); 2684 2685 /* 2686 * Skip PHYs that have nothing attached or are dead. 2687 */ 2688 if ((pptr->dtype == NOTHING) || pptr->dead) { 2689 pmcs_unlock_phy(pptr); 2690 pptr = pptr->sibling; 2691 continue; 2692 } 2693 2694 if (pptr->changed) { 2695 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 2696 "%s: oops, PHY %s changed; restart discovery", 2697 __func__, pptr->path); 2698 pmcs_unlock_phy(pptr); 2699 return (B_FALSE); 2700 } 2701 2702 /* 2703 * Get the iport for this root PHY, then call the helper 2704 * to report observations for this iport's targets 2705 */ 2706 wwn = pmcs_barray2wwn(pptr->sas_address); 2707 pmcs_unlock_phy(pptr); 2708 iport = pmcs_get_iport_by_wwn(pwp, wwn); 2709 if (iport == NULL) { 2710 /* No iport for this tgt */ 2711 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2712 "%s: no iport for this target", __func__); 2713 pptr = pptr->sibling; 2714 continue; 2715 } 2716 2717 pmcs_lock_phy(pptr); 2718 if (!iport->report_skip) { 2719 if (pmcs_report_iport_observations( 2720 pwp, iport, pptr) == B_FALSE) { 2721 pmcs_rele_iport(iport); 2722 pmcs_unlock_phy(pptr); 2723 return (B_FALSE); 2724 } 2725 } 2726 pmcs_rele_iport(iport); 2727 pmcs_unlock_phy(pptr); 2728 pptr = pptr->sibling; 2729 } 2730 2731 /* 2732 * The observation is complete, end sets. Note we will skip any 2733 * iports that are active, but have no PHYs in them (i.e. awaiting 2734 * unconfigure). Set to restart discovery if we find this. 2735 */ 2736 rw_enter(&pwp->iports_lock, RW_READER); 2737 for (iport = list_head(&pwp->iports); 2738 iport != NULL; 2739 iport = list_next(&pwp->iports, iport)) { 2740 2741 if (iport->report_skip) 2742 continue; /* skip set_end */ 2743 2744 tgtmap = iport->iss_tgtmap; 2745 ASSERT(tgtmap); 2746 if (scsi_hba_tgtmap_set_end(tgtmap, 0) != DDI_SUCCESS) { 2747 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2748 "%s: cannot set_end tgtmap ", __func__); 2749 rw_exit(&pwp->iports_lock); 2750 return (B_FALSE); 2751 } 2752 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2753 "%s: set end on tgtmap [0x%p]", __func__, (void *)tgtmap); 2754 } 2755 2756 /* 2757 * Now that discovery is complete, set up the necessary 2758 * DDI properties on each iport node. 2759 */ 2760 for (iport = list_head(&pwp->iports); iport != NULL; 2761 iport = list_next(&pwp->iports, iport)) { 2762 /* Set up the 'attached-port' property on the iport */ 2763 ap = kmem_zalloc(PMCS_MAX_UA_SIZE, KM_SLEEP); 2764 mutex_enter(&iport->lock); 2765 pptr = iport->pptr; 2766 mutex_exit(&iport->lock); 2767 if (pptr == NULL) { 2768 /* 2769 * This iport is down, but has not been 2770 * removed from our list (unconfigured). 2771 * Set our value to '0'. 2772 */ 2773 (void) snprintf(ap, 1, "%s", "0"); 2774 } else { 2775 /* Otherwise, set it to remote phy's wwn */ 2776 pmcs_lock_phy(pptr); 2777 wwn = pmcs_barray2wwn(pptr->sas_address); 2778 (void) scsi_wwn_to_wwnstr(wwn, 1, ap); 2779 pmcs_unlock_phy(pptr); 2780 } 2781 if (ndi_prop_update_string(DDI_DEV_T_NONE, iport->dip, 2782 SCSI_ADDR_PROP_ATTACHED_PORT, ap) != DDI_SUCCESS) { 2783 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "%s: Failed " 2784 "to set prop ("SCSI_ADDR_PROP_ATTACHED_PORT")", 2785 __func__); 2786 } 2787 kmem_free(ap, PMCS_MAX_UA_SIZE); 2788 } 2789 rw_exit(&pwp->iports_lock); 2790 2791 return (B_TRUE); 2792 } 2793 2794 /* 2795 * Report observations into a particular iport's target map 2796 * 2797 * Called with phyp (and all descendents) locked 2798 */ 2799 static boolean_t 2800 pmcs_report_iport_observations(pmcs_hw_t *pwp, pmcs_iport_t *iport, 2801 pmcs_phy_t *phyp) 2802 { 2803 pmcs_phy_t *lphyp; 2804 scsi_hba_tgtmap_t *tgtmap; 2805 scsi_tgtmap_tgt_type_t tgt_type; 2806 char *ua; 2807 uint64_t wwn; 2808 2809 tgtmap = iport->iss_tgtmap; 2810 ASSERT(tgtmap); 2811 2812 lphyp = phyp; 2813 while (lphyp) { 2814 switch (lphyp->dtype) { 2815 default: /* Skip unknown PHYs. */ 2816 /* for non-root phys, skip to sibling */ 2817 goto next_phy; 2818 2819 case SATA: 2820 case SAS: 2821 tgt_type = SCSI_TGT_SCSI_DEVICE; 2822 break; 2823 2824 case EXPANDER: 2825 tgt_type = SCSI_TGT_SMP_DEVICE; 2826 break; 2827 } 2828 2829 if (lphyp->dead || !lphyp->configured) { 2830 goto next_phy; 2831 } 2832 2833 wwn = pmcs_barray2wwn(lphyp->sas_address); 2834 ua = scsi_wwn_to_wwnstr(wwn, 1, NULL); 2835 2836 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, lphyp, NULL, 2837 "iport_observation: adding %s on tgtmap [0x%p] phy [0x%p]", 2838 ua, (void *)tgtmap, (void*)lphyp); 2839 2840 if (scsi_hba_tgtmap_set_add(tgtmap, tgt_type, ua, NULL) != 2841 DDI_SUCCESS) { 2842 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2843 "%s: failed to add address %s", __func__, ua); 2844 scsi_free_wwnstr(ua); 2845 return (B_FALSE); 2846 } 2847 scsi_free_wwnstr(ua); 2848 2849 if (lphyp->children) { 2850 if (pmcs_report_iport_observations(pwp, iport, 2851 lphyp->children) == B_FALSE) { 2852 return (B_FALSE); 2853 } 2854 } 2855 2856 /* for non-root phys, report siblings too */ 2857 next_phy: 2858 if (IS_ROOT_PHY(lphyp)) { 2859 lphyp = NULL; 2860 } else { 2861 lphyp = lphyp->sibling; 2862 } 2863 } 2864 2865 return (B_TRUE); 2866 } 2867 2868 /* 2869 * Check for and configure new devices. 2870 * 2871 * If the changed device is a SATA device, add a SATA device. 2872 * 2873 * If the changed device is a SAS device, add a SAS device. 2874 * 2875 * If the changed device is an EXPANDER device, do a REPORT 2876 * GENERAL SMP command to find out the number of contained phys. 2877 * 2878 * For each number of contained phys, allocate a phy, do a 2879 * DISCOVERY SMP command to find out what kind of device it 2880 * is and add it to the linked list of phys on the *next* level. 2881 * 2882 * NOTE: pptr passed in by the caller will be a root PHY 2883 */ 2884 static int 2885 pmcs_configure_new_devices(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 2886 { 2887 int rval = 0; 2888 pmcs_iport_t *iport; 2889 pmcs_phy_t *pnext, *orig_pptr = pptr, *root_phy, *pchild; 2890 uint64_t wwn; 2891 2892 /* 2893 * First, walk through each PHY at this level 2894 */ 2895 while (pptr) { 2896 pmcs_lock_phy(pptr); 2897 pnext = pptr->sibling; 2898 2899 /* 2900 * Set the new dtype if it has changed 2901 */ 2902 if ((pptr->pend_dtype != NEW) && 2903 (pptr->pend_dtype != pptr->dtype)) { 2904 pptr->dtype = pptr->pend_dtype; 2905 } 2906 2907 if (pptr->changed == 0 || pptr->dead || pptr->configured) { 2908 goto next_phy; 2909 } 2910 2911 /* 2912 * Confirm that this target's iport is configured 2913 */ 2914 root_phy = pmcs_get_root_phy(pptr); 2915 wwn = pmcs_barray2wwn(root_phy->sas_address); 2916 pmcs_unlock_phy(pptr); 2917 iport = pmcs_get_iport_by_wwn(pwp, wwn); 2918 if (iport == NULL) { 2919 /* No iport for this tgt, restart */ 2920 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2921 "%s: iport not yet configured, " 2922 "retry discovery", __func__); 2923 pnext = NULL; 2924 rval = -1; 2925 pmcs_lock_phy(pptr); 2926 goto next_phy; 2927 } 2928 2929 pmcs_lock_phy(pptr); 2930 switch (pptr->dtype) { 2931 case NOTHING: 2932 pptr->changed = 0; 2933 break; 2934 case SATA: 2935 case SAS: 2936 pptr->iport = iport; 2937 pmcs_new_tport(pwp, pptr); 2938 break; 2939 case EXPANDER: 2940 pmcs_configure_expander(pwp, pptr, iport); 2941 break; 2942 } 2943 pmcs_rele_iport(iport); 2944 2945 mutex_enter(&pwp->config_lock); 2946 if (pwp->config_changed) { 2947 mutex_exit(&pwp->config_lock); 2948 pnext = NULL; 2949 goto next_phy; 2950 } 2951 mutex_exit(&pwp->config_lock); 2952 2953 next_phy: 2954 pmcs_unlock_phy(pptr); 2955 pptr = pnext; 2956 } 2957 2958 if (rval != 0) { 2959 return (rval); 2960 } 2961 2962 /* 2963 * Now walk through each PHY again, recalling ourselves if they 2964 * have children 2965 */ 2966 pptr = orig_pptr; 2967 while (pptr) { 2968 pmcs_lock_phy(pptr); 2969 pnext = pptr->sibling; 2970 pchild = pptr->children; 2971 pmcs_unlock_phy(pptr); 2972 2973 if (pchild) { 2974 rval = pmcs_configure_new_devices(pwp, pchild); 2975 if (rval != 0) { 2976 break; 2977 } 2978 } 2979 2980 pptr = pnext; 2981 } 2982 2983 return (rval); 2984 } 2985 2986 /* 2987 * Set all phys and descendent phys as changed if changed == B_TRUE, otherwise 2988 * mark them all as not changed. 2989 * 2990 * Called with parent PHY locked. 2991 */ 2992 void 2993 pmcs_set_changed(pmcs_hw_t *pwp, pmcs_phy_t *parent, boolean_t changed, 2994 int level) 2995 { 2996 pmcs_phy_t *pptr; 2997 2998 if (level == 0) { 2999 if (changed) { 3000 PHY_CHANGED(pwp, parent); 3001 } else { 3002 parent->changed = 0; 3003 } 3004 if (parent->dtype == EXPANDER && parent->level) { 3005 parent->width = 1; 3006 } 3007 if (parent->children) { 3008 pmcs_set_changed(pwp, parent->children, changed, 3009 level + 1); 3010 } 3011 } else { 3012 pptr = parent; 3013 while (pptr) { 3014 if (changed) { 3015 PHY_CHANGED(pwp, pptr); 3016 } else { 3017 pptr->changed = 0; 3018 } 3019 if (pptr->dtype == EXPANDER && pptr->level) { 3020 pptr->width = 1; 3021 } 3022 if (pptr->children) { 3023 pmcs_set_changed(pwp, pptr->children, changed, 3024 level + 1); 3025 } 3026 pptr = pptr->sibling; 3027 } 3028 } 3029 } 3030 3031 /* 3032 * Take the passed phy mark it and its descendants as dead. 3033 * Fire up reconfiguration to abort commands and bury it. 3034 * 3035 * Called with the parent PHY locked. 3036 */ 3037 void 3038 pmcs_kill_changed(pmcs_hw_t *pwp, pmcs_phy_t *parent, int level) 3039 { 3040 pmcs_phy_t *pptr = parent; 3041 3042 while (pptr) { 3043 pptr->link_rate = 0; 3044 pptr->abort_sent = 0; 3045 pptr->abort_pending = 1; 3046 SCHEDULE_WORK(pwp, PMCS_WORK_ABORT_HANDLE); 3047 pptr->need_rl_ext = 0; 3048 3049 if (pptr->dead == 0) { 3050 PHY_CHANGED(pwp, pptr); 3051 RESTART_DISCOVERY(pwp); 3052 } 3053 3054 pptr->dead = 1; 3055 3056 if (pptr->children) { 3057 pmcs_kill_changed(pwp, pptr->children, level + 1); 3058 } 3059 3060 /* 3061 * Only kill siblings at level > 0 3062 */ 3063 if (level == 0) { 3064 return; 3065 } 3066 3067 pptr = pptr->sibling; 3068 } 3069 } 3070 3071 /* 3072 * Go through every PHY and clear any that are dead (unless they're expanders) 3073 */ 3074 static void 3075 pmcs_clear_phys(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3076 { 3077 pmcs_phy_t *pnext, *phyp; 3078 3079 phyp = pptr; 3080 while (phyp) { 3081 if (IS_ROOT_PHY(phyp)) { 3082 pmcs_lock_phy(phyp); 3083 } 3084 3085 if ((phyp->dtype != EXPANDER) && phyp->dead) { 3086 pmcs_clear_phy(pwp, phyp); 3087 } 3088 3089 if (phyp->children) { 3090 pmcs_clear_phys(pwp, phyp->children); 3091 } 3092 3093 pnext = phyp->sibling; 3094 3095 if (IS_ROOT_PHY(phyp)) { 3096 pmcs_unlock_phy(phyp); 3097 } 3098 3099 phyp = pnext; 3100 } 3101 } 3102 3103 /* 3104 * Clear volatile parts of a phy. Called with PHY locked. 3105 */ 3106 void 3107 pmcs_clear_phy(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3108 { 3109 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "%s: %s", 3110 __func__, pptr->path); 3111 ASSERT(mutex_owned(&pptr->phy_lock)); 3112 /* keep sibling */ 3113 /* keep children */ 3114 /* keep parent */ 3115 pptr->device_id = PMCS_INVALID_DEVICE_ID; 3116 /* keep hw_event_ack */ 3117 pptr->ncphy = 0; 3118 /* keep phynum */ 3119 pptr->width = 0; 3120 pptr->ds_recovery_retries = 0; 3121 pptr->ds_prev_good_recoveries = 0; 3122 pptr->last_good_recovery = 0; 3123 pptr->prev_recovery = 0; 3124 3125 /* keep dtype */ 3126 pptr->config_stop = 0; 3127 pptr->spinup_hold = 0; 3128 pptr->atdt = 0; 3129 /* keep portid */ 3130 pptr->link_rate = 0; 3131 pptr->valid_device_id = 0; 3132 pptr->abort_sent = 0; 3133 pptr->abort_pending = 0; 3134 pptr->need_rl_ext = 0; 3135 pptr->subsidiary = 0; 3136 pptr->configured = 0; 3137 pptr->deregister_wait = 0; 3138 pptr->reenumerate = 0; 3139 /* Only mark dead if it's not a root PHY and its dtype isn't NOTHING */ 3140 /* XXX: What about directly attached disks? */ 3141 if (!IS_ROOT_PHY(pptr) && (pptr->dtype != NOTHING)) 3142 pptr->dead = 1; 3143 pptr->changed = 0; 3144 /* keep SAS address */ 3145 /* keep path */ 3146 /* keep ref_count */ 3147 /* Don't clear iport on root PHYs - they are handled in pmcs_intr.c */ 3148 if (!IS_ROOT_PHY(pptr)) { 3149 pptr->last_iport = pptr->iport; 3150 pptr->iport = NULL; 3151 } 3152 /* keep target */ 3153 } 3154 3155 /* 3156 * Allocate softstate for this target if there isn't already one. If there 3157 * is, just redo our internal configuration. If it is actually "new", we'll 3158 * soon get a tran_tgt_init for it. 3159 * 3160 * Called with PHY locked. 3161 */ 3162 static void 3163 pmcs_new_tport(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3164 { 3165 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "%s: phy 0x%p @ %s", 3166 __func__, (void *)pptr, pptr->path); 3167 3168 if (pmcs_configure_phy(pwp, pptr) == B_FALSE) { 3169 /* 3170 * If the config failed, mark the PHY as changed. 3171 */ 3172 PHY_CHANGED(pwp, pptr); 3173 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3174 "%s: pmcs_configure_phy failed for phy 0x%p", __func__, 3175 (void *)pptr); 3176 return; 3177 } 3178 3179 /* Mark PHY as no longer changed */ 3180 pptr->changed = 0; 3181 3182 /* 3183 * If the PHY has no target pointer: 3184 * 3185 * If it's a root PHY, see if another PHY in the iport holds the 3186 * target pointer (primary PHY changed). If so, move it over. 3187 * 3188 * If it's not a root PHY, see if there's a PHY on the dead_phys 3189 * list that matches. 3190 */ 3191 if (pptr->target == NULL) { 3192 if (IS_ROOT_PHY(pptr)) { 3193 pmcs_phy_t *rphy = pwp->root_phys; 3194 3195 while (rphy) { 3196 if (rphy == pptr) { 3197 rphy = rphy->sibling; 3198 continue; 3199 } 3200 3201 mutex_enter(&rphy->phy_lock); 3202 if ((rphy->iport == pptr->iport) && 3203 (rphy->target != NULL)) { 3204 mutex_enter(&rphy->target->statlock); 3205 pptr->target = rphy->target; 3206 rphy->target = NULL; 3207 pptr->target->phy = pptr; 3208 /* The target is now on pptr */ 3209 mutex_exit(&pptr->target->statlock); 3210 mutex_exit(&rphy->phy_lock); 3211 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, 3212 pptr, pptr->target, 3213 "%s: Moved target from %s to %s", 3214 __func__, rphy->path, pptr->path); 3215 break; 3216 } 3217 mutex_exit(&rphy->phy_lock); 3218 3219 rphy = rphy->sibling; 3220 } 3221 } else { 3222 pmcs_reap_dead_phy(pptr); 3223 } 3224 } 3225 3226 /* 3227 * Only assign the device if there is a target for this PHY with a 3228 * matching SAS address. If an iport is disconnected from one piece 3229 * of storage and connected to another within the iport stabilization 3230 * time, we can get the PHY/target mismatch situation. 3231 * 3232 * Otherwise, it'll get done in tran_tgt_init. 3233 */ 3234 if (pptr->target) { 3235 mutex_enter(&pptr->target->statlock); 3236 if (pmcs_phy_target_match(pptr) == B_FALSE) { 3237 mutex_exit(&pptr->target->statlock); 3238 if (!IS_ROOT_PHY(pptr)) { 3239 pmcs_dec_phy_ref_count(pptr); 3240 } 3241 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 3242 "%s: Not assigning existing tgt %p for PHY %p " 3243 "(WWN mismatch)", __func__, (void *)pptr->target, 3244 (void *)pptr); 3245 pptr->target = NULL; 3246 return; 3247 } 3248 3249 if (!pmcs_assign_device(pwp, pptr->target)) { 3250 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, pptr->target, 3251 "%s: pmcs_assign_device failed for target 0x%p", 3252 __func__, (void *)pptr->target); 3253 } 3254 mutex_exit(&pptr->target->statlock); 3255 } 3256 } 3257 3258 /* 3259 * Called with PHY lock held. 3260 */ 3261 static boolean_t 3262 pmcs_configure_phy(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3263 { 3264 char *dtype; 3265 3266 ASSERT(mutex_owned(&pptr->phy_lock)); 3267 3268 /* 3269 * Mark this device as no longer changed. 3270 */ 3271 pptr->changed = 0; 3272 3273 /* 3274 * If we don't have a device handle, get one. 3275 */ 3276 if (pmcs_get_device_handle(pwp, pptr)) { 3277 return (B_FALSE); 3278 } 3279 3280 pptr->configured = 1; 3281 3282 switch (pptr->dtype) { 3283 case SAS: 3284 dtype = "SAS"; 3285 break; 3286 case SATA: 3287 dtype = "SATA"; 3288 break; 3289 case EXPANDER: 3290 dtype = "SMP"; 3291 break; 3292 default: 3293 dtype = "???"; 3294 } 3295 3296 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "config_dev: %s " 3297 "dev %s " SAS_ADDR_FMT " dev id 0x%x lr 0x%x", dtype, pptr->path, 3298 SAS_ADDR_PRT(pptr->sas_address), pptr->device_id, pptr->link_rate); 3299 3300 return (B_TRUE); 3301 } 3302 3303 /* 3304 * Called with PHY locked 3305 */ 3306 static void 3307 pmcs_configure_expander(pmcs_hw_t *pwp, pmcs_phy_t *pptr, pmcs_iport_t *iport) 3308 { 3309 pmcs_phy_t *ctmp, *clist = NULL, *cnext; 3310 int result, i, nphy = 0; 3311 boolean_t root_phy = B_FALSE; 3312 3313 ASSERT(iport); 3314 3315 /* 3316 * Step 1- clear our "changed" bit. If we need to retry/restart due 3317 * to resource shortages, we'll set it again. While we're doing 3318 * configuration, other events may set it again as well. If the PHY 3319 * is a root PHY and is currently marked as having changed, reset the 3320 * config_stop timer as well. 3321 */ 3322 if (IS_ROOT_PHY(pptr) && pptr->changed) { 3323 pptr->config_stop = ddi_get_lbolt() + 3324 drv_usectohz(PMCS_MAX_CONFIG_TIME); 3325 } 3326 pptr->changed = 0; 3327 3328 /* 3329 * Step 2- make sure we don't overflow 3330 */ 3331 if (pptr->level == PMCS_MAX_XPND-1) { 3332 pmcs_prt(pwp, PMCS_PRT_WARN, pptr, NULL, 3333 "%s: SAS expansion tree too deep", __func__); 3334 return; 3335 } 3336 3337 /* 3338 * Step 3- Check if this expander is part of a wide phy that has 3339 * already been configured. 3340 * 3341 * This is known by checking this level for another EXPANDER device 3342 * with the same SAS address and isn't already marked as a subsidiary 3343 * phy and a parent whose SAS address is the same as our SAS address 3344 * (if there are parents). 3345 */ 3346 if (!IS_ROOT_PHY(pptr)) { 3347 /* 3348 * No need to lock the parent here because we're in discovery 3349 * and the only time a PHY's children pointer can change is 3350 * in discovery; either in pmcs_clear_expander (which has 3351 * already been called) or here, down below. Plus, trying to 3352 * grab the parent's lock here can cause deadlock. 3353 */ 3354 ctmp = pptr->parent->children; 3355 } else { 3356 ctmp = pwp->root_phys; 3357 root_phy = B_TRUE; 3358 } 3359 3360 while (ctmp) { 3361 /* 3362 * If we've checked all PHYs up to pptr, we stop. Otherwise, 3363 * we'll be checking for a primary PHY with a higher PHY 3364 * number than pptr, which will never happen. The primary 3365 * PHY on non-root expanders will ALWAYS be the lowest 3366 * numbered PHY. 3367 */ 3368 if (ctmp == pptr) { 3369 break; 3370 } 3371 3372 /* 3373 * If pptr and ctmp are root PHYs, just grab the mutex on 3374 * ctmp. No need to lock the entire tree. If they are not 3375 * root PHYs, there is no need to lock since a non-root PHY's 3376 * SAS address and other characteristics can only change in 3377 * discovery anyway. 3378 */ 3379 if (root_phy) { 3380 mutex_enter(&ctmp->phy_lock); 3381 } 3382 3383 if (ctmp->dtype == EXPANDER && ctmp->width && 3384 memcmp(ctmp->sas_address, pptr->sas_address, 8) == 0) { 3385 int widephy = 0; 3386 /* 3387 * If these phys are not root PHYs, compare their SAS 3388 * addresses too. 3389 */ 3390 if (!root_phy) { 3391 if (memcmp(ctmp->parent->sas_address, 3392 pptr->parent->sas_address, 8) == 0) { 3393 widephy = 1; 3394 } 3395 } else { 3396 widephy = 1; 3397 } 3398 if (widephy) { 3399 ctmp->width++; 3400 pptr->subsidiary = 1; 3401 3402 /* 3403 * Update the primary PHY's attached-port-pm 3404 * and target-port-pm information with the info 3405 * from this subsidiary 3406 */ 3407 pmcs_update_phy_pm_props(ctmp, 3408 pptr->att_port_pm_tmp, 3409 pptr->tgt_port_pm_tmp, B_TRUE); 3410 3411 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3412 "%s: PHY %s part of wide PHY %s " 3413 "(now %d wide)", __func__, pptr->path, 3414 ctmp->path, ctmp->width); 3415 if (root_phy) { 3416 mutex_exit(&ctmp->phy_lock); 3417 } 3418 return; 3419 } 3420 } 3421 3422 cnext = ctmp->sibling; 3423 if (root_phy) { 3424 mutex_exit(&ctmp->phy_lock); 3425 } 3426 ctmp = cnext; 3427 } 3428 3429 /* 3430 * Step 4- If we don't have a device handle, get one. Since this 3431 * is the primary PHY, make sure subsidiary is cleared. 3432 */ 3433 pptr->subsidiary = 0; 3434 pptr->iport = iport; 3435 if (pmcs_get_device_handle(pwp, pptr)) { 3436 goto out; 3437 } 3438 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "Config expander %s " 3439 SAS_ADDR_FMT " dev id 0x%x lr 0x%x", pptr->path, 3440 SAS_ADDR_PRT(pptr->sas_address), pptr->device_id, pptr->link_rate); 3441 3442 /* 3443 * Step 5- figure out how many phys are in this expander. 3444 */ 3445 nphy = pmcs_expander_get_nphy(pwp, pptr); 3446 if (nphy <= 0) { 3447 if (nphy == 0 && ddi_get_lbolt() < pptr->config_stop) { 3448 PHY_CHANGED(pwp, pptr); 3449 RESTART_DISCOVERY(pwp); 3450 } else { 3451 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3452 "%s: Retries exhausted for %s, killing", __func__, 3453 pptr->path); 3454 pptr->config_stop = 0; 3455 pmcs_kill_changed(pwp, pptr, 0); 3456 } 3457 goto out; 3458 } 3459 3460 /* 3461 * Step 6- Allocate a list of phys for this expander and figure out 3462 * what each one is. 3463 */ 3464 for (i = 0; i < nphy; i++) { 3465 ctmp = kmem_cache_alloc(pwp->phy_cache, KM_SLEEP); 3466 bzero(ctmp, sizeof (pmcs_phy_t)); 3467 ctmp->device_id = PMCS_INVALID_DEVICE_ID; 3468 ctmp->sibling = clist; 3469 ctmp->pend_dtype = NEW; /* Init pending dtype */ 3470 ctmp->config_stop = ddi_get_lbolt() + 3471 drv_usectohz(PMCS_MAX_CONFIG_TIME); 3472 clist = ctmp; 3473 } 3474 3475 mutex_enter(&pwp->config_lock); 3476 if (pwp->config_changed) { 3477 RESTART_DISCOVERY_LOCKED(pwp); 3478 mutex_exit(&pwp->config_lock); 3479 /* 3480 * Clean up the newly allocated PHYs and return 3481 */ 3482 while (clist) { 3483 ctmp = clist->sibling; 3484 kmem_cache_free(pwp->phy_cache, clist); 3485 clist = ctmp; 3486 } 3487 return; 3488 } 3489 mutex_exit(&pwp->config_lock); 3490 3491 /* 3492 * Step 7- Now fill in the rest of the static portions of the phy. 3493 */ 3494 for (i = 0, ctmp = clist; ctmp; ctmp = ctmp->sibling, i++) { 3495 ctmp->parent = pptr; 3496 ctmp->pwp = pwp; 3497 ctmp->level = pptr->level+1; 3498 ctmp->portid = pptr->portid; 3499 if (ctmp->tolerates_sas2) { 3500 ASSERT(i < SAS2_PHYNUM_MAX); 3501 ctmp->phynum = i & SAS2_PHYNUM_MASK; 3502 } else { 3503 ASSERT(i < SAS_PHYNUM_MAX); 3504 ctmp->phynum = i & SAS_PHYNUM_MASK; 3505 } 3506 pmcs_phy_name(pwp, ctmp, ctmp->path, sizeof (ctmp->path)); 3507 pmcs_lock_phy(ctmp); 3508 } 3509 3510 /* 3511 * Step 8- Discover things about each phy in the expander. 3512 */ 3513 for (i = 0, ctmp = clist; ctmp; ctmp = ctmp->sibling, i++) { 3514 result = pmcs_expander_content_discover(pwp, pptr, ctmp); 3515 if (result <= 0) { 3516 if (ddi_get_lbolt() < pptr->config_stop) { 3517 PHY_CHANGED(pwp, pptr); 3518 RESTART_DISCOVERY(pwp); 3519 } else { 3520 pptr->config_stop = 0; 3521 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3522 "%s: Retries exhausted for %s, killing", 3523 __func__, pptr->path); 3524 pmcs_kill_changed(pwp, pptr, 0); 3525 } 3526 goto out; 3527 } 3528 3529 /* Set pend_dtype to dtype for 1st time initialization */ 3530 ctmp->pend_dtype = ctmp->dtype; 3531 } 3532 3533 /* 3534 * Step 9: Install the new list on the next level. There should 3535 * typically be no children pointer on this PHY. There is one known 3536 * case where this can happen, though. If a root PHY goes down and 3537 * comes back up before discovery can run, we will fail to remove the 3538 * children from that PHY since it will no longer be marked dead. 3539 * However, in this case, all children should also be marked dead. If 3540 * we see that, take those children and put them on the dead_phys list. 3541 */ 3542 if (pptr->children != NULL) { 3543 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 3544 "%s: Expander @ %s still has children: Clean up", 3545 __func__, pptr->path); 3546 pmcs_add_dead_phys(pwp, pptr->children); 3547 } 3548 3549 /* 3550 * Set the new children pointer for this expander 3551 */ 3552 pptr->children = clist; 3553 clist = NULL; 3554 pptr->ncphy = nphy; 3555 pptr->configured = 1; 3556 3557 /* 3558 * We only set width if we're greater than level 0. 3559 */ 3560 if (pptr->level) { 3561 pptr->width = 1; 3562 } 3563 3564 /* 3565 * Now tell the rest of the world about us, as an SMP node. 3566 */ 3567 pptr->iport = iport; 3568 pmcs_new_tport(pwp, pptr); 3569 3570 out: 3571 while (clist) { 3572 ctmp = clist->sibling; 3573 pmcs_unlock_phy(clist); 3574 kmem_cache_free(pwp->phy_cache, clist); 3575 clist = ctmp; 3576 } 3577 } 3578 3579 /* 3580 * 2. Check expanders marked changed (but not dead) to see if they still have 3581 * the same number of phys and the same SAS address. Mark them, their subsidiary 3582 * phys (if wide) and their descendents dead if anything has changed. Check the 3583 * the devices they contain to see if *they* have changed. If they've changed 3584 * from type NOTHING we leave them marked changed to be configured later 3585 * (picking up a new SAS address and link rate if possible). Otherwise, any 3586 * change in type, SAS address or removal of target role will cause us to 3587 * mark them (and their descendents) as dead and cause any pending commands 3588 * and associated devices to be removed. 3589 * 3590 * Called with PHY (pptr) locked. 3591 */ 3592 3593 static void 3594 pmcs_check_expander(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3595 { 3596 int nphy, result; 3597 pmcs_phy_t *ctmp, *local, *local_list = NULL, *local_tail = NULL; 3598 boolean_t kill_changed, changed; 3599 3600 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3601 "%s: check %s", __func__, pptr->path); 3602 3603 /* 3604 * Step 1: Mark phy as not changed. We will mark it changed if we need 3605 * to retry. 3606 */ 3607 pptr->changed = 0; 3608 3609 /* 3610 * Reset the config_stop time. Although we're not actually configuring 3611 * anything here, we do want some indication of when to give up trying 3612 * if we can't communicate with the expander. 3613 */ 3614 pptr->config_stop = ddi_get_lbolt() + 3615 drv_usectohz(PMCS_MAX_CONFIG_TIME); 3616 3617 /* 3618 * Step 2: Figure out how many phys are in this expander. If 3619 * pmcs_expander_get_nphy returns 0 we ran out of resources, 3620 * so reschedule and try later. If it returns another error, 3621 * just return. 3622 */ 3623 nphy = pmcs_expander_get_nphy(pwp, pptr); 3624 if (nphy <= 0) { 3625 if ((nphy == 0) && (ddi_get_lbolt() < pptr->config_stop)) { 3626 PHY_CHANGED(pwp, pptr); 3627 RESTART_DISCOVERY(pwp); 3628 } else { 3629 pptr->config_stop = 0; 3630 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3631 "%s: Retries exhausted for %s, killing", __func__, 3632 pptr->path); 3633 pmcs_kill_changed(pwp, pptr, 0); 3634 } 3635 return; 3636 } 3637 3638 /* 3639 * Step 3: If the number of phys don't agree, kill the old sub-tree. 3640 */ 3641 if (nphy != pptr->ncphy) { 3642 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3643 "%s: number of contained phys for %s changed from %d to %d", 3644 __func__, pptr->path, pptr->ncphy, nphy); 3645 /* 3646 * Force a rescan of this expander after dead contents 3647 * are cleared and removed. 3648 */ 3649 pmcs_kill_changed(pwp, pptr, 0); 3650 return; 3651 } 3652 3653 /* 3654 * Step 4: if we're at the bottom of the stack, we're done 3655 * (we can't have any levels below us) 3656 */ 3657 if (pptr->level == PMCS_MAX_XPND-1) { 3658 return; 3659 } 3660 3661 /* 3662 * Step 5: Discover things about each phy in this expander. We do 3663 * this by walking the current list of contained phys and doing a 3664 * content discovery for it to a local phy. 3665 */ 3666 ctmp = pptr->children; 3667 ASSERT(ctmp); 3668 if (ctmp == NULL) { 3669 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3670 "%s: No children attached to expander @ %s?", __func__, 3671 pptr->path); 3672 return; 3673 } 3674 3675 while (ctmp) { 3676 /* 3677 * Allocate a local PHY to contain the proposed new contents 3678 * and link it to the rest of the local PHYs so that they 3679 * can all be freed later. 3680 */ 3681 local = pmcs_clone_phy(ctmp); 3682 3683 if (local_list == NULL) { 3684 local_list = local; 3685 local_tail = local; 3686 } else { 3687 local_tail->sibling = local; 3688 local_tail = local; 3689 } 3690 3691 /* 3692 * Need to lock the local PHY since pmcs_expander_content_ 3693 * discovery may call pmcs_clear_phy on it, which expects 3694 * the PHY to be locked. 3695 */ 3696 pmcs_lock_phy(local); 3697 result = pmcs_expander_content_discover(pwp, pptr, local); 3698 pmcs_unlock_phy(local); 3699 if (result <= 0) { 3700 if (ddi_get_lbolt() < pptr->config_stop) { 3701 PHY_CHANGED(pwp, pptr); 3702 RESTART_DISCOVERY(pwp); 3703 } else { 3704 pptr->config_stop = 0; 3705 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3706 "%s: Retries exhausted for %s, killing", 3707 __func__, pptr->path); 3708 pmcs_kill_changed(pwp, pptr, 0); 3709 } 3710 3711 /* 3712 * Release all the local PHYs that we allocated. 3713 */ 3714 pmcs_free_phys(pwp, local_list); 3715 return; 3716 } 3717 3718 ctmp = ctmp->sibling; 3719 } 3720 3721 /* 3722 * Step 6: Compare the local PHY's contents to our current PHY. If 3723 * there are changes, take the appropriate action. 3724 * This is done in two steps (step 5 above, and 6 here) so that if we 3725 * have to bail during this process (e.g. pmcs_expander_content_discover 3726 * fails), we haven't actually changed the state of any of the real 3727 * PHYs. Next time we come through here, we'll be starting over from 3728 * scratch. This keeps us from marking a changed PHY as no longer 3729 * changed, but then having to bail only to come back next time and 3730 * think that the PHY hadn't changed. If this were to happen, we 3731 * would fail to properly configure the device behind this PHY. 3732 */ 3733 local = local_list; 3734 ctmp = pptr->children; 3735 3736 while (ctmp) { 3737 changed = B_FALSE; 3738 kill_changed = B_FALSE; 3739 3740 /* 3741 * We set local to local_list prior to this loop so that we 3742 * can simply walk the local_list while we walk this list. The 3743 * two lists should be completely in sync. 3744 * 3745 * Clear the changed flag here. 3746 */ 3747 ctmp->changed = 0; 3748 3749 if (ctmp->dtype != local->dtype) { 3750 if (ctmp->dtype != NOTHING) { 3751 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 3752 "%s: %s type changed from %s to %s " 3753 "(killing)", __func__, ctmp->path, 3754 PHY_TYPE(ctmp), PHY_TYPE(local)); 3755 /* 3756 * Force a rescan of this expander after dead 3757 * contents are cleared and removed. 3758 */ 3759 changed = B_TRUE; 3760 kill_changed = B_TRUE; 3761 } else { 3762 changed = B_TRUE; 3763 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 3764 "%s: %s type changed from NOTHING to %s", 3765 __func__, ctmp->path, PHY_TYPE(local)); 3766 /* 3767 * Since this PHY was nothing and is now 3768 * something, reset the config_stop timer. 3769 */ 3770 ctmp->config_stop = ddi_get_lbolt() + 3771 drv_usectohz(PMCS_MAX_CONFIG_TIME); 3772 } 3773 3774 } else if (ctmp->atdt != local->atdt) { 3775 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, "%s: " 3776 "%s attached device type changed from %d to %d " 3777 "(killing)", __func__, ctmp->path, ctmp->atdt, 3778 local->atdt); 3779 /* 3780 * Force a rescan of this expander after dead 3781 * contents are cleared and removed. 3782 */ 3783 changed = B_TRUE; 3784 3785 if (local->atdt == 0) { 3786 kill_changed = B_TRUE; 3787 } 3788 } else if (ctmp->link_rate != local->link_rate) { 3789 pmcs_prt(pwp, PMCS_PRT_INFO, ctmp, NULL, "%s: %s " 3790 "changed speed from %s to %s", __func__, ctmp->path, 3791 pmcs_get_rate(ctmp->link_rate), 3792 pmcs_get_rate(local->link_rate)); 3793 /* If the speed changed from invalid, force rescan */ 3794 if (!PMCS_VALID_LINK_RATE(ctmp->link_rate)) { 3795 changed = B_TRUE; 3796 RESTART_DISCOVERY(pwp); 3797 } else { 3798 /* Just update to the new link rate */ 3799 ctmp->link_rate = local->link_rate; 3800 } 3801 3802 if (!PMCS_VALID_LINK_RATE(local->link_rate)) { 3803 kill_changed = B_TRUE; 3804 } 3805 } else if (memcmp(ctmp->sas_address, local->sas_address, 3806 sizeof (ctmp->sas_address)) != 0) { 3807 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 3808 "%s: SAS Addr for %s changed from " SAS_ADDR_FMT 3809 "to " SAS_ADDR_FMT " (kill old tree)", __func__, 3810 ctmp->path, SAS_ADDR_PRT(ctmp->sas_address), 3811 SAS_ADDR_PRT(local->sas_address)); 3812 /* 3813 * Force a rescan of this expander after dead 3814 * contents are cleared and removed. 3815 */ 3816 changed = B_TRUE; 3817 } else { 3818 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 3819 "%s: %s looks the same (type %s)", 3820 __func__, ctmp->path, PHY_TYPE(ctmp)); 3821 /* 3822 * If EXPANDER, still mark it changed so we 3823 * re-evaluate its contents. If it's not an expander, 3824 * but it hasn't been configured, also mark it as 3825 * changed so that it will undergo configuration. 3826 */ 3827 if (ctmp->dtype == EXPANDER) { 3828 changed = B_TRUE; 3829 } else if ((ctmp->dtype != NOTHING) && 3830 !ctmp->configured) { 3831 ctmp->changed = 1; 3832 } else { 3833 /* It simply hasn't changed */ 3834 ctmp->changed = 0; 3835 } 3836 } 3837 3838 /* 3839 * If the PHY changed, call pmcs_kill_changed if indicated, 3840 * update its contents to reflect its current state and mark it 3841 * as changed. 3842 */ 3843 if (changed) { 3844 /* 3845 * pmcs_kill_changed will mark the PHY as changed, so 3846 * only do PHY_CHANGED if we did not do kill_changed. 3847 */ 3848 if (kill_changed) { 3849 pmcs_kill_changed(pwp, ctmp, 0); 3850 } else { 3851 /* 3852 * If we're not killing the device, it's not 3853 * dead. Mark the PHY as changed. 3854 */ 3855 PHY_CHANGED(pwp, ctmp); 3856 3857 if (ctmp->dead) { 3858 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, 3859 ctmp, NULL, "%s: Unmarking PHY %s " 3860 "dead, restarting discovery", 3861 __func__, ctmp->path); 3862 ctmp->dead = 0; 3863 RESTART_DISCOVERY(pwp); 3864 } 3865 } 3866 3867 /* 3868 * If the dtype of this PHY is now NOTHING, mark it as 3869 * unconfigured. Set pend_dtype to what the new dtype 3870 * is. It'll get updated at the end of the discovery 3871 * process. 3872 */ 3873 if (local->dtype == NOTHING) { 3874 bzero(ctmp->sas_address, 3875 sizeof (local->sas_address)); 3876 ctmp->atdt = 0; 3877 ctmp->link_rate = 0; 3878 ctmp->pend_dtype = NOTHING; 3879 ctmp->configured = 0; 3880 } else { 3881 (void) memcpy(ctmp->sas_address, 3882 local->sas_address, 3883 sizeof (local->sas_address)); 3884 ctmp->atdt = local->atdt; 3885 ctmp->link_rate = local->link_rate; 3886 ctmp->pend_dtype = local->dtype; 3887 } 3888 } 3889 3890 local = local->sibling; 3891 ctmp = ctmp->sibling; 3892 } 3893 3894 /* 3895 * If we got to here, that means we were able to see all the PHYs 3896 * and we can now update all of the real PHYs with the information 3897 * we got on the local PHYs. Once that's done, free all the local 3898 * PHYs. 3899 */ 3900 3901 pmcs_free_phys(pwp, local_list); 3902 } 3903 3904 /* 3905 * Top level routine to check expanders. We call pmcs_check_expander for 3906 * each expander. Since we're not doing any configuration right now, it 3907 * doesn't matter if this is breadth-first. 3908 */ 3909 static void 3910 pmcs_check_expanders(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3911 { 3912 pmcs_phy_t *phyp, *pnext, *pchild; 3913 3914 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3915 "%s: %s", __func__, pptr->path); 3916 3917 /* 3918 * Check each expander at this level 3919 */ 3920 phyp = pptr; 3921 while (phyp) { 3922 pmcs_lock_phy(phyp); 3923 3924 if ((phyp->dtype == EXPANDER) && phyp->changed && 3925 !phyp->dead && !phyp->subsidiary && 3926 phyp->configured) { 3927 pmcs_check_expander(pwp, phyp); 3928 } 3929 3930 pnext = phyp->sibling; 3931 pmcs_unlock_phy(phyp); 3932 phyp = pnext; 3933 } 3934 3935 /* 3936 * Now check the children 3937 */ 3938 phyp = pptr; 3939 while (phyp) { 3940 pmcs_lock_phy(phyp); 3941 pnext = phyp->sibling; 3942 pchild = phyp->children; 3943 pmcs_unlock_phy(phyp); 3944 3945 if (pchild) { 3946 pmcs_check_expanders(pwp, pchild); 3947 } 3948 3949 phyp = pnext; 3950 } 3951 } 3952 3953 /* 3954 * Called with softstate and PHY locked 3955 */ 3956 static void 3957 pmcs_clear_expander(pmcs_hw_t *pwp, pmcs_phy_t *pptr, int level) 3958 { 3959 pmcs_phy_t *ctmp; 3960 3961 ASSERT(mutex_owned(&pwp->lock)); 3962 ASSERT(mutex_owned(&pptr->phy_lock)); 3963 ASSERT(pptr->level < PMCS_MAX_XPND - 1); 3964 3965 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3966 "%s: checking %s", __func__, pptr->path); 3967 3968 ctmp = pptr->children; 3969 while (ctmp) { 3970 /* 3971 * If the expander is dead, mark its children dead 3972 */ 3973 if (pptr->dead) { 3974 ctmp->dead = 1; 3975 } 3976 if (ctmp->dtype == EXPANDER) { 3977 pmcs_clear_expander(pwp, ctmp, level + 1); 3978 } 3979 ctmp = ctmp->sibling; 3980 } 3981 3982 /* 3983 * If this expander is not dead, we're done here. 3984 */ 3985 if (!pptr->dead) { 3986 return; 3987 } 3988 3989 /* 3990 * Now snip out the list of children below us and release them 3991 */ 3992 if (pptr->children) { 3993 pmcs_add_dead_phys(pwp, pptr->children); 3994 } 3995 3996 pptr->children = NULL; 3997 3998 /* 3999 * Clear subsidiary phys as well. Getting the parent's PHY lock 4000 * is only necessary if level == 0 since otherwise the parent is 4001 * already locked. 4002 */ 4003 if (!IS_ROOT_PHY(pptr)) { 4004 if (level == 0) { 4005 mutex_enter(&pptr->parent->phy_lock); 4006 } 4007 ctmp = pptr->parent->children; 4008 if (level == 0) { 4009 mutex_exit(&pptr->parent->phy_lock); 4010 } 4011 } else { 4012 ctmp = pwp->root_phys; 4013 } 4014 4015 while (ctmp) { 4016 if (ctmp == pptr) { 4017 ctmp = ctmp->sibling; 4018 continue; 4019 } 4020 /* 4021 * We only need to lock subsidiary PHYs on the level 0 4022 * expander. Any children of that expander, subsidiaries or 4023 * not, will already be locked. 4024 */ 4025 if (level == 0) { 4026 pmcs_lock_phy(ctmp); 4027 } 4028 if (ctmp->dtype != EXPANDER || ctmp->subsidiary == 0 || 4029 memcmp(ctmp->sas_address, pptr->sas_address, 4030 sizeof (ctmp->sas_address)) != 0) { 4031 if (level == 0) { 4032 pmcs_unlock_phy(ctmp); 4033 } 4034 ctmp = ctmp->sibling; 4035 continue; 4036 } 4037 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 4038 "%s: subsidiary %s", __func__, ctmp->path); 4039 pmcs_clear_phy(pwp, ctmp); 4040 if (level == 0) { 4041 pmcs_unlock_phy(ctmp); 4042 } 4043 ctmp = ctmp->sibling; 4044 } 4045 4046 pmcs_clear_phy(pwp, pptr); 4047 } 4048 4049 /* 4050 * Called with PHY locked and with scratch acquired. We return 0 if 4051 * we fail to allocate resources or notice that the configuration 4052 * count changed while we were running the command. We return 4053 * less than zero if we had an I/O error or received an unsupported 4054 * configuration. Otherwise we return the number of phys in the 4055 * expander. 4056 */ 4057 #define DFM(m, y) if (m == NULL) m = y 4058 static int 4059 pmcs_expander_get_nphy(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 4060 { 4061 struct pmcwork *pwrk; 4062 char buf[64]; 4063 const uint_t rdoff = 0x100; /* returned data offset */ 4064 smp_response_frame_t *srf; 4065 smp_report_general_resp_t *srgr; 4066 uint32_t msg[PMCS_MSG_SIZE], *ptr, htag, status, ival; 4067 int result = 0; 4068 4069 ival = 0x40001100; 4070 4071 again: 4072 if (!pptr->iport || !pptr->valid_device_id) { 4073 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, pptr->target, 4074 "%s: Can't reach PHY %s", __func__, pptr->path); 4075 goto out; 4076 } 4077 4078 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 4079 if (pwrk == NULL) { 4080 goto out; 4081 } 4082 (void) memset(pwp->scratch, 0x77, PMCS_SCRATCH_SIZE); 4083 pwrk->arg = pwp->scratch; 4084 pwrk->dtype = pptr->dtype; 4085 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4086 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4087 if (ptr == NULL) { 4088 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4089 pmcs_prt(pwp, PMCS_PRT_DEBUG2, pptr, NULL, 4090 "%s: GET_IQ_ENTRY failed", __func__); 4091 pmcs_pwork(pwp, pwrk); 4092 goto out; 4093 } 4094 4095 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, PMCIN_SMP_REQUEST)); 4096 msg[1] = LE_32(pwrk->htag); 4097 msg[2] = LE_32(pptr->device_id); 4098 msg[3] = LE_32((4 << SMP_REQUEST_LENGTH_SHIFT) | SMP_INDIRECT_RESPONSE); 4099 /* 4100 * Send SMP REPORT GENERAL (of either SAS1.1 or SAS2 flavors). 4101 */ 4102 msg[4] = BE_32(ival); 4103 msg[5] = 0; 4104 msg[6] = 0; 4105 msg[7] = 0; 4106 msg[8] = 0; 4107 msg[9] = 0; 4108 msg[10] = 0; 4109 msg[11] = 0; 4110 msg[12] = LE_32(DWORD0(pwp->scratch_dma+rdoff)); 4111 msg[13] = LE_32(DWORD1(pwp->scratch_dma+rdoff)); 4112 msg[14] = LE_32(PMCS_SCRATCH_SIZE - rdoff); 4113 msg[15] = 0; 4114 4115 COPY_MESSAGE(ptr, msg, PMCS_MSG_SIZE); 4116 4117 /* SMP serialization */ 4118 pmcs_smp_acquire(pptr->iport); 4119 4120 pwrk->state = PMCS_WORK_STATE_ONCHIP; 4121 htag = pwrk->htag; 4122 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4123 4124 pmcs_unlock_phy(pptr); 4125 WAIT_FOR(pwrk, 1000, result); 4126 /* Release SMP lock before reacquiring PHY lock */ 4127 pmcs_smp_release(pptr->iport); 4128 pmcs_lock_phy(pptr); 4129 4130 pmcs_pwork(pwp, pwrk); 4131 4132 mutex_enter(&pwp->config_lock); 4133 if (pwp->config_changed) { 4134 RESTART_DISCOVERY_LOCKED(pwp); 4135 mutex_exit(&pwp->config_lock); 4136 result = 0; 4137 goto out; 4138 } 4139 mutex_exit(&pwp->config_lock); 4140 4141 if (result) { 4142 pmcs_timed_out(pwp, htag, __func__); 4143 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4144 "%s: Issuing SMP ABORT for htag 0x%08x", __func__, htag); 4145 if (pmcs_abort(pwp, pptr, htag, 0, 0)) { 4146 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4147 "%s: Unable to issue SMP ABORT for htag 0x%08x", 4148 __func__, htag); 4149 } else { 4150 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4151 "%s: Issuing SMP ABORT for htag 0x%08x", 4152 __func__, htag); 4153 } 4154 result = 0; 4155 goto out; 4156 } 4157 ptr = (void *)pwp->scratch; 4158 status = LE_32(ptr[2]); 4159 if (status == PMCOUT_STATUS_UNDERFLOW || 4160 status == PMCOUT_STATUS_OVERFLOW) { 4161 pmcs_prt(pwp, PMCS_PRT_DEBUG_UNDERFLOW, pptr, NULL, 4162 "%s: over/underflow", __func__); 4163 status = PMCOUT_STATUS_OK; 4164 } 4165 srf = (smp_response_frame_t *)&((uint32_t *)pwp->scratch)[rdoff >> 2]; 4166 srgr = (smp_report_general_resp_t *) 4167 &((uint32_t *)pwp->scratch)[(rdoff >> 2)+1]; 4168 4169 if (status != PMCOUT_STATUS_OK) { 4170 char *nag = NULL; 4171 (void) snprintf(buf, sizeof (buf), 4172 "%s: SMP op failed (0x%x)", __func__, status); 4173 switch (status) { 4174 case PMCOUT_STATUS_IO_PORT_IN_RESET: 4175 DFM(nag, "I/O Port In Reset"); 4176 /* FALLTHROUGH */ 4177 case PMCOUT_STATUS_ERROR_HW_TIMEOUT: 4178 DFM(nag, "Hardware Timeout"); 4179 /* FALLTHROUGH */ 4180 case PMCOUT_STATUS_ERROR_INTERNAL_SMP_RESOURCE: 4181 DFM(nag, "Internal SMP Resource Failure"); 4182 /* FALLTHROUGH */ 4183 case PMCOUT_STATUS_XFER_ERR_PHY_NOT_READY: 4184 DFM(nag, "PHY Not Ready"); 4185 /* FALLTHROUGH */ 4186 case PMCOUT_STATUS_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 4187 DFM(nag, "Connection Rate Not Supported"); 4188 /* FALLTHROUGH */ 4189 case PMCOUT_STATUS_IO_XFER_OPEN_RETRY_TIMEOUT: 4190 DFM(nag, "Open Retry Timeout"); 4191 /* FALLTHROUGH */ 4192 case PMCOUT_STATUS_SMP_RESP_CONNECTION_ERROR: 4193 DFM(nag, "Response Connection Error"); 4194 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4195 "%s: expander %s SMP operation failed (%s)", 4196 __func__, pptr->path, nag); 4197 break; 4198 4199 /* 4200 * For the IO_DS_NON_OPERATIONAL case, we need to kick off 4201 * device state recovery and return 0 so that the caller 4202 * doesn't assume this expander is dead for good. 4203 */ 4204 case PMCOUT_STATUS_IO_DS_NON_OPERATIONAL: { 4205 pmcs_xscsi_t *xp = pptr->target; 4206 4207 pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, pptr, xp, 4208 "%s: expander %s device state non-operational", 4209 __func__, pptr->path); 4210 4211 if (xp == NULL) { 4212 /* 4213 * Kick off recovery right now. 4214 */ 4215 SCHEDULE_WORK(pwp, PMCS_WORK_DS_ERR_RECOVERY); 4216 (void) ddi_taskq_dispatch(pwp->tq, pmcs_worker, 4217 pwp, DDI_NOSLEEP); 4218 } else { 4219 mutex_enter(&xp->statlock); 4220 pmcs_start_dev_state_recovery(xp, pptr); 4221 mutex_exit(&xp->statlock); 4222 } 4223 4224 break; 4225 } 4226 4227 default: 4228 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, buf, ptr); 4229 result = -EIO; 4230 break; 4231 } 4232 } else if (srf->srf_frame_type != SMP_FRAME_TYPE_RESPONSE) { 4233 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4234 "%s: bad response frame type 0x%x", 4235 __func__, srf->srf_frame_type); 4236 result = -EINVAL; 4237 } else if (srf->srf_function != SMP_FUNC_REPORT_GENERAL) { 4238 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4239 "%s: bad response function 0x%x", 4240 __func__, srf->srf_function); 4241 result = -EINVAL; 4242 } else if (srf->srf_result != 0) { 4243 /* 4244 * Check to see if we have a value of 3 for failure and 4245 * whether we were using a SAS2.0 allocation length value 4246 * and retry without it. 4247 */ 4248 if (srf->srf_result == 3 && (ival & 0xff00)) { 4249 ival &= ~0xff00; 4250 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4251 "%s: err 0x%x with SAS2 request- retry with SAS1", 4252 __func__, srf->srf_result); 4253 goto again; 4254 } 4255 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4256 "%s: bad response 0x%x", __func__, srf->srf_result); 4257 result = -EINVAL; 4258 } else if (srgr->srgr_configuring) { 4259 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4260 "%s: expander at phy %s is still configuring", 4261 __func__, pptr->path); 4262 result = 0; 4263 } else { 4264 result = srgr->srgr_number_of_phys; 4265 if (ival & 0xff00) { 4266 pptr->tolerates_sas2 = 1; 4267 } 4268 /* 4269 * Save off the REPORT_GENERAL response 4270 */ 4271 bcopy(srgr, &pptr->rg_resp, sizeof (smp_report_general_resp_t)); 4272 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4273 "%s has %d phys and %s SAS2", pptr->path, result, 4274 pptr->tolerates_sas2? "tolerates" : "does not tolerate"); 4275 } 4276 out: 4277 return (result); 4278 } 4279 4280 /* 4281 * Called with expander locked (and thus, pptr) as well as all PHYs up to 4282 * the root, and scratch acquired. Return 0 if we fail to allocate resources 4283 * or notice that the configuration changed while we were running the command. 4284 * 4285 * We return less than zero if we had an I/O error or received an 4286 * unsupported configuration. 4287 */ 4288 static int 4289 pmcs_expander_content_discover(pmcs_hw_t *pwp, pmcs_phy_t *expander, 4290 pmcs_phy_t *pptr) 4291 { 4292 struct pmcwork *pwrk; 4293 char buf[64]; 4294 uint8_t sas_address[8]; 4295 uint8_t att_sas_address[8]; 4296 smp_response_frame_t *srf; 4297 smp_discover_resp_t *sdr; 4298 const uint_t rdoff = 0x100; /* returned data offset */ 4299 uint8_t *roff; 4300 uint32_t status, *ptr, msg[PMCS_MSG_SIZE], htag; 4301 int result = 0; 4302 uint8_t ini_support; 4303 uint8_t tgt_support; 4304 4305 if (!expander->iport || !expander->valid_device_id) { 4306 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, expander, expander->target, 4307 "%s: Can't reach PHY %s", __func__, expander->path); 4308 goto out; 4309 } 4310 4311 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, expander); 4312 if (pwrk == NULL) { 4313 goto out; 4314 } 4315 (void) memset(pwp->scratch, 0x77, PMCS_SCRATCH_SIZE); 4316 pwrk->arg = pwp->scratch; 4317 pwrk->dtype = expander->dtype; 4318 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, PMCIN_SMP_REQUEST)); 4319 msg[1] = LE_32(pwrk->htag); 4320 msg[2] = LE_32(expander->device_id); 4321 msg[3] = LE_32((12 << SMP_REQUEST_LENGTH_SHIFT) | 4322 SMP_INDIRECT_RESPONSE); 4323 /* 4324 * Send SMP DISCOVER (of either SAS1.1 or SAS2 flavors). 4325 */ 4326 if (expander->tolerates_sas2) { 4327 msg[4] = BE_32(0x40101B00); 4328 } else { 4329 msg[4] = BE_32(0x40100000); 4330 } 4331 msg[5] = 0; 4332 msg[6] = BE_32((pptr->phynum << 16)); 4333 msg[7] = 0; 4334 msg[8] = 0; 4335 msg[9] = 0; 4336 msg[10] = 0; 4337 msg[11] = 0; 4338 msg[12] = LE_32(DWORD0(pwp->scratch_dma+rdoff)); 4339 msg[13] = LE_32(DWORD1(pwp->scratch_dma+rdoff)); 4340 msg[14] = LE_32(PMCS_SCRATCH_SIZE - rdoff); 4341 msg[15] = 0; 4342 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4343 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4344 if (ptr == NULL) { 4345 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4346 goto out; 4347 } 4348 4349 COPY_MESSAGE(ptr, msg, PMCS_MSG_SIZE); 4350 4351 /* SMP serialization */ 4352 pmcs_smp_acquire(expander->iport); 4353 4354 pwrk->state = PMCS_WORK_STATE_ONCHIP; 4355 htag = pwrk->htag; 4356 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4357 4358 /* 4359 * Drop PHY lock while waiting so other completions aren't potentially 4360 * blocked. 4361 */ 4362 pmcs_unlock_phy(expander); 4363 WAIT_FOR(pwrk, 1000, result); 4364 /* Release SMP lock before reacquiring PHY lock */ 4365 pmcs_smp_release(expander->iport); 4366 pmcs_lock_phy(expander); 4367 4368 pmcs_pwork(pwp, pwrk); 4369 4370 mutex_enter(&pwp->config_lock); 4371 if (pwp->config_changed) { 4372 RESTART_DISCOVERY_LOCKED(pwp); 4373 mutex_exit(&pwp->config_lock); 4374 result = 0; 4375 goto out; 4376 } 4377 mutex_exit(&pwp->config_lock); 4378 4379 if (result) { 4380 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, pmcs_timeo, __func__); 4381 if (pmcs_abort(pwp, expander, htag, 0, 0)) { 4382 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4383 "%s: Unable to issue SMP ABORT for htag 0x%08x", 4384 __func__, htag); 4385 } else { 4386 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4387 "%s: Issuing SMP ABORT for htag 0x%08x", 4388 __func__, htag); 4389 } 4390 result = -ETIMEDOUT; 4391 goto out; 4392 } 4393 ptr = (void *)pwp->scratch; 4394 /* 4395 * Point roff to the DMA offset for returned data 4396 */ 4397 roff = pwp->scratch; 4398 roff += rdoff; 4399 srf = (smp_response_frame_t *)roff; 4400 sdr = (smp_discover_resp_t *)(roff+4); 4401 status = LE_32(ptr[2]); 4402 if (status == PMCOUT_STATUS_UNDERFLOW || 4403 status == PMCOUT_STATUS_OVERFLOW) { 4404 pmcs_prt(pwp, PMCS_PRT_DEBUG_UNDERFLOW, pptr, NULL, 4405 "%s: over/underflow", __func__); 4406 status = PMCOUT_STATUS_OK; 4407 } 4408 if (status != PMCOUT_STATUS_OK) { 4409 char *nag = NULL; 4410 (void) snprintf(buf, sizeof (buf), 4411 "%s: SMP op failed (0x%x)", __func__, status); 4412 switch (status) { 4413 case PMCOUT_STATUS_ERROR_HW_TIMEOUT: 4414 DFM(nag, "Hardware Timeout"); 4415 /* FALLTHROUGH */ 4416 case PMCOUT_STATUS_ERROR_INTERNAL_SMP_RESOURCE: 4417 DFM(nag, "Internal SMP Resource Failure"); 4418 /* FALLTHROUGH */ 4419 case PMCOUT_STATUS_XFER_ERR_PHY_NOT_READY: 4420 DFM(nag, "PHY Not Ready"); 4421 /* FALLTHROUGH */ 4422 case PMCOUT_STATUS_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 4423 DFM(nag, "Connection Rate Not Supported"); 4424 /* FALLTHROUGH */ 4425 case PMCOUT_STATUS_IO_XFER_OPEN_RETRY_TIMEOUT: 4426 DFM(nag, "Open Retry Timeout"); 4427 /* FALLTHROUGH */ 4428 case PMCOUT_STATUS_SMP_RESP_CONNECTION_ERROR: 4429 DFM(nag, "Response Connection Error"); 4430 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4431 "%s: expander %s SMP operation failed (%s)", 4432 __func__, pptr->path, nag); 4433 break; 4434 default: 4435 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, buf, ptr); 4436 result = -EIO; 4437 break; 4438 } 4439 goto out; 4440 } else if (srf->srf_frame_type != SMP_FRAME_TYPE_RESPONSE) { 4441 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4442 "%s: bad response frame type 0x%x", 4443 __func__, srf->srf_frame_type); 4444 result = -EINVAL; 4445 goto out; 4446 } else if (srf->srf_function != SMP_FUNC_DISCOVER) { 4447 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4448 "%s: bad response function 0x%x", 4449 __func__, srf->srf_function); 4450 result = -EINVAL; 4451 goto out; 4452 } else if (srf->srf_result != SMP_RES_FUNCTION_ACCEPTED) { 4453 result = pmcs_smp_function_result(pwp, srf); 4454 /* Need not fail if PHY is Vacant */ 4455 if (result != SMP_RES_PHY_VACANT) { 4456 result = -EINVAL; 4457 goto out; 4458 } 4459 } 4460 4461 /* 4462 * Save off the DISCOVER response 4463 */ 4464 bcopy(sdr, &pptr->disc_resp, sizeof (smp_discover_resp_t)); 4465 4466 ini_support = (sdr->sdr_attached_sata_host | 4467 (sdr->sdr_attached_smp_initiator << 1) | 4468 (sdr->sdr_attached_stp_initiator << 2) | 4469 (sdr->sdr_attached_ssp_initiator << 3)); 4470 4471 tgt_support = (sdr->sdr_attached_sata_device | 4472 (sdr->sdr_attached_smp_target << 1) | 4473 (sdr->sdr_attached_stp_target << 2) | 4474 (sdr->sdr_attached_ssp_target << 3)); 4475 4476 pmcs_wwn2barray(BE_64(sdr->sdr_sas_addr), sas_address); 4477 pmcs_wwn2barray(BE_64(sdr->sdr_attached_sas_addr), att_sas_address); 4478 4479 /* 4480 * Set the routing attribute regardless of the PHY type. 4481 */ 4482 pptr->routing_attr = sdr->sdr_routing_attr; 4483 4484 switch (sdr->sdr_attached_device_type) { 4485 case SAS_IF_DTYPE_ENDPOINT: 4486 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4487 "exp_content: %s atdt=0x%x lr=%x is=%x ts=%x SAS=" 4488 SAS_ADDR_FMT " attSAS=" SAS_ADDR_FMT " atPHY=%x", 4489 pptr->path, 4490 sdr->sdr_attached_device_type, 4491 sdr->sdr_negotiated_logical_link_rate, 4492 ini_support, 4493 tgt_support, 4494 SAS_ADDR_PRT(sas_address), 4495 SAS_ADDR_PRT(att_sas_address), 4496 sdr->sdr_attached_phy_identifier); 4497 4498 if (sdr->sdr_attached_sata_device || 4499 sdr->sdr_attached_stp_target) { 4500 pptr->dtype = SATA; 4501 } else if (sdr->sdr_attached_ssp_target) { 4502 pptr->dtype = SAS; 4503 } else if (tgt_support || ini_support) { 4504 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4505 "%s: %s has tgt support=%x init support=(%x)", 4506 __func__, pptr->path, tgt_support, ini_support); 4507 } 4508 4509 switch (pptr->routing_attr) { 4510 case SMP_ROUTING_SUBTRACTIVE: 4511 case SMP_ROUTING_TABLE: 4512 case SMP_ROUTING_DIRECT: 4513 pptr->routing_method = SMP_ROUTING_DIRECT; 4514 break; 4515 default: 4516 pptr->routing_method = 0xff; /* Invalid method */ 4517 break; 4518 } 4519 pmcs_update_phy_pm_props(pptr, (1ULL << pptr->phynum), 4520 (1ULL << sdr->sdr_attached_phy_identifier), B_TRUE); 4521 break; 4522 case SAS_IF_DTYPE_EDGE: 4523 case SAS_IF_DTYPE_FANOUT: 4524 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4525 "exp_content: %s atdt=0x%x lr=%x is=%x ts=%x SAS=" 4526 SAS_ADDR_FMT " attSAS=" SAS_ADDR_FMT " atPHY=%x", 4527 pptr->path, 4528 sdr->sdr_attached_device_type, 4529 sdr->sdr_negotiated_logical_link_rate, 4530 ini_support, 4531 tgt_support, 4532 SAS_ADDR_PRT(sas_address), 4533 SAS_ADDR_PRT(att_sas_address), 4534 sdr->sdr_attached_phy_identifier); 4535 if (sdr->sdr_attached_smp_target) { 4536 /* 4537 * Avoid configuring phys that just point back 4538 * at a parent phy 4539 */ 4540 if (expander->parent && 4541 memcmp(expander->parent->sas_address, 4542 att_sas_address, 4543 sizeof (expander->parent->sas_address)) == 0) { 4544 pmcs_prt(pwp, PMCS_PRT_DEBUG3, pptr, NULL, 4545 "%s: skipping port back to parent " 4546 "expander (%s)", __func__, pptr->path); 4547 pptr->dtype = NOTHING; 4548 break; 4549 } 4550 pptr->dtype = EXPANDER; 4551 4552 } else if (tgt_support || ini_support) { 4553 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4554 "%s has tgt support=%x init support=(%x)", 4555 pptr->path, tgt_support, ini_support); 4556 pptr->dtype = EXPANDER; 4557 } 4558 if (pptr->routing_attr == SMP_ROUTING_DIRECT) { 4559 pptr->routing_method = 0xff; /* Invalid method */ 4560 } else { 4561 pptr->routing_method = pptr->routing_attr; 4562 } 4563 pmcs_update_phy_pm_props(pptr, (1ULL << pptr->phynum), 4564 (1ULL << sdr->sdr_attached_phy_identifier), B_TRUE); 4565 break; 4566 default: 4567 pptr->dtype = NOTHING; 4568 break; 4569 } 4570 if (pptr->dtype != NOTHING) { 4571 pmcs_phy_t *ctmp; 4572 4573 /* 4574 * If the attached device is a SATA device and the expander 4575 * is (possibly) a SAS2 compliant expander, check for whether 4576 * there is a NAA=5 WWN field starting at this offset and 4577 * use that for the SAS Address for this device. 4578 */ 4579 if (expander->tolerates_sas2 && pptr->dtype == SATA && 4580 (roff[SAS_ATTACHED_NAME_OFFSET] >> 8) == 0x5) { 4581 (void) memcpy(pptr->sas_address, 4582 &roff[SAS_ATTACHED_NAME_OFFSET], 8); 4583 } else { 4584 (void) memcpy(pptr->sas_address, att_sas_address, 8); 4585 } 4586 pptr->atdt = (sdr->sdr_attached_device_type); 4587 /* 4588 * Now run up from the expander's parent up to the top to 4589 * make sure we only use the least common link_rate. 4590 */ 4591 for (ctmp = expander->parent; ctmp; ctmp = ctmp->parent) { 4592 if (ctmp->link_rate < 4593 sdr->sdr_negotiated_logical_link_rate) { 4594 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4595 "%s: derating link rate from %x to %x due " 4596 "to %s being slower", pptr->path, 4597 sdr->sdr_negotiated_logical_link_rate, 4598 ctmp->link_rate, 4599 ctmp->path); 4600 sdr->sdr_negotiated_logical_link_rate = 4601 ctmp->link_rate; 4602 } 4603 } 4604 pptr->link_rate = sdr->sdr_negotiated_logical_link_rate; 4605 pptr->state.prog_min_rate = sdr->sdr_prog_min_phys_link_rate; 4606 pptr->state.hw_min_rate = sdr->sdr_hw_min_phys_link_rate; 4607 pptr->state.prog_max_rate = sdr->sdr_prog_max_phys_link_rate; 4608 pptr->state.hw_max_rate = sdr->sdr_hw_max_phys_link_rate; 4609 PHY_CHANGED(pwp, pptr); 4610 } else { 4611 pmcs_clear_phy(pwp, pptr); 4612 } 4613 result = 1; 4614 out: 4615 return (result); 4616 } 4617 4618 /* 4619 * Get a work structure and assign it a tag with type and serial number 4620 * If a structure is returned, it is returned locked. 4621 */ 4622 pmcwork_t * 4623 pmcs_gwork(pmcs_hw_t *pwp, uint32_t tag_type, pmcs_phy_t *phyp) 4624 { 4625 pmcwork_t *p; 4626 uint16_t snum; 4627 uint32_t off; 4628 4629 mutex_enter(&pwp->wfree_lock); 4630 p = STAILQ_FIRST(&pwp->wf); 4631 if (p == NULL) { 4632 /* 4633 * If we couldn't get a work structure, it's time to bite 4634 * the bullet, grab the pfree_lock and copy over all the 4635 * work structures from the pending free list to the actual 4636 * free list (assuming it's not also empty). 4637 */ 4638 mutex_enter(&pwp->pfree_lock); 4639 if (STAILQ_FIRST(&pwp->pf) == NULL) { 4640 mutex_exit(&pwp->pfree_lock); 4641 mutex_exit(&pwp->wfree_lock); 4642 return (NULL); 4643 } 4644 pwp->wf.stqh_first = pwp->pf.stqh_first; 4645 pwp->wf.stqh_last = pwp->pf.stqh_last; 4646 STAILQ_INIT(&pwp->pf); 4647 mutex_exit(&pwp->pfree_lock); 4648 4649 p = STAILQ_FIRST(&pwp->wf); 4650 ASSERT(p != NULL); 4651 } 4652 STAILQ_REMOVE(&pwp->wf, p, pmcwork, next); 4653 snum = pwp->wserno++; 4654 mutex_exit(&pwp->wfree_lock); 4655 4656 off = p - pwp->work; 4657 4658 mutex_enter(&p->lock); 4659 ASSERT(p->state == PMCS_WORK_STATE_NIL); 4660 ASSERT(p->htag == PMCS_TAG_FREE); 4661 p->htag = (tag_type << PMCS_TAG_TYPE_SHIFT) & PMCS_TAG_TYPE_MASK; 4662 p->htag |= ((snum << PMCS_TAG_SERNO_SHIFT) & PMCS_TAG_SERNO_MASK); 4663 p->htag |= ((off << PMCS_TAG_INDEX_SHIFT) & PMCS_TAG_INDEX_MASK); 4664 p->start = gethrtime(); 4665 p->state = PMCS_WORK_STATE_READY; 4666 p->ssp_event = 0; 4667 p->dead = 0; 4668 4669 if (phyp) { 4670 p->phy = phyp; 4671 pmcs_inc_phy_ref_count(phyp); 4672 } 4673 4674 return (p); 4675 } 4676 4677 /* 4678 * Called with pwrk lock held. Returned with lock released. 4679 */ 4680 void 4681 pmcs_pwork(pmcs_hw_t *pwp, pmcwork_t *p) 4682 { 4683 ASSERT(p != NULL); 4684 ASSERT(mutex_owned(&p->lock)); 4685 4686 p->last_ptr = p->ptr; 4687 p->last_arg = p->arg; 4688 p->last_phy = p->phy; 4689 p->last_xp = p->xp; 4690 p->last_htag = p->htag; 4691 p->last_state = p->state; 4692 p->finish = gethrtime(); 4693 4694 if (p->phy) { 4695 pmcs_dec_phy_ref_count(p->phy); 4696 } 4697 4698 p->state = PMCS_WORK_STATE_NIL; 4699 p->htag = PMCS_TAG_FREE; 4700 p->xp = NULL; 4701 p->ptr = NULL; 4702 p->arg = NULL; 4703 p->phy = NULL; 4704 p->abt_htag = 0; 4705 p->timer = 0; 4706 mutex_exit(&p->lock); 4707 4708 if (mutex_tryenter(&pwp->wfree_lock) == 0) { 4709 mutex_enter(&pwp->pfree_lock); 4710 STAILQ_INSERT_TAIL(&pwp->pf, p, next); 4711 mutex_exit(&pwp->pfree_lock); 4712 } else { 4713 STAILQ_INSERT_TAIL(&pwp->wf, p, next); 4714 mutex_exit(&pwp->wfree_lock); 4715 } 4716 } 4717 4718 /* 4719 * Find a work structure based upon a tag and make sure that the tag 4720 * serial number matches the work structure we've found. 4721 * If a structure is found, its lock is held upon return. 4722 */ 4723 pmcwork_t * 4724 pmcs_tag2wp(pmcs_hw_t *pwp, uint32_t htag) 4725 { 4726 pmcwork_t *p; 4727 uint32_t idx = PMCS_TAG_INDEX(htag); 4728 4729 p = &pwp->work[idx]; 4730 4731 mutex_enter(&p->lock); 4732 if (p->htag == htag) { 4733 return (p); 4734 } 4735 mutex_exit(&p->lock); 4736 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, 4737 "INDEX 0x%x HTAG 0x%x got p->htag 0x%x", idx, htag, p->htag); 4738 return (NULL); 4739 } 4740 4741 /* 4742 * Issue an abort for a command or for all commands. 4743 * 4744 * Since this can be called from interrupt context, 4745 * we don't wait for completion if wait is not set. 4746 * 4747 * Called with PHY lock held. 4748 */ 4749 int 4750 pmcs_abort(pmcs_hw_t *pwp, pmcs_phy_t *pptr, uint32_t tag, int all_cmds, 4751 int wait) 4752 { 4753 pmcwork_t *pwrk; 4754 pmcs_xscsi_t *tgt; 4755 uint32_t msg[PMCS_MSG_SIZE], *ptr; 4756 int result, abt_type; 4757 uint32_t abt_htag, status; 4758 4759 if (pptr->abort_all_start) { 4760 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, "%s: ABORT_ALL for " 4761 "(%s) already in progress.", __func__, pptr->path); 4762 return (EBUSY); 4763 } 4764 4765 switch (pptr->dtype) { 4766 case SAS: 4767 abt_type = PMCIN_SSP_ABORT; 4768 break; 4769 case SATA: 4770 abt_type = PMCIN_SATA_ABORT; 4771 break; 4772 case EXPANDER: 4773 abt_type = PMCIN_SMP_ABORT; 4774 break; 4775 default: 4776 return (0); 4777 } 4778 4779 pwrk = pmcs_gwork(pwp, wait ? PMCS_TAG_TYPE_WAIT : PMCS_TAG_TYPE_NONE, 4780 pptr); 4781 4782 if (pwrk == NULL) { 4783 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nowrk, __func__); 4784 return (ENOMEM); 4785 } 4786 4787 pwrk->dtype = pptr->dtype; 4788 if (wait) { 4789 pwrk->arg = msg; 4790 } 4791 if (pptr->valid_device_id == 0) { 4792 pmcs_pwork(pwp, pwrk); 4793 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4794 "%s: Invalid DeviceID", __func__); 4795 return (ENODEV); 4796 } 4797 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, abt_type)); 4798 msg[1] = LE_32(pwrk->htag); 4799 msg[2] = LE_32(pptr->device_id); 4800 if (all_cmds) { 4801 msg[3] = 0; 4802 msg[4] = LE_32(1); 4803 pwrk->ptr = NULL; 4804 pptr->abort_all_start = gethrtime(); 4805 } else { 4806 msg[3] = LE_32(tag); 4807 msg[4] = 0; 4808 pwrk->abt_htag = tag; 4809 } 4810 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4811 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4812 if (ptr == NULL) { 4813 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4814 pmcs_pwork(pwp, pwrk); 4815 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nomsg, __func__); 4816 return (ENOMEM); 4817 } 4818 4819 COPY_MESSAGE(ptr, msg, 5); 4820 if (all_cmds) { 4821 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4822 "%s: aborting all commands for %s device %s. (htag=0x%x)", 4823 __func__, pmcs_get_typename(pptr->dtype), pptr->path, 4824 msg[1]); 4825 } else { 4826 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4827 "%s: aborting tag 0x%x for %s device %s. (htag=0x%x)", 4828 __func__, tag, pmcs_get_typename(pptr->dtype), pptr->path, 4829 msg[1]); 4830 } 4831 pwrk->state = PMCS_WORK_STATE_ONCHIP; 4832 4833 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4834 if (!wait) { 4835 mutex_exit(&pwrk->lock); 4836 return (0); 4837 } 4838 4839 abt_htag = pwrk->htag; 4840 pmcs_unlock_phy(pwrk->phy); 4841 WAIT_FOR(pwrk, 1000, result); 4842 pmcs_lock_phy(pwrk->phy); 4843 4844 tgt = pwrk->xp; 4845 pmcs_pwork(pwp, pwrk); 4846 4847 if (tgt != NULL) { 4848 mutex_enter(&tgt->aqlock); 4849 if (!STAILQ_EMPTY(&tgt->aq)) { 4850 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 4851 "%s: Abort complete (result=0x%x), but " 4852 "aq not empty (tgt 0x%p), waiting", 4853 __func__, result, (void *)tgt); 4854 cv_wait(&tgt->abort_cv, &tgt->aqlock); 4855 } 4856 mutex_exit(&tgt->aqlock); 4857 } 4858 4859 if (all_cmds) { 4860 pptr->abort_all_start = 0; 4861 cv_signal(&pptr->abort_all_cv); 4862 } 4863 4864 if (result) { 4865 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 4866 "%s: Abort (htag 0x%08x) request timed out", 4867 __func__, abt_htag); 4868 if (tgt != NULL) { 4869 mutex_enter(&tgt->statlock); 4870 if ((tgt->dev_state != PMCS_DEVICE_STATE_IN_RECOVERY) && 4871 (tgt->dev_state != 4872 PMCS_DEVICE_STATE_NON_OPERATIONAL)) { 4873 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 4874 "%s: Trying DS error recovery for tgt 0x%p", 4875 __func__, (void *)tgt); 4876 (void) pmcs_send_err_recovery_cmd(pwp, 4877 PMCS_DEVICE_STATE_IN_RECOVERY, pptr, tgt); 4878 } 4879 mutex_exit(&tgt->statlock); 4880 } 4881 return (ETIMEDOUT); 4882 } 4883 4884 status = LE_32(msg[2]); 4885 if (status != PMCOUT_STATUS_OK) { 4886 /* 4887 * The only non-success status are IO_NOT_VALID & 4888 * IO_ABORT_IN_PROGRESS. 4889 * In case of IO_ABORT_IN_PROGRESS, the other ABORT cmd's 4890 * status is of concern and this duplicate cmd status can 4891 * be ignored. 4892 * If IO_NOT_VALID, that's not an error per-se. 4893 * For abort of single I/O complete the command anyway. 4894 * If, however, we were aborting all, that is a problem 4895 * as IO_NOT_VALID really means that the IO or device is 4896 * not there. So, discovery process will take of the cleanup. 4897 */ 4898 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 4899 "%s: abort result 0x%x", __func__, LE_32(msg[2])); 4900 if (all_cmds) { 4901 PHY_CHANGED(pwp, pptr); 4902 RESTART_DISCOVERY(pwp); 4903 } else { 4904 return (EINVAL); 4905 } 4906 4907 return (0); 4908 } 4909 4910 if (tgt != NULL) { 4911 mutex_enter(&tgt->statlock); 4912 if (tgt->dev_state == PMCS_DEVICE_STATE_IN_RECOVERY) { 4913 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 4914 "%s: Restoring OPERATIONAL dev_state for tgt 0x%p", 4915 __func__, (void *)tgt); 4916 (void) pmcs_send_err_recovery_cmd(pwp, 4917 PMCS_DEVICE_STATE_OPERATIONAL, pptr, tgt); 4918 } 4919 mutex_exit(&tgt->statlock); 4920 } 4921 4922 return (0); 4923 } 4924 4925 /* 4926 * Issue a task management function to an SSP device. 4927 * 4928 * Called with PHY lock held. 4929 * statlock CANNOT be held upon entry. 4930 */ 4931 int 4932 pmcs_ssp_tmf(pmcs_hw_t *pwp, pmcs_phy_t *pptr, uint8_t tmf, uint32_t tag, 4933 uint64_t lun, uint32_t *response) 4934 { 4935 int result, ds; 4936 uint8_t local[PMCS_QENTRY_SIZE << 1], *xd; 4937 sas_ssp_rsp_iu_t *rptr = (void *)local; 4938 static const uint8_t ssp_rsp_evec[] = { 4939 0x58, 0x61, 0x56, 0x72, 0x00 4940 }; 4941 uint32_t msg[PMCS_MSG_SIZE], *ptr, status; 4942 struct pmcwork *pwrk; 4943 pmcs_xscsi_t *xp; 4944 4945 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 4946 if (pwrk == NULL) { 4947 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nowrk, __func__); 4948 return (ENOMEM); 4949 } 4950 /* 4951 * NB: We use the PMCS_OQ_GENERAL outbound queue 4952 * NB: so as to not get entangled in normal I/O 4953 * NB: processing. 4954 */ 4955 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 4956 PMCIN_SSP_INI_TM_START)); 4957 msg[1] = LE_32(pwrk->htag); 4958 msg[2] = LE_32(pptr->device_id); 4959 if (tmf == SAS_ABORT_TASK || tmf == SAS_QUERY_TASK) { 4960 msg[3] = LE_32(tag); 4961 } else { 4962 msg[3] = 0; 4963 } 4964 msg[4] = LE_32(tmf); 4965 msg[5] = BE_32((uint32_t)lun); 4966 msg[6] = BE_32((uint32_t)(lun >> 32)); 4967 msg[7] = LE_32(PMCIN_MESSAGE_REPORT); 4968 4969 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4970 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4971 if (ptr == NULL) { 4972 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4973 pmcs_pwork(pwp, pwrk); 4974 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nomsg, __func__); 4975 return (ENOMEM); 4976 } 4977 COPY_MESSAGE(ptr, msg, 7); 4978 pwrk->arg = msg; 4979 pwrk->dtype = pptr->dtype; 4980 xp = pptr->target; 4981 pwrk->xp = xp; 4982 4983 if (xp != NULL) { 4984 mutex_enter(&xp->statlock); 4985 if (xp->dev_state == PMCS_DEVICE_STATE_NON_OPERATIONAL) { 4986 mutex_exit(&xp->statlock); 4987 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4988 pmcs_pwork(pwp, pwrk); 4989 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, "%s: Not " 4990 "sending '%s' because DS is '%s'", __func__, 4991 pmcs_tmf2str(tmf), pmcs_status_str 4992 (PMCOUT_STATUS_IO_DS_NON_OPERATIONAL)); 4993 return (EIO); 4994 } 4995 mutex_exit(&xp->statlock); 4996 } 4997 4998 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 4999 "%s: sending '%s' to %s (lun %llu) tag 0x%x", __func__, 5000 pmcs_tmf2str(tmf), pptr->path, (unsigned long long) lun, tag); 5001 pwrk->state = PMCS_WORK_STATE_ONCHIP; 5002 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5003 5004 pmcs_unlock_phy(pptr); 5005 /* 5006 * This is a command sent to the target device, so it can take 5007 * significant amount of time to complete when path & device is busy. 5008 * Set a timeout to 20 seconds 5009 */ 5010 WAIT_FOR(pwrk, 20000, result); 5011 pmcs_lock_phy(pptr); 5012 pmcs_pwork(pwp, pwrk); 5013 5014 if (result) { 5015 if (xp == NULL) { 5016 return (ETIMEDOUT); 5017 } 5018 5019 mutex_enter(&xp->statlock); 5020 pmcs_start_dev_state_recovery(xp, pptr); 5021 mutex_exit(&xp->statlock); 5022 return (ETIMEDOUT); 5023 } 5024 5025 status = LE_32(msg[2]); 5026 if (status != PMCOUT_STATUS_OK) { 5027 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5028 "%s: status %s for TMF %s action to %s, lun %llu", 5029 __func__, pmcs_status_str(status), pmcs_tmf2str(tmf), 5030 pptr->path, (unsigned long long) lun); 5031 if ((status == PMCOUT_STATUS_IO_DS_NON_OPERATIONAL) || 5032 (status == PMCOUT_STATUS_OPEN_CNX_ERROR_BREAK) || 5033 (status == PMCOUT_STATUS_OPEN_CNX_ERROR_IT_NEXUS_LOSS)) { 5034 ds = PMCS_DEVICE_STATE_NON_OPERATIONAL; 5035 } else if (status == PMCOUT_STATUS_IO_DS_IN_RECOVERY) { 5036 /* 5037 * If the status is IN_RECOVERY, it's an indication 5038 * that it's now time for us to request to have the 5039 * device state set to OPERATIONAL since we're the ones 5040 * that requested recovery to begin with. 5041 */ 5042 ds = PMCS_DEVICE_STATE_OPERATIONAL; 5043 } else { 5044 ds = PMCS_DEVICE_STATE_IN_RECOVERY; 5045 } 5046 if (xp != NULL) { 5047 mutex_enter(&xp->statlock); 5048 if (xp->dev_state != ds) { 5049 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5050 "%s: Sending err recovery cmd" 5051 " for tgt 0x%p (status = %s)", 5052 __func__, (void *)xp, 5053 pmcs_status_str(status)); 5054 (void) pmcs_send_err_recovery_cmd(pwp, ds, 5055 pptr, xp); 5056 } 5057 mutex_exit(&xp->statlock); 5058 } 5059 return (EIO); 5060 } else { 5061 ds = PMCS_DEVICE_STATE_OPERATIONAL; 5062 if (xp != NULL) { 5063 mutex_enter(&xp->statlock); 5064 if (xp->dev_state != ds) { 5065 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5066 "%s: Sending err recovery cmd" 5067 " for tgt 0x%p (status = %s)", 5068 __func__, (void *)xp, 5069 pmcs_status_str(status)); 5070 (void) pmcs_send_err_recovery_cmd(pwp, ds, 5071 pptr, xp); 5072 } 5073 mutex_exit(&xp->statlock); 5074 } 5075 } 5076 if (LE_32(msg[3]) == 0) { 5077 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5078 "TMF completed with no response"); 5079 return (EIO); 5080 } 5081 pmcs_endian_transform(pwp, local, &msg[5], ssp_rsp_evec); 5082 xd = (uint8_t *)(&msg[5]); 5083 xd += SAS_RSP_HDR_SIZE; 5084 if (rptr->datapres != SAS_RSP_DATAPRES_RESPONSE_DATA) { 5085 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5086 "%s: TMF response not RESPONSE DATA (0x%x)", 5087 __func__, rptr->datapres); 5088 return (EIO); 5089 } 5090 if (rptr->response_data_length != 4) { 5091 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, 5092 "Bad SAS RESPONSE DATA LENGTH", msg); 5093 return (EIO); 5094 } 5095 (void) memcpy(&status, xd, sizeof (uint32_t)); 5096 status = BE_32(status); 5097 if (response != NULL) 5098 *response = status; 5099 /* 5100 * The status is actually in the low-order byte. The upper three 5101 * bytes contain additional information for the TMFs that support them. 5102 * However, at this time we do not issue any of those. In the other 5103 * cases, the upper three bytes are supposed to be 0, but it appears 5104 * they aren't always. Just mask them off. 5105 */ 5106 switch (status & 0xff) { 5107 case SAS_RSP_TMF_COMPLETE: 5108 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5109 "%s: TMF complete", __func__); 5110 result = 0; 5111 break; 5112 case SAS_RSP_TMF_SUCCEEDED: 5113 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5114 "%s: TMF succeeded", __func__); 5115 result = 0; 5116 break; 5117 case SAS_RSP_INVALID_FRAME: 5118 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5119 "%s: TMF returned INVALID FRAME", __func__); 5120 result = EIO; 5121 break; 5122 case SAS_RSP_TMF_NOT_SUPPORTED: 5123 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5124 "%s: TMF returned TMF NOT SUPPORTED", __func__); 5125 result = EIO; 5126 break; 5127 case SAS_RSP_TMF_FAILED: 5128 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5129 "%s: TMF returned TMF FAILED", __func__); 5130 result = EIO; 5131 break; 5132 case SAS_RSP_TMF_INCORRECT_LUN: 5133 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5134 "%s: TMF returned INCORRECT LUN", __func__); 5135 result = EIO; 5136 break; 5137 case SAS_RSP_OVERLAPPED_OIPTTA: 5138 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5139 "%s: TMF returned OVERLAPPED INITIATOR PORT TRANSFER TAG " 5140 "ATTEMPTED", __func__); 5141 result = EIO; 5142 break; 5143 default: 5144 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5145 "%s: TMF returned unknown code 0x%x", __func__, status); 5146 result = EIO; 5147 break; 5148 } 5149 return (result); 5150 } 5151 5152 /* 5153 * Called with PHY lock held and scratch acquired 5154 */ 5155 int 5156 pmcs_sata_abort_ncq(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 5157 { 5158 const char *utag_fail_fmt = "%s: untagged NCQ command failure"; 5159 const char *tag_fail_fmt = "%s: NCQ command failure (tag 0x%x)"; 5160 uint32_t msg[PMCS_QENTRY_SIZE], *ptr, result, status; 5161 uint8_t *fp = pwp->scratch, ds; 5162 fis_t fis; 5163 pmcwork_t *pwrk; 5164 pmcs_xscsi_t *tgt; 5165 5166 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 5167 if (pwrk == NULL) { 5168 return (ENOMEM); 5169 } 5170 msg[0] = LE_32(PMCS_IOMB_IN_SAS(PMCS_OQ_IODONE, 5171 PMCIN_SATA_HOST_IO_START)); 5172 msg[1] = LE_32(pwrk->htag); 5173 msg[2] = LE_32(pptr->device_id); 5174 msg[3] = LE_32(512); 5175 msg[4] = LE_32(SATA_PROTOCOL_PIO | PMCIN_DATADIR_2_INI); 5176 msg[5] = LE_32((READ_LOG_EXT << 16) | (C_BIT << 8) | FIS_REG_H2DEV); 5177 msg[6] = LE_32(0x10); 5178 msg[8] = LE_32(1); 5179 msg[9] = 0; 5180 msg[10] = 0; 5181 msg[11] = 0; 5182 msg[12] = LE_32(DWORD0(pwp->scratch_dma)); 5183 msg[13] = LE_32(DWORD1(pwp->scratch_dma)); 5184 msg[14] = LE_32(512); 5185 msg[15] = 0; 5186 5187 pwrk->arg = msg; 5188 pwrk->dtype = pptr->dtype; 5189 5190 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5191 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5192 if (ptr == NULL) { 5193 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5194 pmcs_pwork(pwp, pwrk); 5195 return (ENOMEM); 5196 } 5197 COPY_MESSAGE(ptr, msg, PMCS_QENTRY_SIZE); 5198 pwrk->state = PMCS_WORK_STATE_ONCHIP; 5199 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5200 5201 pmcs_unlock_phy(pptr); 5202 WAIT_FOR(pwrk, 250, result); 5203 pmcs_lock_phy(pptr); 5204 pmcs_pwork(pwp, pwrk); 5205 5206 tgt = pptr->target; 5207 if (result) { 5208 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, pmcs_timeo, __func__); 5209 return (EIO); 5210 } 5211 status = LE_32(msg[2]); 5212 if (status != PMCOUT_STATUS_OK || LE_32(msg[3])) { 5213 if (tgt == NULL) { 5214 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 5215 "%s: cannot find target for phy 0x%p for " 5216 "dev state recovery", __func__, (void *)pptr); 5217 return (EIO); 5218 } 5219 5220 mutex_enter(&tgt->statlock); 5221 5222 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, "READ LOG EXT", msg); 5223 if ((status == PMCOUT_STATUS_IO_DS_NON_OPERATIONAL) || 5224 (status == PMCOUT_STATUS_OPEN_CNX_ERROR_BREAK) || 5225 (status == PMCOUT_STATUS_OPEN_CNX_ERROR_IT_NEXUS_LOSS)) { 5226 ds = PMCS_DEVICE_STATE_NON_OPERATIONAL; 5227 } else { 5228 ds = PMCS_DEVICE_STATE_IN_RECOVERY; 5229 } 5230 if (tgt->dev_state != ds) { 5231 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, "%s: Trying " 5232 "SATA DS Recovery for tgt(0x%p) for status(%s)", 5233 __func__, (void *)tgt, pmcs_status_str(status)); 5234 (void) pmcs_send_err_recovery_cmd(pwp, ds, pptr, tgt); 5235 } 5236 5237 mutex_exit(&tgt->statlock); 5238 return (EIO); 5239 } 5240 fis[0] = (fp[4] << 24) | (fp[3] << 16) | (fp[2] << 8) | FIS_REG_D2H; 5241 fis[1] = (fp[8] << 24) | (fp[7] << 16) | (fp[6] << 8) | fp[5]; 5242 fis[2] = (fp[12] << 24) | (fp[11] << 16) | (fp[10] << 8) | fp[9]; 5243 fis[3] = (fp[16] << 24) | (fp[15] << 16) | (fp[14] << 8) | fp[13]; 5244 fis[4] = 0; 5245 if (fp[0] & 0x80) { 5246 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 5247 utag_fail_fmt, __func__); 5248 } else { 5249 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 5250 tag_fail_fmt, __func__, fp[0] & 0x1f); 5251 } 5252 pmcs_fis_dump(pwp, fis); 5253 pptr->need_rl_ext = 0; 5254 return (0); 5255 } 5256 5257 /* 5258 * Transform a structure from CPU to Device endian format, or 5259 * vice versa, based upon a transformation vector. 5260 * 5261 * A transformation vector is an array of bytes, each byte 5262 * of which is defined thusly: 5263 * 5264 * bit 7: from CPU to desired endian, otherwise from desired endian 5265 * to CPU format 5266 * bit 6: Big Endian, else Little Endian 5267 * bits 5-4: 5268 * 00 Undefined 5269 * 01 One Byte quantities 5270 * 02 Two Byte quantities 5271 * 03 Four Byte quantities 5272 * 5273 * bits 3-0: 5274 * 00 Undefined 5275 * Number of quantities to transform 5276 * 5277 * The vector is terminated by a 0 value. 5278 */ 5279 5280 void 5281 pmcs_endian_transform(pmcs_hw_t *pwp, void *orig_out, void *orig_in, 5282 const uint8_t *xfvec) 5283 { 5284 uint8_t c, *out = orig_out, *in = orig_in; 5285 5286 if (xfvec == NULL) { 5287 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 5288 "%s: null xfvec", __func__); 5289 return; 5290 } 5291 if (out == NULL) { 5292 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 5293 "%s: null out", __func__); 5294 return; 5295 } 5296 if (in == NULL) { 5297 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 5298 "%s: null in", __func__); 5299 return; 5300 } 5301 while ((c = *xfvec++) != 0) { 5302 int nbyt = (c & 0xf); 5303 int size = (c >> 4) & 0x3; 5304 int bige = (c >> 4) & 0x4; 5305 5306 switch (size) { 5307 case 1: 5308 { 5309 while (nbyt-- > 0) { 5310 *out++ = *in++; 5311 } 5312 break; 5313 } 5314 case 2: 5315 { 5316 uint16_t tmp; 5317 while (nbyt-- > 0) { 5318 (void) memcpy(&tmp, in, sizeof (uint16_t)); 5319 if (bige) { 5320 tmp = BE_16(tmp); 5321 } else { 5322 tmp = LE_16(tmp); 5323 } 5324 (void) memcpy(out, &tmp, sizeof (uint16_t)); 5325 out += sizeof (uint16_t); 5326 in += sizeof (uint16_t); 5327 } 5328 break; 5329 } 5330 case 3: 5331 { 5332 uint32_t tmp; 5333 while (nbyt-- > 0) { 5334 (void) memcpy(&tmp, in, sizeof (uint32_t)); 5335 if (bige) { 5336 tmp = BE_32(tmp); 5337 } else { 5338 tmp = LE_32(tmp); 5339 } 5340 (void) memcpy(out, &tmp, sizeof (uint32_t)); 5341 out += sizeof (uint32_t); 5342 in += sizeof (uint32_t); 5343 } 5344 break; 5345 } 5346 default: 5347 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 5348 "%s: bad size", __func__); 5349 return; 5350 } 5351 } 5352 } 5353 5354 const char * 5355 pmcs_get_rate(unsigned int linkrt) 5356 { 5357 const char *rate; 5358 switch (linkrt) { 5359 case SAS_LINK_RATE_1_5GBIT: 5360 rate = "1.5"; 5361 break; 5362 case SAS_LINK_RATE_3GBIT: 5363 rate = "3.0"; 5364 break; 5365 case SAS_LINK_RATE_6GBIT: 5366 rate = "6.0"; 5367 break; 5368 default: 5369 rate = "???"; 5370 break; 5371 } 5372 return (rate); 5373 } 5374 5375 const char * 5376 pmcs_get_typename(pmcs_dtype_t type) 5377 { 5378 switch (type) { 5379 case NOTHING: 5380 return ("NIL"); 5381 case SATA: 5382 return ("SATA"); 5383 case SAS: 5384 return ("SSP"); 5385 case EXPANDER: 5386 return ("EXPANDER"); 5387 } 5388 return ("????"); 5389 } 5390 5391 const char * 5392 pmcs_tmf2str(int tmf) 5393 { 5394 switch (tmf) { 5395 case SAS_ABORT_TASK: 5396 return ("Abort Task"); 5397 case SAS_ABORT_TASK_SET: 5398 return ("Abort Task Set"); 5399 case SAS_CLEAR_TASK_SET: 5400 return ("Clear Task Set"); 5401 case SAS_LOGICAL_UNIT_RESET: 5402 return ("Logical Unit Reset"); 5403 case SAS_I_T_NEXUS_RESET: 5404 return ("I_T Nexus Reset"); 5405 case SAS_CLEAR_ACA: 5406 return ("Clear ACA"); 5407 case SAS_QUERY_TASK: 5408 return ("Query Task"); 5409 case SAS_QUERY_TASK_SET: 5410 return ("Query Task Set"); 5411 case SAS_QUERY_UNIT_ATTENTION: 5412 return ("Query Unit Attention"); 5413 default: 5414 return ("Unknown"); 5415 } 5416 } 5417 5418 const char * 5419 pmcs_status_str(uint32_t status) 5420 { 5421 switch (status) { 5422 case PMCOUT_STATUS_OK: 5423 return ("OK"); 5424 case PMCOUT_STATUS_ABORTED: 5425 return ("ABORTED"); 5426 case PMCOUT_STATUS_OVERFLOW: 5427 return ("OVERFLOW"); 5428 case PMCOUT_STATUS_UNDERFLOW: 5429 return ("UNDERFLOW"); 5430 case PMCOUT_STATUS_FAILED: 5431 return ("FAILED"); 5432 case PMCOUT_STATUS_ABORT_RESET: 5433 return ("ABORT_RESET"); 5434 case PMCOUT_STATUS_IO_NOT_VALID: 5435 return ("IO_NOT_VALID"); 5436 case PMCOUT_STATUS_NO_DEVICE: 5437 return ("NO_DEVICE"); 5438 case PMCOUT_STATUS_ILLEGAL_PARAMETER: 5439 return ("ILLEGAL_PARAMETER"); 5440 case PMCOUT_STATUS_LINK_FAILURE: 5441 return ("LINK_FAILURE"); 5442 case PMCOUT_STATUS_PROG_ERROR: 5443 return ("PROG_ERROR"); 5444 case PMCOUT_STATUS_EDC_IN_ERROR: 5445 return ("EDC_IN_ERROR"); 5446 case PMCOUT_STATUS_EDC_OUT_ERROR: 5447 return ("EDC_OUT_ERROR"); 5448 case PMCOUT_STATUS_ERROR_HW_TIMEOUT: 5449 return ("ERROR_HW_TIMEOUT"); 5450 case PMCOUT_STATUS_XFER_ERR_BREAK: 5451 return ("XFER_ERR_BREAK"); 5452 case PMCOUT_STATUS_XFER_ERR_PHY_NOT_READY: 5453 return ("XFER_ERR_PHY_NOT_READY"); 5454 case PMCOUT_STATUS_OPEN_CNX_PROTOCOL_NOT_SUPPORTED: 5455 return ("OPEN_CNX_PROTOCOL_NOT_SUPPORTED"); 5456 case PMCOUT_STATUS_OPEN_CNX_ERROR_ZONE_VIOLATION: 5457 return ("OPEN_CNX_ERROR_ZONE_VIOLATION"); 5458 case PMCOUT_STATUS_OPEN_CNX_ERROR_BREAK: 5459 return ("OPEN_CNX_ERROR_BREAK"); 5460 case PMCOUT_STATUS_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 5461 return ("OPEN_CNX_ERROR_IT_NEXUS_LOSS"); 5462 case PMCOUT_STATUS_OPENCNX_ERROR_BAD_DESTINATION: 5463 return ("OPENCNX_ERROR_BAD_DESTINATION"); 5464 case PMCOUT_STATUS_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 5465 return ("OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED"); 5466 case PMCOUT_STATUS_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 5467 return ("OPEN_CNX_ERROR_STP_RESOURCES_BUSY"); 5468 case PMCOUT_STATUS_OPEN_CNX_ERROR_WRONG_DESTINATION: 5469 return ("OPEN_CNX_ERROR_WRONG_DESTINATION"); 5470 case PMCOUT_STATUS_OPEN_CNX_ERROR_UNKNOWN_ERROR: 5471 return ("OPEN_CNX_ERROR_UNKNOWN_ERROR"); 5472 case PMCOUT_STATUS_IO_XFER_ERROR_NAK_RECEIVED: 5473 return ("IO_XFER_ERROR_NAK_RECEIVED"); 5474 case PMCOUT_STATUS_XFER_ERROR_ACK_NAK_TIMEOUT: 5475 return ("XFER_ERROR_ACK_NAK_TIMEOUT"); 5476 case PMCOUT_STATUS_XFER_ERROR_PEER_ABORTED: 5477 return ("XFER_ERROR_PEER_ABORTED"); 5478 case PMCOUT_STATUS_XFER_ERROR_RX_FRAME: 5479 return ("XFER_ERROR_RX_FRAME"); 5480 case PMCOUT_STATUS_IO_XFER_ERROR_DMA: 5481 return ("IO_XFER_ERROR_DMA"); 5482 case PMCOUT_STATUS_XFER_ERROR_CREDIT_TIMEOUT: 5483 return ("XFER_ERROR_CREDIT_TIMEOUT"); 5484 case PMCOUT_STATUS_XFER_ERROR_SATA_LINK_TIMEOUT: 5485 return ("XFER_ERROR_SATA_LINK_TIMEOUT"); 5486 case PMCOUT_STATUS_XFER_ERROR_SATA: 5487 return ("XFER_ERROR_SATA"); 5488 case PMCOUT_STATUS_XFER_ERROR_REJECTED_NCQ_MODE: 5489 return ("XFER_ERROR_REJECTED_NCQ_MODE"); 5490 case PMCOUT_STATUS_XFER_ERROR_ABORTED_DUE_TO_SRST: 5491 return ("XFER_ERROR_ABORTED_DUE_TO_SRST"); 5492 case PMCOUT_STATUS_XFER_ERROR_ABORTED_NCQ_MODE: 5493 return ("XFER_ERROR_ABORTED_NCQ_MODE"); 5494 case PMCOUT_STATUS_IO_XFER_OPEN_RETRY_TIMEOUT: 5495 return ("IO_XFER_OPEN_RETRY_TIMEOUT"); 5496 case PMCOUT_STATUS_SMP_RESP_CONNECTION_ERROR: 5497 return ("SMP_RESP_CONNECTION_ERROR"); 5498 case PMCOUT_STATUS_XFER_ERROR_UNEXPECTED_PHASE: 5499 return ("XFER_ERROR_UNEXPECTED_PHASE"); 5500 case PMCOUT_STATUS_XFER_ERROR_RDY_OVERRUN: 5501 return ("XFER_ERROR_RDY_OVERRUN"); 5502 case PMCOUT_STATUS_XFER_ERROR_RDY_NOT_EXPECTED: 5503 return ("XFER_ERROR_RDY_NOT_EXPECTED"); 5504 case PMCOUT_STATUS_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 5505 return ("XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT"); 5506 case PMCOUT_STATUS_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NACK: 5507 return ("XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NACK"); 5508 case PMCOUT_STATUS_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK: 5509 return ("XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK"); 5510 case PMCOUT_STATUS_XFER_ERROR_OFFSET_MISMATCH: 5511 return ("XFER_ERROR_OFFSET_MISMATCH"); 5512 case PMCOUT_STATUS_XFER_ERROR_ZERO_DATA_LEN: 5513 return ("XFER_ERROR_ZERO_DATA_LEN"); 5514 case PMCOUT_STATUS_XFER_CMD_FRAME_ISSUED: 5515 return ("XFER_CMD_FRAME_ISSUED"); 5516 case PMCOUT_STATUS_ERROR_INTERNAL_SMP_RESOURCE: 5517 return ("ERROR_INTERNAL_SMP_RESOURCE"); 5518 case PMCOUT_STATUS_IO_PORT_IN_RESET: 5519 return ("IO_PORT_IN_RESET"); 5520 case PMCOUT_STATUS_IO_DS_NON_OPERATIONAL: 5521 return ("DEVICE STATE NON-OPERATIONAL"); 5522 case PMCOUT_STATUS_IO_DS_IN_RECOVERY: 5523 return ("DEVICE STATE IN RECOVERY"); 5524 default: 5525 return (NULL); 5526 } 5527 } 5528 5529 uint64_t 5530 pmcs_barray2wwn(uint8_t ba[8]) 5531 { 5532 uint64_t result = 0; 5533 int i; 5534 5535 for (i = 0; i < 8; i++) { 5536 result <<= 8; 5537 result |= ba[i]; 5538 } 5539 return (result); 5540 } 5541 5542 void 5543 pmcs_wwn2barray(uint64_t wwn, uint8_t ba[8]) 5544 { 5545 int i; 5546 for (i = 0; i < 8; i++) { 5547 ba[7 - i] = wwn & 0xff; 5548 wwn >>= 8; 5549 } 5550 } 5551 5552 void 5553 pmcs_report_fwversion(pmcs_hw_t *pwp) 5554 { 5555 const char *fwsupport; 5556 switch (PMCS_FW_TYPE(pwp)) { 5557 case PMCS_FW_TYPE_RELEASED: 5558 fwsupport = "Released"; 5559 break; 5560 case PMCS_FW_TYPE_DEVELOPMENT: 5561 fwsupport = "Development"; 5562 break; 5563 case PMCS_FW_TYPE_ALPHA: 5564 fwsupport = "Alpha"; 5565 break; 5566 case PMCS_FW_TYPE_BETA: 5567 fwsupport = "Beta"; 5568 break; 5569 default: 5570 fwsupport = "Special"; 5571 break; 5572 } 5573 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 5574 "Chip Revision: %c; F/W Revision %x.%x.%x %s", 'A' + pwp->chiprev, 5575 PMCS_FW_MAJOR(pwp), PMCS_FW_MINOR(pwp), PMCS_FW_MICRO(pwp), 5576 fwsupport); 5577 } 5578 5579 void 5580 pmcs_phy_name(pmcs_hw_t *pwp, pmcs_phy_t *pptr, char *obuf, size_t olen) 5581 { 5582 if (pptr->parent) { 5583 pmcs_phy_name(pwp, pptr->parent, obuf, olen); 5584 (void) snprintf(obuf, olen, "%s.%02x", obuf, pptr->phynum); 5585 } else { 5586 (void) snprintf(obuf, olen, "pp%02x", pptr->phynum); 5587 } 5588 } 5589 5590 /* 5591 * Implementation for pmcs_find_phy_by_devid. 5592 * If the PHY is found, it is returned locked. 5593 */ 5594 static pmcs_phy_t * 5595 pmcs_find_phy_by_devid_impl(pmcs_phy_t *phyp, uint32_t device_id) 5596 { 5597 pmcs_phy_t *match, *cphyp, *nphyp; 5598 5599 ASSERT(!mutex_owned(&phyp->phy_lock)); 5600 5601 while (phyp) { 5602 pmcs_lock_phy(phyp); 5603 5604 if ((phyp->valid_device_id) && (phyp->device_id == device_id)) { 5605 return (phyp); 5606 } 5607 if (phyp->children) { 5608 cphyp = phyp->children; 5609 pmcs_unlock_phy(phyp); 5610 match = pmcs_find_phy_by_devid_impl(cphyp, device_id); 5611 if (match) { 5612 ASSERT(mutex_owned(&match->phy_lock)); 5613 return (match); 5614 } 5615 pmcs_lock_phy(phyp); 5616 } 5617 5618 if (IS_ROOT_PHY(phyp)) { 5619 pmcs_unlock_phy(phyp); 5620 phyp = NULL; 5621 } else { 5622 nphyp = phyp->sibling; 5623 pmcs_unlock_phy(phyp); 5624 phyp = nphyp; 5625 } 5626 } 5627 5628 return (NULL); 5629 } 5630 5631 /* 5632 * If the PHY is found, it is returned locked 5633 */ 5634 pmcs_phy_t * 5635 pmcs_find_phy_by_devid(pmcs_hw_t *pwp, uint32_t device_id) 5636 { 5637 pmcs_phy_t *phyp, *match = NULL; 5638 5639 phyp = pwp->root_phys; 5640 5641 while (phyp) { 5642 match = pmcs_find_phy_by_devid_impl(phyp, device_id); 5643 if (match) { 5644 ASSERT(mutex_owned(&match->phy_lock)); 5645 return (match); 5646 } 5647 phyp = phyp->sibling; 5648 } 5649 5650 return (NULL); 5651 } 5652 5653 /* 5654 * This function is called as a sanity check to ensure that a newly registered 5655 * PHY doesn't have a device_id that exists with another registered PHY. 5656 */ 5657 static boolean_t 5658 pmcs_validate_devid(pmcs_phy_t *parent, pmcs_phy_t *phyp, uint32_t device_id) 5659 { 5660 pmcs_phy_t *pptr, *pchild; 5661 boolean_t rval; 5662 5663 pptr = parent; 5664 5665 while (pptr) { 5666 if (pptr->valid_device_id && (pptr != phyp) && 5667 (pptr->device_id == device_id)) { 5668 /* 5669 * This can still be OK if both of these PHYs actually 5670 * represent the same device (e.g. expander). It could 5671 * be a case of a new "primary" PHY. If the SAS address 5672 * is the same and they have the same parent, we'll 5673 * accept this if the PHY to be registered is the 5674 * primary. 5675 */ 5676 if ((phyp->parent == pptr->parent) && 5677 (memcmp(phyp->sas_address, 5678 pptr->sas_address, 8) == 0) && (phyp->width > 1)) { 5679 /* 5680 * Move children over to the new primary and 5681 * update both PHYs 5682 */ 5683 pmcs_lock_phy(pptr); 5684 phyp->children = pptr->children; 5685 pchild = phyp->children; 5686 while (pchild) { 5687 pchild->parent = phyp; 5688 pchild = pchild->sibling; 5689 } 5690 phyp->subsidiary = 0; 5691 phyp->ncphy = pptr->ncphy; 5692 /* 5693 * device_id, valid_device_id, and configured 5694 * will be set by the caller 5695 */ 5696 pptr->children = NULL; 5697 pptr->subsidiary = 1; 5698 pptr->ncphy = 0; 5699 pmcs_unlock_phy(pptr); 5700 pmcs_prt(pptr->pwp, PMCS_PRT_DEBUG, pptr, NULL, 5701 "%s: Moving device_id %d from PHY %s to %s", 5702 __func__, device_id, pptr->path, 5703 phyp->path); 5704 return (B_TRUE); 5705 } 5706 pmcs_prt(pptr->pwp, PMCS_PRT_DEBUG, pptr, NULL, 5707 "%s: phy %s already exists as %s with " 5708 "device id 0x%x", __func__, phyp->path, 5709 pptr->path, device_id); 5710 return (B_FALSE); 5711 } 5712 5713 if (pptr->children) { 5714 rval = pmcs_validate_devid(pptr->children, phyp, 5715 device_id); 5716 if (rval == B_FALSE) { 5717 return (rval); 5718 } 5719 } 5720 5721 pptr = pptr->sibling; 5722 } 5723 5724 /* This PHY and device_id are valid */ 5725 return (B_TRUE); 5726 } 5727 5728 /* 5729 * If the PHY is found, it is returned locked 5730 */ 5731 static pmcs_phy_t * 5732 pmcs_find_phy_by_wwn_impl(pmcs_phy_t *phyp, uint8_t *wwn) 5733 { 5734 pmcs_phy_t *matched_phy, *cphyp, *nphyp; 5735 5736 ASSERT(!mutex_owned(&phyp->phy_lock)); 5737 5738 while (phyp) { 5739 pmcs_lock_phy(phyp); 5740 5741 if (phyp->valid_device_id) { 5742 if (memcmp(phyp->sas_address, wwn, 8) == 0) { 5743 return (phyp); 5744 } 5745 } 5746 5747 if (phyp->children) { 5748 cphyp = phyp->children; 5749 pmcs_unlock_phy(phyp); 5750 matched_phy = pmcs_find_phy_by_wwn_impl(cphyp, wwn); 5751 if (matched_phy) { 5752 ASSERT(mutex_owned(&matched_phy->phy_lock)); 5753 return (matched_phy); 5754 } 5755 pmcs_lock_phy(phyp); 5756 } 5757 5758 /* 5759 * Only iterate through non-root PHYs 5760 */ 5761 if (IS_ROOT_PHY(phyp)) { 5762 pmcs_unlock_phy(phyp); 5763 phyp = NULL; 5764 } else { 5765 nphyp = phyp->sibling; 5766 pmcs_unlock_phy(phyp); 5767 phyp = nphyp; 5768 } 5769 } 5770 5771 return (NULL); 5772 } 5773 5774 pmcs_phy_t * 5775 pmcs_find_phy_by_wwn(pmcs_hw_t *pwp, uint64_t wwn) 5776 { 5777 uint8_t ebstr[8]; 5778 pmcs_phy_t *pptr, *matched_phy; 5779 5780 pmcs_wwn2barray(wwn, ebstr); 5781 5782 pptr = pwp->root_phys; 5783 while (pptr) { 5784 matched_phy = pmcs_find_phy_by_wwn_impl(pptr, ebstr); 5785 if (matched_phy) { 5786 ASSERT(mutex_owned(&matched_phy->phy_lock)); 5787 return (matched_phy); 5788 } 5789 5790 pptr = pptr->sibling; 5791 } 5792 5793 return (NULL); 5794 } 5795 5796 5797 /* 5798 * pmcs_find_phy_by_sas_address 5799 * 5800 * Find a PHY that both matches "sas_addr" and is on "iport". 5801 * If a matching PHY is found, it is returned locked. 5802 */ 5803 pmcs_phy_t * 5804 pmcs_find_phy_by_sas_address(pmcs_hw_t *pwp, pmcs_iport_t *iport, 5805 pmcs_phy_t *root, char *sas_addr) 5806 { 5807 int ua_form = 1; 5808 uint64_t wwn; 5809 char addr[PMCS_MAX_UA_SIZE]; 5810 pmcs_phy_t *pptr, *pnext, *pchild; 5811 5812 if (root == NULL) { 5813 pptr = pwp->root_phys; 5814 } else { 5815 pptr = root; 5816 } 5817 5818 while (pptr) { 5819 pmcs_lock_phy(pptr); 5820 /* 5821 * If the PHY is dead or does not have a valid device ID, 5822 * skip it. 5823 */ 5824 if ((pptr->dead) || (!pptr->valid_device_id)) { 5825 goto next_phy; 5826 } 5827 5828 if (pptr->iport != iport) { 5829 goto next_phy; 5830 } 5831 5832 wwn = pmcs_barray2wwn(pptr->sas_address); 5833 (void *) scsi_wwn_to_wwnstr(wwn, ua_form, addr); 5834 if (strncmp(addr, sas_addr, strlen(addr)) == 0) { 5835 return (pptr); 5836 } 5837 5838 if (pptr->children) { 5839 pchild = pptr->children; 5840 pmcs_unlock_phy(pptr); 5841 pnext = pmcs_find_phy_by_sas_address(pwp, iport, pchild, 5842 sas_addr); 5843 if (pnext) { 5844 return (pnext); 5845 } 5846 pmcs_lock_phy(pptr); 5847 } 5848 5849 next_phy: 5850 pnext = pptr->sibling; 5851 pmcs_unlock_phy(pptr); 5852 pptr = pnext; 5853 } 5854 5855 return (NULL); 5856 } 5857 5858 void 5859 pmcs_fis_dump(pmcs_hw_t *pwp, fis_t fis) 5860 { 5861 switch (fis[0] & 0xff) { 5862 case FIS_REG_H2DEV: 5863 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 5864 "FIS REGISTER HOST TO DEVICE: " 5865 "OP=0x%02x Feature=0x%04x Count=0x%04x Device=0x%02x " 5866 "LBA=%llu", BYTE2(fis[0]), BYTE3(fis[2]) << 8 | 5867 BYTE3(fis[0]), WORD0(fis[3]), BYTE3(fis[1]), 5868 (unsigned long long) 5869 (((uint64_t)fis[2] & 0x00ffffff) << 24 | 5870 ((uint64_t)fis[1] & 0x00ffffff))); 5871 break; 5872 case FIS_REG_D2H: 5873 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 5874 "FIS REGISTER DEVICE TO HOST: Status=0x%02x " 5875 "Error=0x%02x Dev=0x%02x Count=0x%04x LBA=%llu", 5876 BYTE2(fis[0]), BYTE3(fis[0]), BYTE3(fis[1]), WORD0(fis[3]), 5877 (unsigned long long)(((uint64_t)fis[2] & 0x00ffffff) << 24 | 5878 ((uint64_t)fis[1] & 0x00ffffff))); 5879 break; 5880 default: 5881 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 5882 "FIS: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", 5883 fis[0], fis[1], fis[2], fis[3], fis[4], fis[5], fis[6]); 5884 break; 5885 } 5886 } 5887 5888 void 5889 pmcs_print_entry(pmcs_hw_t *pwp, int level, char *msg, void *arg) 5890 { 5891 uint32_t *mb = arg; 5892 size_t i; 5893 5894 pmcs_prt(pwp, level, NULL, NULL, msg); 5895 for (i = 0; i < (PMCS_QENTRY_SIZE / sizeof (uint32_t)); i += 4) { 5896 pmcs_prt(pwp, level, NULL, NULL, 5897 "Offset %2lu: 0x%08x 0x%08x 0x%08x 0x%08x", 5898 i * sizeof (uint32_t), LE_32(mb[i]), 5899 LE_32(mb[i+1]), LE_32(mb[i+2]), LE_32(mb[i+3])); 5900 } 5901 } 5902 5903 /* 5904 * If phyp == NULL we're being called from the worker thread, in which 5905 * case we need to check all the PHYs. In this case, the softstate lock 5906 * will be held. 5907 * If phyp is non-NULL, just issue the spinup release for the specified PHY 5908 * (which will already be locked). 5909 */ 5910 void 5911 pmcs_spinup_release(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 5912 { 5913 uint32_t *msg; 5914 struct pmcwork *pwrk; 5915 pmcs_phy_t *tphyp; 5916 5917 if (phyp != NULL) { 5918 ASSERT(mutex_owned(&phyp->phy_lock)); 5919 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, phyp, NULL, 5920 "%s: Issuing spinup release only for PHY %s", __func__, 5921 phyp->path); 5922 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5923 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5924 if (msg == NULL || (pwrk = 5925 pmcs_gwork(pwp, PMCS_TAG_TYPE_NONE, NULL)) == NULL) { 5926 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5927 SCHEDULE_WORK(pwp, PMCS_WORK_SPINUP_RELEASE); 5928 return; 5929 } 5930 5931 phyp->spinup_hold = 0; 5932 bzero(msg, PMCS_QENTRY_SIZE); 5933 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 5934 PMCIN_LOCAL_PHY_CONTROL)); 5935 msg[1] = LE_32(pwrk->htag); 5936 msg[2] = LE_32((0x10 << 8) | phyp->phynum); 5937 5938 pwrk->dtype = phyp->dtype; 5939 pwrk->state = PMCS_WORK_STATE_ONCHIP; 5940 mutex_exit(&pwrk->lock); 5941 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5942 return; 5943 } 5944 5945 ASSERT(mutex_owned(&pwp->lock)); 5946 5947 tphyp = pwp->root_phys; 5948 while (tphyp) { 5949 pmcs_lock_phy(tphyp); 5950 if (tphyp->spinup_hold == 0) { 5951 pmcs_unlock_phy(tphyp); 5952 tphyp = tphyp->sibling; 5953 continue; 5954 } 5955 5956 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, phyp, NULL, 5957 "%s: Issuing spinup release for PHY %s", __func__, 5958 phyp->path); 5959 5960 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5961 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5962 if (msg == NULL || (pwrk = 5963 pmcs_gwork(pwp, PMCS_TAG_TYPE_NONE, NULL)) == NULL) { 5964 pmcs_unlock_phy(tphyp); 5965 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5966 SCHEDULE_WORK(pwp, PMCS_WORK_SPINUP_RELEASE); 5967 break; 5968 } 5969 5970 tphyp->spinup_hold = 0; 5971 bzero(msg, PMCS_QENTRY_SIZE); 5972 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 5973 PMCIN_LOCAL_PHY_CONTROL)); 5974 msg[1] = LE_32(pwrk->htag); 5975 msg[2] = LE_32((0x10 << 8) | tphyp->phynum); 5976 5977 pwrk->dtype = phyp->dtype; 5978 pwrk->state = PMCS_WORK_STATE_ONCHIP; 5979 mutex_exit(&pwrk->lock); 5980 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5981 pmcs_unlock_phy(tphyp); 5982 5983 tphyp = tphyp->sibling; 5984 } 5985 } 5986 5987 /* 5988 * Abort commands on dead PHYs and deregister them as well as removing 5989 * the associated targets. 5990 */ 5991 static int 5992 pmcs_kill_devices(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 5993 { 5994 pmcs_phy_t *pnext, *pchild; 5995 boolean_t remove_device; 5996 int rval = 0; 5997 5998 while (phyp) { 5999 pmcs_lock_phy(phyp); 6000 pchild = phyp->children; 6001 pnext = phyp->sibling; 6002 pmcs_unlock_phy(phyp); 6003 6004 if (pchild) { 6005 rval = pmcs_kill_devices(pwp, pchild); 6006 if (rval) { 6007 return (rval); 6008 } 6009 } 6010 6011 /* 6012 * pmcs_remove_device requires the softstate lock. 6013 */ 6014 mutex_enter(&pwp->lock); 6015 pmcs_lock_phy(phyp); 6016 if (phyp->dead && phyp->valid_device_id) { 6017 remove_device = B_TRUE; 6018 } else { 6019 remove_device = B_FALSE; 6020 } 6021 6022 if (remove_device) { 6023 pmcs_remove_device(pwp, phyp); 6024 mutex_exit(&pwp->lock); 6025 6026 rval = pmcs_kill_device(pwp, phyp); 6027 6028 if (rval) { 6029 pmcs_unlock_phy(phyp); 6030 return (rval); 6031 } 6032 } else { 6033 mutex_exit(&pwp->lock); 6034 } 6035 6036 pmcs_unlock_phy(phyp); 6037 phyp = pnext; 6038 } 6039 6040 return (rval); 6041 } 6042 6043 /* 6044 * Called with PHY locked 6045 */ 6046 int 6047 pmcs_kill_device(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 6048 { 6049 int r, result; 6050 uint32_t msg[PMCS_MSG_SIZE], *ptr, status; 6051 struct pmcwork *pwrk; 6052 6053 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, "kill %s device @ %s", 6054 pmcs_get_typename(pptr->dtype), pptr->path); 6055 6056 /* 6057 * There may be an outstanding ABORT_ALL running, which we wouldn't 6058 * know just by checking abort_pending. We can, however, check 6059 * abort_all_start. If it's non-zero, there is one, and we'll just 6060 * sit here and wait for it to complete. If we don't, we'll remove 6061 * the device while there are still commands pending. 6062 */ 6063 if (pptr->abort_all_start) { 6064 while (pptr->abort_all_start) { 6065 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 6066 "%s: Waiting for outstanding ABORT_ALL on PHY 0x%p", 6067 __func__, (void *)pptr); 6068 cv_wait(&pptr->abort_all_cv, &pptr->phy_lock); 6069 } 6070 } else if (pptr->abort_pending) { 6071 r = pmcs_abort(pwp, pptr, pptr->device_id, 1, 1); 6072 6073 if (r) { 6074 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 6075 "%s: ABORT_ALL returned non-zero status (%d) for " 6076 "PHY 0x%p", __func__, r, (void *)pptr); 6077 return (r); 6078 } 6079 pptr->abort_pending = 0; 6080 } 6081 6082 if (pptr->valid_device_id == 0) { 6083 return (0); 6084 } 6085 6086 if ((pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr)) == NULL) { 6087 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nowrk, __func__); 6088 return (ENOMEM); 6089 } 6090 pwrk->arg = msg; 6091 pwrk->dtype = pptr->dtype; 6092 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 6093 PMCIN_DEREGISTER_DEVICE_HANDLE)); 6094 msg[1] = LE_32(pwrk->htag); 6095 msg[2] = LE_32(pptr->device_id); 6096 6097 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 6098 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 6099 if (ptr == NULL) { 6100 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 6101 mutex_exit(&pwrk->lock); 6102 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nomsg, __func__); 6103 return (ENOMEM); 6104 } 6105 6106 COPY_MESSAGE(ptr, msg, 3); 6107 pwrk->state = PMCS_WORK_STATE_ONCHIP; 6108 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 6109 6110 pmcs_unlock_phy(pptr); 6111 WAIT_FOR(pwrk, 250, result); 6112 pmcs_lock_phy(pptr); 6113 pmcs_pwork(pwp, pwrk); 6114 6115 if (result) { 6116 return (ETIMEDOUT); 6117 } 6118 status = LE_32(msg[2]); 6119 if (status != PMCOUT_STATUS_OK) { 6120 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 6121 "%s: status 0x%x when trying to deregister device %s", 6122 __func__, status, pptr->path); 6123 } 6124 6125 pptr->device_id = PMCS_INVALID_DEVICE_ID; 6126 PHY_CHANGED(pwp, pptr); 6127 RESTART_DISCOVERY(pwp); 6128 pptr->valid_device_id = 0; 6129 return (0); 6130 } 6131 6132 /* 6133 * Acknowledge the SAS h/w events that need acknowledgement. 6134 * This is only needed for first level PHYs. 6135 */ 6136 void 6137 pmcs_ack_events(pmcs_hw_t *pwp) 6138 { 6139 uint32_t msg[PMCS_MSG_SIZE], *ptr; 6140 struct pmcwork *pwrk; 6141 pmcs_phy_t *pptr; 6142 6143 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 6144 pmcs_lock_phy(pptr); 6145 if (pptr->hw_event_ack == 0) { 6146 pmcs_unlock_phy(pptr); 6147 continue; 6148 } 6149 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 6150 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 6151 6152 if ((ptr == NULL) || (pwrk = 6153 pmcs_gwork(pwp, PMCS_TAG_TYPE_NONE, NULL)) == NULL) { 6154 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 6155 pmcs_unlock_phy(pptr); 6156 SCHEDULE_WORK(pwp, PMCS_WORK_SAS_HW_ACK); 6157 break; 6158 } 6159 6160 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 6161 PMCIN_SAW_HW_EVENT_ACK)); 6162 msg[1] = LE_32(pwrk->htag); 6163 msg[2] = LE_32(pptr->hw_event_ack); 6164 6165 mutex_exit(&pwrk->lock); 6166 pwrk->dtype = pptr->dtype; 6167 pptr->hw_event_ack = 0; 6168 COPY_MESSAGE(ptr, msg, 3); 6169 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 6170 pmcs_unlock_phy(pptr); 6171 } 6172 } 6173 6174 /* 6175 * Load DMA 6176 */ 6177 int 6178 pmcs_dma_load(pmcs_hw_t *pwp, pmcs_cmd_t *sp, uint32_t *msg) 6179 { 6180 ddi_dma_cookie_t *sg; 6181 pmcs_dmachunk_t *tc; 6182 pmcs_dmasgl_t *sgl, *prior; 6183 int seg, tsc; 6184 uint64_t sgl_addr; 6185 6186 /* 6187 * If we have no data segments, we're done. 6188 */ 6189 if (CMD2PKT(sp)->pkt_numcookies == 0) { 6190 return (0); 6191 } 6192 6193 /* 6194 * Get the S/G list pointer. 6195 */ 6196 sg = CMD2PKT(sp)->pkt_cookies; 6197 6198 /* 6199 * If we only have one dma segment, we can directly address that 6200 * data within the Inbound message itself. 6201 */ 6202 if (CMD2PKT(sp)->pkt_numcookies == 1) { 6203 msg[12] = LE_32(DWORD0(sg->dmac_laddress)); 6204 msg[13] = LE_32(DWORD1(sg->dmac_laddress)); 6205 msg[14] = LE_32(sg->dmac_size); 6206 msg[15] = 0; 6207 return (0); 6208 } 6209 6210 /* 6211 * Otherwise, we'll need one or more external S/G list chunks. 6212 * Get the first one and its dma address into the Inbound message. 6213 */ 6214 mutex_enter(&pwp->dma_lock); 6215 tc = pwp->dma_freelist; 6216 if (tc == NULL) { 6217 SCHEDULE_WORK(pwp, PMCS_WORK_ADD_DMA_CHUNKS); 6218 mutex_exit(&pwp->dma_lock); 6219 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, 6220 "%s: out of SG lists", __func__); 6221 return (-1); 6222 } 6223 pwp->dma_freelist = tc->nxt; 6224 mutex_exit(&pwp->dma_lock); 6225 6226 tc->nxt = NULL; 6227 sp->cmd_clist = tc; 6228 sgl = tc->chunks; 6229 (void) memset(tc->chunks, 0, PMCS_SGL_CHUNKSZ); 6230 sgl_addr = tc->addr; 6231 msg[12] = LE_32(DWORD0(sgl_addr)); 6232 msg[13] = LE_32(DWORD1(sgl_addr)); 6233 msg[14] = 0; 6234 msg[15] = LE_32(PMCS_DMASGL_EXTENSION); 6235 6236 prior = sgl; 6237 tsc = 0; 6238 6239 for (seg = 0; seg < CMD2PKT(sp)->pkt_numcookies; seg++) { 6240 /* 6241 * If the current segment count for this chunk is one less than 6242 * the number s/g lists per chunk and we have more than one seg 6243 * to go, we need another chunk. Get it, and make sure that the 6244 * tail end of the the previous chunk points the new chunk 6245 * (if remembering an offset can be called 'pointing to'). 6246 * 6247 * Note that we can store the offset into our command area that 6248 * represents the new chunk in the length field of the part 6249 * that points the PMC chip at the next chunk- the PMC chip 6250 * ignores this field when the EXTENSION bit is set. 6251 * 6252 * This is required for dma unloads later. 6253 */ 6254 if (tsc == (PMCS_SGL_NCHUNKS - 1) && 6255 seg < (CMD2PKT(sp)->pkt_numcookies - 1)) { 6256 mutex_enter(&pwp->dma_lock); 6257 tc = pwp->dma_freelist; 6258 if (tc == NULL) { 6259 SCHEDULE_WORK(pwp, PMCS_WORK_ADD_DMA_CHUNKS); 6260 mutex_exit(&pwp->dma_lock); 6261 pmcs_dma_unload(pwp, sp); 6262 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, 6263 "%s: out of SG lists", __func__); 6264 return (-1); 6265 } 6266 pwp->dma_freelist = tc->nxt; 6267 tc->nxt = sp->cmd_clist; 6268 mutex_exit(&pwp->dma_lock); 6269 6270 sp->cmd_clist = tc; 6271 (void) memset(tc->chunks, 0, PMCS_SGL_CHUNKSZ); 6272 sgl = tc->chunks; 6273 sgl_addr = tc->addr; 6274 prior[PMCS_SGL_NCHUNKS-1].sglal = 6275 LE_32(DWORD0(sgl_addr)); 6276 prior[PMCS_SGL_NCHUNKS-1].sglah = 6277 LE_32(DWORD1(sgl_addr)); 6278 prior[PMCS_SGL_NCHUNKS-1].sglen = 0; 6279 prior[PMCS_SGL_NCHUNKS-1].flags = 6280 LE_32(PMCS_DMASGL_EXTENSION); 6281 prior = sgl; 6282 tsc = 0; 6283 } 6284 sgl[tsc].sglal = LE_32(DWORD0(sg->dmac_laddress)); 6285 sgl[tsc].sglah = LE_32(DWORD1(sg->dmac_laddress)); 6286 sgl[tsc].sglen = LE_32(sg->dmac_size); 6287 sgl[tsc++].flags = 0; 6288 sg++; 6289 } 6290 return (0); 6291 } 6292 6293 /* 6294 * Unload DMA 6295 */ 6296 void 6297 pmcs_dma_unload(pmcs_hw_t *pwp, pmcs_cmd_t *sp) 6298 { 6299 pmcs_dmachunk_t *cp; 6300 6301 mutex_enter(&pwp->dma_lock); 6302 while ((cp = sp->cmd_clist) != NULL) { 6303 sp->cmd_clist = cp->nxt; 6304 cp->nxt = pwp->dma_freelist; 6305 pwp->dma_freelist = cp; 6306 } 6307 mutex_exit(&pwp->dma_lock); 6308 } 6309 6310 /* 6311 * Take a chunk of consistent memory that has just been allocated and inserted 6312 * into the cip indices and prepare it for DMA chunk usage and add it to the 6313 * freelist. 6314 * 6315 * Called with dma_lock locked (except during attach when it's unnecessary) 6316 */ 6317 void 6318 pmcs_idma_chunks(pmcs_hw_t *pwp, pmcs_dmachunk_t *dcp, 6319 pmcs_chunk_t *pchunk, unsigned long lim) 6320 { 6321 unsigned long off, n; 6322 pmcs_dmachunk_t *np = dcp; 6323 pmcs_chunk_t *tmp_chunk; 6324 6325 if (pwp->dma_chunklist == NULL) { 6326 pwp->dma_chunklist = pchunk; 6327 } else { 6328 tmp_chunk = pwp->dma_chunklist; 6329 while (tmp_chunk->next) { 6330 tmp_chunk = tmp_chunk->next; 6331 } 6332 tmp_chunk->next = pchunk; 6333 } 6334 6335 /* 6336 * Install offsets into chunk lists. 6337 */ 6338 for (n = 0, off = 0; off < lim; off += PMCS_SGL_CHUNKSZ, n++) { 6339 np->chunks = (void *)&pchunk->addrp[off]; 6340 np->addr = pchunk->dma_addr + off; 6341 np->acc_handle = pchunk->acc_handle; 6342 np->dma_handle = pchunk->dma_handle; 6343 if ((off + PMCS_SGL_CHUNKSZ) < lim) { 6344 np = np->nxt; 6345 } 6346 } 6347 np->nxt = pwp->dma_freelist; 6348 pwp->dma_freelist = dcp; 6349 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, 6350 "added %lu DMA chunks ", n); 6351 } 6352 6353 /* 6354 * Change the value of the interrupt coalescing timer. This is done currently 6355 * only for I/O completions. If we're using the "auto clear" feature, it can 6356 * be turned back on when interrupt coalescing is turned off and must be 6357 * turned off when the coalescing timer is on. 6358 * NOTE: PMCS_MSIX_GENERAL and PMCS_OQ_IODONE are the same value. As long 6359 * as that's true, we don't need to distinguish between them. 6360 */ 6361 6362 void 6363 pmcs_set_intr_coal_timer(pmcs_hw_t *pwp, pmcs_coal_timer_adj_t adj) 6364 { 6365 if (adj == DECREASE_TIMER) { 6366 /* If the timer is already off, nothing to do. */ 6367 if (pwp->io_intr_coal.timer_on == B_FALSE) { 6368 return; 6369 } 6370 6371 pwp->io_intr_coal.intr_coal_timer -= PMCS_COAL_TIMER_GRAN; 6372 6373 if (pwp->io_intr_coal.intr_coal_timer == 0) { 6374 /* Disable the timer */ 6375 pmcs_wr_topunit(pwp, PMCS_INT_COALESCING_CONTROL, 0); 6376 6377 if (pwp->odb_auto_clear & (1 << PMCS_MSIX_IODONE)) { 6378 pmcs_wr_topunit(pwp, PMCS_OBDB_AUTO_CLR, 6379 pwp->odb_auto_clear); 6380 } 6381 6382 pwp->io_intr_coal.timer_on = B_FALSE; 6383 pwp->io_intr_coal.max_io_completions = B_FALSE; 6384 pwp->io_intr_coal.num_intrs = 0; 6385 pwp->io_intr_coal.int_cleared = B_FALSE; 6386 pwp->io_intr_coal.num_io_completions = 0; 6387 6388 DTRACE_PROBE1(pmcs__intr__coalesce__timer__off, 6389 pmcs_io_intr_coal_t *, &pwp->io_intr_coal); 6390 } else { 6391 pmcs_wr_topunit(pwp, PMCS_INT_COALESCING_TIMER, 6392 pwp->io_intr_coal.intr_coal_timer); 6393 } 6394 } else { 6395 /* 6396 * If the timer isn't on yet, do the setup for it now. 6397 */ 6398 if (pwp->io_intr_coal.timer_on == B_FALSE) { 6399 /* If auto clear is being used, turn it off. */ 6400 if (pwp->odb_auto_clear & (1 << PMCS_MSIX_IODONE)) { 6401 pmcs_wr_topunit(pwp, PMCS_OBDB_AUTO_CLR, 6402 (pwp->odb_auto_clear & 6403 ~(1 << PMCS_MSIX_IODONE))); 6404 } 6405 6406 pmcs_wr_topunit(pwp, PMCS_INT_COALESCING_CONTROL, 6407 (1 << PMCS_MSIX_IODONE)); 6408 pwp->io_intr_coal.timer_on = B_TRUE; 6409 pwp->io_intr_coal.intr_coal_timer = 6410 PMCS_COAL_TIMER_GRAN; 6411 6412 DTRACE_PROBE1(pmcs__intr__coalesce__timer__on, 6413 pmcs_io_intr_coal_t *, &pwp->io_intr_coal); 6414 } else { 6415 pwp->io_intr_coal.intr_coal_timer += 6416 PMCS_COAL_TIMER_GRAN; 6417 } 6418 6419 if (pwp->io_intr_coal.intr_coal_timer > PMCS_MAX_COAL_TIMER) { 6420 pwp->io_intr_coal.intr_coal_timer = PMCS_MAX_COAL_TIMER; 6421 } 6422 6423 pmcs_wr_topunit(pwp, PMCS_INT_COALESCING_TIMER, 6424 pwp->io_intr_coal.intr_coal_timer); 6425 } 6426 6427 /* 6428 * Adjust the interrupt threshold based on the current timer value 6429 */ 6430 pwp->io_intr_coal.intr_threshold = 6431 PMCS_INTR_THRESHOLD(PMCS_QUANTUM_TIME_USECS * 1000 / 6432 (pwp->io_intr_coal.intr_latency + 6433 (pwp->io_intr_coal.intr_coal_timer * 1000))); 6434 } 6435 6436 /* 6437 * Register Access functions 6438 */ 6439 uint32_t 6440 pmcs_rd_iqci(pmcs_hw_t *pwp, uint32_t qnum) 6441 { 6442 uint32_t iqci; 6443 6444 if (ddi_dma_sync(pwp->cip_handles, 0, 0, DDI_DMA_SYNC_FORKERNEL) != 6445 DDI_SUCCESS) { 6446 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6447 "%s: ddi_dma_sync failed?", __func__); 6448 } 6449 6450 iqci = LE_32( 6451 ((uint32_t *)((void *)pwp->cip))[IQ_OFFSET(qnum) >> 2]); 6452 6453 return (iqci); 6454 } 6455 6456 uint32_t 6457 pmcs_rd_oqpi(pmcs_hw_t *pwp, uint32_t qnum) 6458 { 6459 uint32_t oqpi; 6460 6461 if (ddi_dma_sync(pwp->cip_handles, 0, 0, DDI_DMA_SYNC_FORKERNEL) != 6462 DDI_SUCCESS) { 6463 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6464 "%s: ddi_dma_sync failed?", __func__); 6465 } 6466 6467 oqpi = LE_32( 6468 ((uint32_t *)((void *)pwp->cip))[OQ_OFFSET(qnum) >> 2]); 6469 6470 return (oqpi); 6471 } 6472 6473 uint32_t 6474 pmcs_rd_gsm_reg(pmcs_hw_t *pwp, uint32_t off) 6475 { 6476 uint32_t rv, newaxil, oldaxil; 6477 6478 newaxil = off & ~GSM_BASE_MASK; 6479 off &= GSM_BASE_MASK; 6480 mutex_enter(&pwp->axil_lock); 6481 oldaxil = ddi_get32(pwp->top_acc_handle, 6482 &pwp->top_regs[PMCS_AXI_TRANS >> 2]); 6483 ddi_put32(pwp->top_acc_handle, 6484 &pwp->top_regs[PMCS_AXI_TRANS >> 2], newaxil); 6485 drv_usecwait(10); 6486 if (ddi_get32(pwp->top_acc_handle, 6487 &pwp->top_regs[PMCS_AXI_TRANS >> 2]) != newaxil) { 6488 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6489 "AXIL register update failed"); 6490 } 6491 rv = ddi_get32(pwp->gsm_acc_handle, &pwp->gsm_regs[off >> 2]); 6492 ddi_put32(pwp->top_acc_handle, 6493 &pwp->top_regs[PMCS_AXI_TRANS >> 2], oldaxil); 6494 drv_usecwait(10); 6495 if (ddi_get32(pwp->top_acc_handle, 6496 &pwp->top_regs[PMCS_AXI_TRANS >> 2]) != oldaxil) { 6497 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6498 "AXIL register restore failed"); 6499 } 6500 mutex_exit(&pwp->axil_lock); 6501 return (rv); 6502 } 6503 6504 void 6505 pmcs_wr_gsm_reg(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6506 { 6507 uint32_t newaxil, oldaxil; 6508 6509 newaxil = off & ~GSM_BASE_MASK; 6510 off &= GSM_BASE_MASK; 6511 mutex_enter(&pwp->axil_lock); 6512 oldaxil = ddi_get32(pwp->top_acc_handle, 6513 &pwp->top_regs[PMCS_AXI_TRANS >> 2]); 6514 ddi_put32(pwp->top_acc_handle, 6515 &pwp->top_regs[PMCS_AXI_TRANS >> 2], newaxil); 6516 drv_usecwait(10); 6517 if (ddi_get32(pwp->top_acc_handle, 6518 &pwp->top_regs[PMCS_AXI_TRANS >> 2]) != newaxil) { 6519 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6520 "AXIL register update failed"); 6521 } 6522 ddi_put32(pwp->gsm_acc_handle, &pwp->gsm_regs[off >> 2], val); 6523 ddi_put32(pwp->top_acc_handle, 6524 &pwp->top_regs[PMCS_AXI_TRANS >> 2], oldaxil); 6525 drv_usecwait(10); 6526 if (ddi_get32(pwp->top_acc_handle, 6527 &pwp->top_regs[PMCS_AXI_TRANS >> 2]) != oldaxil) { 6528 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6529 "AXIL register restore failed"); 6530 } 6531 mutex_exit(&pwp->axil_lock); 6532 } 6533 6534 uint32_t 6535 pmcs_rd_topunit(pmcs_hw_t *pwp, uint32_t off) 6536 { 6537 switch (off) { 6538 case PMCS_SPC_RESET: 6539 case PMCS_SPC_BOOT_STRAP: 6540 case PMCS_SPC_DEVICE_ID: 6541 case PMCS_DEVICE_REVISION: 6542 off = pmcs_rd_gsm_reg(pwp, off); 6543 break; 6544 default: 6545 off = ddi_get32(pwp->top_acc_handle, 6546 &pwp->top_regs[off >> 2]); 6547 break; 6548 } 6549 return (off); 6550 } 6551 6552 void 6553 pmcs_wr_topunit(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6554 { 6555 switch (off) { 6556 case PMCS_SPC_RESET: 6557 case PMCS_DEVICE_REVISION: 6558 pmcs_wr_gsm_reg(pwp, off, val); 6559 break; 6560 default: 6561 ddi_put32(pwp->top_acc_handle, &pwp->top_regs[off >> 2], val); 6562 break; 6563 } 6564 } 6565 6566 uint32_t 6567 pmcs_rd_msgunit(pmcs_hw_t *pwp, uint32_t off) 6568 { 6569 return (ddi_get32(pwp->msg_acc_handle, &pwp->msg_regs[off >> 2])); 6570 } 6571 6572 uint32_t 6573 pmcs_rd_mpi_tbl(pmcs_hw_t *pwp, uint32_t off) 6574 { 6575 return (ddi_get32(pwp->mpi_acc_handle, 6576 &pwp->mpi_regs[(pwp->mpi_offset + off) >> 2])); 6577 } 6578 6579 uint32_t 6580 pmcs_rd_gst_tbl(pmcs_hw_t *pwp, uint32_t off) 6581 { 6582 return (ddi_get32(pwp->mpi_acc_handle, 6583 &pwp->mpi_regs[(pwp->mpi_gst_offset + off) >> 2])); 6584 } 6585 6586 uint32_t 6587 pmcs_rd_iqc_tbl(pmcs_hw_t *pwp, uint32_t off) 6588 { 6589 return (ddi_get32(pwp->mpi_acc_handle, 6590 &pwp->mpi_regs[(pwp->mpi_iqc_offset + off) >> 2])); 6591 } 6592 6593 uint32_t 6594 pmcs_rd_oqc_tbl(pmcs_hw_t *pwp, uint32_t off) 6595 { 6596 return (ddi_get32(pwp->mpi_acc_handle, 6597 &pwp->mpi_regs[(pwp->mpi_oqc_offset + off) >> 2])); 6598 } 6599 6600 uint32_t 6601 pmcs_rd_iqpi(pmcs_hw_t *pwp, uint32_t qnum) 6602 { 6603 return (ddi_get32(pwp->mpi_acc_handle, 6604 &pwp->mpi_regs[pwp->iqpi_offset[qnum] >> 2])); 6605 } 6606 6607 uint32_t 6608 pmcs_rd_oqci(pmcs_hw_t *pwp, uint32_t qnum) 6609 { 6610 return (ddi_get32(pwp->mpi_acc_handle, 6611 &pwp->mpi_regs[pwp->oqci_offset[qnum] >> 2])); 6612 } 6613 6614 void 6615 pmcs_wr_msgunit(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6616 { 6617 ddi_put32(pwp->msg_acc_handle, &pwp->msg_regs[off >> 2], val); 6618 } 6619 6620 void 6621 pmcs_wr_mpi_tbl(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6622 { 6623 ddi_put32(pwp->mpi_acc_handle, 6624 &pwp->mpi_regs[(pwp->mpi_offset + off) >> 2], (val)); 6625 } 6626 6627 void 6628 pmcs_wr_gst_tbl(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6629 { 6630 ddi_put32(pwp->mpi_acc_handle, 6631 &pwp->mpi_regs[(pwp->mpi_gst_offset + off) >> 2], val); 6632 } 6633 6634 void 6635 pmcs_wr_iqc_tbl(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6636 { 6637 ddi_put32(pwp->mpi_acc_handle, 6638 &pwp->mpi_regs[(pwp->mpi_iqc_offset + off) >> 2], val); 6639 } 6640 6641 void 6642 pmcs_wr_oqc_tbl(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6643 { 6644 ddi_put32(pwp->mpi_acc_handle, 6645 &pwp->mpi_regs[(pwp->mpi_oqc_offset + off) >> 2], val); 6646 } 6647 6648 void 6649 pmcs_wr_iqci(pmcs_hw_t *pwp, uint32_t qnum, uint32_t val) 6650 { 6651 ((uint32_t *)((void *)pwp->cip))[IQ_OFFSET(qnum) >> 2] = val; 6652 if (ddi_dma_sync(pwp->cip_handles, 0, 0, DDI_DMA_SYNC_FORDEV) != 6653 DDI_SUCCESS) { 6654 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6655 "%s: ddi_dma_sync failed?", __func__); 6656 } 6657 } 6658 6659 void 6660 pmcs_wr_iqpi(pmcs_hw_t *pwp, uint32_t qnum, uint32_t val) 6661 { 6662 ddi_put32(pwp->mpi_acc_handle, 6663 &pwp->mpi_regs[pwp->iqpi_offset[qnum] >> 2], val); 6664 } 6665 6666 void 6667 pmcs_wr_oqci(pmcs_hw_t *pwp, uint32_t qnum, uint32_t val) 6668 { 6669 ddi_put32(pwp->mpi_acc_handle, 6670 &pwp->mpi_regs[pwp->oqci_offset[qnum] >> 2], val); 6671 } 6672 6673 void 6674 pmcs_wr_oqpi(pmcs_hw_t *pwp, uint32_t qnum, uint32_t val) 6675 { 6676 ((uint32_t *)((void *)pwp->cip))[OQ_OFFSET(qnum) >> 2] = val; 6677 if (ddi_dma_sync(pwp->cip_handles, 0, 0, DDI_DMA_SYNC_FORDEV) != 6678 DDI_SUCCESS) { 6679 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6680 "%s: ddi_dma_sync failed?", __func__); 6681 } 6682 } 6683 6684 /* 6685 * Check the status value of an outbound IOMB and report anything bad 6686 */ 6687 6688 void 6689 pmcs_check_iomb_status(pmcs_hw_t *pwp, uint32_t *iomb) 6690 { 6691 uint16_t opcode; 6692 int offset; 6693 6694 if (iomb == NULL) { 6695 return; 6696 } 6697 6698 opcode = LE_32(iomb[0]) & 0xfff; 6699 6700 switch (opcode) { 6701 /* 6702 * The following have no status field, so ignore them 6703 */ 6704 case PMCOUT_ECHO: 6705 case PMCOUT_SAS_HW_EVENT: 6706 case PMCOUT_GET_DEVICE_HANDLE: 6707 case PMCOUT_SATA_EVENT: 6708 case PMCOUT_SSP_EVENT: 6709 case PMCOUT_DEVICE_HANDLE_ARRIVED: 6710 case PMCOUT_SMP_REQUEST_RECEIVED: 6711 case PMCOUT_GPIO: 6712 case PMCOUT_GPIO_EVENT: 6713 case PMCOUT_GET_TIME_STAMP: 6714 case PMCOUT_SKIP_ENTRIES: 6715 case PMCOUT_GET_NVMD_DATA: /* Actually lower 16 bits of word 3 */ 6716 case PMCOUT_SET_NVMD_DATA: /* but ignore - we don't use these */ 6717 case PMCOUT_DEVICE_HANDLE_REMOVED: 6718 case PMCOUT_SSP_REQUEST_RECEIVED: 6719 return; 6720 6721 case PMCOUT_GENERAL_EVENT: 6722 offset = 1; 6723 break; 6724 6725 case PMCOUT_SSP_COMPLETION: 6726 case PMCOUT_SMP_COMPLETION: 6727 case PMCOUT_DEVICE_REGISTRATION: 6728 case PMCOUT_DEREGISTER_DEVICE_HANDLE: 6729 case PMCOUT_SATA_COMPLETION: 6730 case PMCOUT_DEVICE_INFO: 6731 case PMCOUT_FW_FLASH_UPDATE: 6732 case PMCOUT_SSP_ABORT: 6733 case PMCOUT_SATA_ABORT: 6734 case PMCOUT_SAS_DIAG_MODE_START_END: 6735 case PMCOUT_SAS_HW_EVENT_ACK_ACK: 6736 case PMCOUT_SMP_ABORT: 6737 case PMCOUT_SET_DEVICE_STATE: 6738 case PMCOUT_GET_DEVICE_STATE: 6739 case PMCOUT_SET_DEVICE_INFO: 6740 offset = 2; 6741 break; 6742 6743 case PMCOUT_LOCAL_PHY_CONTROL: 6744 case PMCOUT_SAS_DIAG_EXECUTE: 6745 case PMCOUT_PORT_CONTROL: 6746 offset = 3; 6747 break; 6748 6749 case PMCOUT_GET_INFO: 6750 case PMCOUT_GET_VPD: 6751 case PMCOUT_SAS_ASSISTED_DISCOVERY_EVENT: 6752 case PMCOUT_SATA_ASSISTED_DISCOVERY_EVENT: 6753 case PMCOUT_SET_VPD: 6754 case PMCOUT_TWI: 6755 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, 6756 "Got response for deprecated opcode", iomb); 6757 return; 6758 6759 default: 6760 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, 6761 "Got response for unknown opcode", iomb); 6762 return; 6763 } 6764 6765 if (LE_32(iomb[offset]) != PMCOUT_STATUS_OK) { 6766 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, 6767 "bad status on TAG_TYPE_NONE command", iomb); 6768 } 6769 } 6770 6771 /* 6772 * Called with statlock held 6773 */ 6774 void 6775 pmcs_clear_xp(pmcs_hw_t *pwp, pmcs_xscsi_t *xp) 6776 { 6777 _NOTE(ARGUNUSED(pwp)); 6778 6779 ASSERT(mutex_owned(&xp->statlock)); 6780 6781 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, xp, "%s: Device 0x%p is gone.", 6782 __func__, (void *)xp); 6783 6784 /* 6785 * Clear the dip now. This keeps pmcs_remove_device from attempting 6786 * to call us on the same device while we're still flushing queues. 6787 * The only side effect is we can no longer update SM-HBA properties, 6788 * but this device is going away anyway, so no matter. 6789 */ 6790 xp->dip = NULL; 6791 xp->smpd = NULL; 6792 xp->special_running = 0; 6793 xp->recovering = 0; 6794 xp->recover_wait = 0; 6795 xp->draining = 0; 6796 xp->new = 0; 6797 xp->assigned = 0; 6798 xp->dev_state = 0; 6799 xp->tagmap = 0; 6800 xp->dev_gone = 1; 6801 xp->event_recovery = 0; 6802 xp->dtype = NOTHING; 6803 xp->wq_recovery_tail = NULL; 6804 /* Don't clear xp->phy */ 6805 /* Don't clear xp->actv_cnt */ 6806 /* Don't clear xp->actv_pkts */ 6807 6808 /* 6809 * Flush all target queues 6810 */ 6811 pmcs_flush_target_queues(pwp, xp, PMCS_TGT_ALL_QUEUES); 6812 } 6813 6814 static int 6815 pmcs_smp_function_result(pmcs_hw_t *pwp, smp_response_frame_t *srf) 6816 { 6817 int result = srf->srf_result; 6818 6819 switch (result) { 6820 case SMP_RES_UNKNOWN_FUNCTION: 6821 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6822 "%s: SMP DISCOVER Response " 6823 "Function Result: Unknown SMP Function(0x%x)", 6824 __func__, result); 6825 break; 6826 case SMP_RES_FUNCTION_FAILED: 6827 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6828 "%s: SMP DISCOVER Response " 6829 "Function Result: SMP Function Failed(0x%x)", 6830 __func__, result); 6831 break; 6832 case SMP_RES_INVALID_REQUEST_FRAME_LENGTH: 6833 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6834 "%s: SMP DISCOVER Response " 6835 "Function Result: Invalid Request Frame Length(0x%x)", 6836 __func__, result); 6837 break; 6838 case SMP_RES_INCOMPLETE_DESCRIPTOR_LIST: 6839 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6840 "%s: SMP DISCOVER Response " 6841 "Function Result: Incomplete Descriptor List(0x%x)", 6842 __func__, result); 6843 break; 6844 case SMP_RES_PHY_DOES_NOT_EXIST: 6845 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6846 "%s: SMP DISCOVER Response " 6847 "Function Result: PHY does not exist(0x%x)", 6848 __func__, result); 6849 break; 6850 case SMP_RES_PHY_VACANT: 6851 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6852 "%s: SMP DISCOVER Response " 6853 "Function Result: PHY Vacant(0x%x)", 6854 __func__, result); 6855 break; 6856 default: 6857 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6858 "%s: SMP DISCOVER Response " 6859 "Function Result: (0x%x)", 6860 __func__, result); 6861 break; 6862 } 6863 6864 return (result); 6865 } 6866 6867 /* 6868 * Do all the repetitive stuff necessary to setup for DMA 6869 * 6870 * pwp: Used for dip 6871 * dma_attr: ddi_dma_attr_t to use for the mapping 6872 * acch: ddi_acc_handle_t to use for the mapping 6873 * dmah: ddi_dma_handle_t to use 6874 * length: Amount of memory for mapping 6875 * kvap: Pointer filled in with kernel virtual address on successful return 6876 * dma_addr: Pointer filled in with DMA address on successful return 6877 */ 6878 boolean_t 6879 pmcs_dma_setup(pmcs_hw_t *pwp, ddi_dma_attr_t *dma_attr, ddi_acc_handle_t *acch, 6880 ddi_dma_handle_t *dmah, size_t length, caddr_t *kvap, uint64_t *dma_addr) 6881 { 6882 dev_info_t *dip = pwp->dip; 6883 ddi_dma_cookie_t cookie; 6884 size_t real_length; 6885 uint_t ddma_flag = DDI_DMA_CONSISTENT; 6886 uint_t ddabh_flag = DDI_DMA_CONSISTENT | DDI_DMA_RDWR; 6887 uint_t cookie_cnt; 6888 ddi_device_acc_attr_t mattr = { 6889 DDI_DEVICE_ATTR_V0, 6890 DDI_NEVERSWAP_ACC, 6891 DDI_STRICTORDER_ACC, 6892 DDI_DEFAULT_ACC 6893 }; 6894 6895 *acch = NULL; 6896 *dmah = NULL; 6897 6898 if (ddi_dma_alloc_handle(dip, dma_attr, DDI_DMA_SLEEP, NULL, dmah) != 6899 DDI_SUCCESS) { 6900 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6901 "Failed to allocate DMA handle"); 6902 return (B_FALSE); 6903 } 6904 6905 if (ddi_dma_mem_alloc(*dmah, length, &mattr, ddma_flag, DDI_DMA_SLEEP, 6906 NULL, kvap, &real_length, acch) != DDI_SUCCESS) { 6907 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6908 "Failed to allocate DMA mem"); 6909 ddi_dma_free_handle(dmah); 6910 *dmah = NULL; 6911 return (B_FALSE); 6912 } 6913 6914 if (ddi_dma_addr_bind_handle(*dmah, NULL, *kvap, real_length, 6915 ddabh_flag, DDI_DMA_SLEEP, NULL, &cookie, &cookie_cnt) 6916 != DDI_DMA_MAPPED) { 6917 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "Failed to bind DMA"); 6918 ddi_dma_free_handle(dmah); 6919 ddi_dma_mem_free(acch); 6920 *dmah = NULL; 6921 *acch = NULL; 6922 return (B_FALSE); 6923 } 6924 6925 if (cookie_cnt != 1) { 6926 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "Multiple cookies"); 6927 if (ddi_dma_unbind_handle(*dmah) != DDI_SUCCESS) { 6928 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "Condition " 6929 "failed at %s():%d", __func__, __LINE__); 6930 } 6931 ddi_dma_free_handle(dmah); 6932 ddi_dma_mem_free(acch); 6933 *dmah = NULL; 6934 *acch = NULL; 6935 return (B_FALSE); 6936 } 6937 6938 *dma_addr = cookie.dmac_laddress; 6939 6940 return (B_TRUE); 6941 } 6942 6943 /* 6944 * Flush requested queues for a particular target. Called with statlock held 6945 */ 6946 void 6947 pmcs_flush_target_queues(pmcs_hw_t *pwp, pmcs_xscsi_t *tgt, uint8_t queues) 6948 { 6949 pmcs_cmd_t *sp, *sp_next; 6950 pmcwork_t *pwrk; 6951 6952 ASSERT(pwp != NULL); 6953 ASSERT(tgt != NULL); 6954 6955 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, tgt, 6956 "%s: Flushing queues (%d) for target 0x%p", __func__, 6957 queues, (void *)tgt); 6958 6959 /* 6960 * Commands on the wait queue (or the special queue below) don't have 6961 * work structures associated with them. 6962 */ 6963 if (queues & PMCS_TGT_WAIT_QUEUE) { 6964 mutex_enter(&tgt->wqlock); 6965 while ((sp = STAILQ_FIRST(&tgt->wq)) != NULL) { 6966 STAILQ_REMOVE(&tgt->wq, sp, pmcs_cmd, cmd_next); 6967 pmcs_prt(pwp, PMCS_PRT_DEBUG1, NULL, tgt, 6968 "%s: Removing cmd 0x%p from wq for target 0x%p", 6969 __func__, (void *)sp, (void *)tgt); 6970 CMD2PKT(sp)->pkt_reason = CMD_DEV_GONE; 6971 CMD2PKT(sp)->pkt_state = STATE_GOT_BUS; 6972 mutex_exit(&tgt->wqlock); 6973 pmcs_dma_unload(pwp, sp); 6974 mutex_enter(&pwp->cq_lock); 6975 STAILQ_INSERT_TAIL(&pwp->cq, sp, cmd_next); 6976 mutex_exit(&pwp->cq_lock); 6977 mutex_enter(&tgt->wqlock); 6978 } 6979 mutex_exit(&tgt->wqlock); 6980 } 6981 6982 /* 6983 * Commands on the active queue will have work structures associated 6984 * with them. 6985 */ 6986 if (queues & PMCS_TGT_ACTIVE_QUEUE) { 6987 mutex_enter(&tgt->aqlock); 6988 sp = STAILQ_FIRST(&tgt->aq); 6989 while (sp) { 6990 sp_next = STAILQ_NEXT(sp, cmd_next); 6991 pwrk = pmcs_tag2wp(pwp, sp->cmd_tag); 6992 6993 /* 6994 * If we don't find a work structure, it's because 6995 * the command is already complete. If so, move on 6996 * to the next one. 6997 */ 6998 if (pwrk == NULL) { 6999 pmcs_prt(pwp, PMCS_PRT_DEBUG1, tgt->phy, tgt, 7000 "%s: Not removing cmd 0x%p (htag 0x%x) " 7001 "from aq", __func__, (void *)sp, 7002 sp->cmd_tag); 7003 sp = sp_next; 7004 continue; 7005 } 7006 7007 STAILQ_REMOVE(&tgt->aq, sp, pmcs_cmd, cmd_next); 7008 pmcs_prt(pwp, PMCS_PRT_DEBUG1, tgt->phy, tgt, 7009 "%s: Removing cmd 0x%p (htag 0x%x) from aq for " 7010 "target 0x%p", __func__, (void *)sp, sp->cmd_tag, 7011 (void *)tgt); 7012 mutex_exit(&tgt->aqlock); 7013 mutex_exit(&tgt->statlock); 7014 /* 7015 * Mark the work structure as dead and complete it 7016 */ 7017 pwrk->dead = 1; 7018 CMD2PKT(sp)->pkt_reason = CMD_DEV_GONE; 7019 CMD2PKT(sp)->pkt_state = STATE_GOT_BUS; 7020 pmcs_complete_work_impl(pwp, pwrk, NULL, 0); 7021 pmcs_dma_unload(pwp, sp); 7022 mutex_enter(&pwp->cq_lock); 7023 STAILQ_INSERT_TAIL(&pwp->cq, sp, cmd_next); 7024 mutex_exit(&pwp->cq_lock); 7025 mutex_enter(&tgt->aqlock); 7026 mutex_enter(&tgt->statlock); 7027 sp = sp_next; 7028 } 7029 mutex_exit(&tgt->aqlock); 7030 } 7031 7032 if (queues & PMCS_TGT_SPECIAL_QUEUE) { 7033 while ((sp = STAILQ_FIRST(&tgt->sq)) != NULL) { 7034 STAILQ_REMOVE(&tgt->sq, sp, pmcs_cmd, cmd_next); 7035 pmcs_prt(pwp, PMCS_PRT_DEBUG1, tgt->phy, tgt, 7036 "%s: Removing cmd 0x%p from sq for target 0x%p", 7037 __func__, (void *)sp, (void *)tgt); 7038 CMD2PKT(sp)->pkt_reason = CMD_DEV_GONE; 7039 CMD2PKT(sp)->pkt_state = STATE_GOT_BUS; 7040 pmcs_dma_unload(pwp, sp); 7041 mutex_enter(&pwp->cq_lock); 7042 STAILQ_INSERT_TAIL(&pwp->cq, sp, cmd_next); 7043 mutex_exit(&pwp->cq_lock); 7044 } 7045 } 7046 } 7047 7048 void 7049 pmcs_complete_work_impl(pmcs_hw_t *pwp, pmcwork_t *pwrk, uint32_t *iomb, 7050 size_t amt) 7051 { 7052 switch (PMCS_TAG_TYPE(pwrk->htag)) { 7053 case PMCS_TAG_TYPE_CBACK: 7054 { 7055 pmcs_cb_t callback = (pmcs_cb_t)pwrk->ptr; 7056 (*callback)(pwp, pwrk, iomb); 7057 break; 7058 } 7059 case PMCS_TAG_TYPE_WAIT: 7060 if (pwrk->arg && iomb && amt) { 7061 (void) memcpy(pwrk->arg, iomb, amt); 7062 } 7063 cv_signal(&pwrk->sleep_cv); 7064 mutex_exit(&pwrk->lock); 7065 break; 7066 case PMCS_TAG_TYPE_NONE: 7067 #ifdef DEBUG 7068 pmcs_check_iomb_status(pwp, iomb); 7069 #endif 7070 pmcs_pwork(pwp, pwrk); 7071 break; 7072 default: 7073 /* 7074 * We will leak a structure here if we don't know 7075 * what happened 7076 */ 7077 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 7078 "%s: Unknown PMCS_TAG_TYPE (%x)", 7079 __func__, PMCS_TAG_TYPE(pwrk->htag)); 7080 break; 7081 } 7082 } 7083 7084 /* 7085 * Determine if iport still has targets. During detach(9E), if SCSA is 7086 * successfull in its guarantee of tran_tgt_free(9E) before detach(9E), 7087 * this should always return B_FALSE. 7088 */ 7089 boolean_t 7090 pmcs_iport_has_targets(pmcs_hw_t *pwp, pmcs_iport_t *iport) 7091 { 7092 pmcs_xscsi_t *xp; 7093 int i; 7094 7095 mutex_enter(&pwp->lock); 7096 7097 if (!pwp->targets || !pwp->max_dev) { 7098 mutex_exit(&pwp->lock); 7099 return (B_FALSE); 7100 } 7101 7102 for (i = 0; i < pwp->max_dev; i++) { 7103 xp = pwp->targets[i]; 7104 if ((xp == NULL) || (xp->phy == NULL) || 7105 (xp->phy->iport != iport)) { 7106 continue; 7107 } 7108 7109 mutex_exit(&pwp->lock); 7110 return (B_TRUE); 7111 } 7112 7113 mutex_exit(&pwp->lock); 7114 return (B_FALSE); 7115 } 7116 7117 /* 7118 * Called with softstate lock held 7119 */ 7120 void 7121 pmcs_destroy_target(pmcs_xscsi_t *target) 7122 { 7123 pmcs_hw_t *pwp = target->pwp; 7124 pmcs_iport_t *iport; 7125 7126 ASSERT(pwp); 7127 ASSERT(mutex_owned(&pwp->lock)); 7128 7129 if (!target->ua) { 7130 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, target, 7131 "%s: target %p iport address is null", 7132 __func__, (void *)target); 7133 } 7134 7135 iport = pmcs_get_iport_by_ua(pwp, target->ua); 7136 if (iport == NULL) { 7137 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, target, 7138 "%s: no iport associated with tgt(0x%p)", 7139 __func__, (void *)target); 7140 return; 7141 } 7142 7143 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, target, 7144 "%s: free target %p", __func__, (void *)target); 7145 if (target->ua) { 7146 strfree(target->ua); 7147 } 7148 7149 mutex_destroy(&target->wqlock); 7150 mutex_destroy(&target->aqlock); 7151 mutex_destroy(&target->statlock); 7152 cv_destroy(&target->reset_cv); 7153 cv_destroy(&target->abort_cv); 7154 ddi_soft_state_bystr_fini(&target->lun_sstate); 7155 ddi_soft_state_bystr_free(iport->tgt_sstate, target->unit_address); 7156 pmcs_rele_iport(iport); 7157 } 7158 7159 /* 7160 * pmcs_lock_phy_impl 7161 * 7162 * This function is what does the actual work for pmcs_lock_phy. It will 7163 * lock all PHYs from phyp down in a top-down fashion. 7164 * 7165 * Locking notes: 7166 * 1. level starts from 0 for the PHY ("parent") that's passed in. It is 7167 * not a reflection of the actual level of the PHY in the SAS topology. 7168 * 2. If parent is an expander, then parent is locked along with all its 7169 * descendents. 7170 * 3. Expander subsidiary PHYs at level 0 are not locked. It is the 7171 * responsibility of the caller to individually lock expander subsidiary PHYs 7172 * at level 0 if necessary. 7173 * 4. Siblings at level 0 are not traversed due to the possibility that we're 7174 * locking a PHY on the dead list. The siblings could be pointing to invalid 7175 * PHYs. We don't lock siblings at level 0 anyway. 7176 */ 7177 static void 7178 pmcs_lock_phy_impl(pmcs_phy_t *phyp, int level) 7179 { 7180 pmcs_phy_t *tphyp; 7181 7182 ASSERT((phyp->dtype == SAS) || (phyp->dtype == SATA) || 7183 (phyp->dtype == EXPANDER) || (phyp->dtype == NOTHING)); 7184 7185 /* 7186 * Start walking the PHYs. 7187 */ 7188 tphyp = phyp; 7189 while (tphyp) { 7190 /* 7191 * If we're at the top level, only lock ourselves. For anything 7192 * at level > 0, traverse children while locking everything. 7193 */ 7194 if ((level > 0) || (tphyp == phyp)) { 7195 pmcs_prt(tphyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, tphyp, 7196 NULL, "%s: PHY 0x%p parent 0x%p path %s lvl %d", 7197 __func__, (void *)tphyp, (void *)tphyp->parent, 7198 tphyp->path, level); 7199 mutex_enter(&tphyp->phy_lock); 7200 7201 if (tphyp->children) { 7202 pmcs_lock_phy_impl(tphyp->children, level + 1); 7203 } 7204 } 7205 7206 if (level == 0) { 7207 return; 7208 } 7209 7210 tphyp = tphyp->sibling; 7211 } 7212 } 7213 7214 /* 7215 * pmcs_lock_phy 7216 * 7217 * This function is responsible for locking a PHY and all its descendents 7218 */ 7219 void 7220 pmcs_lock_phy(pmcs_phy_t *phyp) 7221 { 7222 #ifdef DEBUG 7223 char *callername = NULL; 7224 ulong_t off; 7225 7226 ASSERT(phyp != NULL); 7227 7228 callername = modgetsymname((uintptr_t)caller(), &off); 7229 7230 if (callername == NULL) { 7231 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7232 "%s: PHY 0x%p path %s caller: unknown", __func__, 7233 (void *)phyp, phyp->path); 7234 } else { 7235 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7236 "%s: PHY 0x%p path %s caller: %s+%lx", __func__, 7237 (void *)phyp, phyp->path, callername, off); 7238 } 7239 #else 7240 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7241 "%s: PHY 0x%p path %s", __func__, (void *)phyp, phyp->path); 7242 #endif 7243 pmcs_lock_phy_impl(phyp, 0); 7244 } 7245 7246 /* 7247 * pmcs_unlock_phy_impl 7248 * 7249 * Unlock all PHYs from phyp down in a bottom-up fashion. 7250 */ 7251 static void 7252 pmcs_unlock_phy_impl(pmcs_phy_t *phyp, int level) 7253 { 7254 pmcs_phy_t *phy_next; 7255 7256 ASSERT((phyp->dtype == SAS) || (phyp->dtype == SATA) || 7257 (phyp->dtype == EXPANDER) || (phyp->dtype == NOTHING)); 7258 7259 /* 7260 * Recurse down to the bottom PHYs 7261 */ 7262 if (level == 0) { 7263 if (phyp->children) { 7264 pmcs_unlock_phy_impl(phyp->children, level + 1); 7265 } 7266 } else { 7267 phy_next = phyp; 7268 while (phy_next) { 7269 if (phy_next->children) { 7270 pmcs_unlock_phy_impl(phy_next->children, 7271 level + 1); 7272 } 7273 phy_next = phy_next->sibling; 7274 } 7275 } 7276 7277 /* 7278 * Iterate through PHYs unlocking all at level > 0 as well the top PHY 7279 */ 7280 phy_next = phyp; 7281 while (phy_next) { 7282 if ((level > 0) || (phy_next == phyp)) { 7283 pmcs_prt(phy_next->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, 7284 phy_next, NULL, 7285 "%s: PHY 0x%p parent 0x%p path %s lvl %d", 7286 __func__, (void *)phy_next, 7287 (void *)phy_next->parent, phy_next->path, level); 7288 mutex_exit(&phy_next->phy_lock); 7289 } 7290 7291 if (level == 0) { 7292 return; 7293 } 7294 7295 phy_next = phy_next->sibling; 7296 } 7297 } 7298 7299 /* 7300 * pmcs_unlock_phy 7301 * 7302 * Unlock a PHY and all its descendents 7303 */ 7304 void 7305 pmcs_unlock_phy(pmcs_phy_t *phyp) 7306 { 7307 #ifdef DEBUG 7308 char *callername = NULL; 7309 ulong_t off; 7310 7311 ASSERT(phyp != NULL); 7312 7313 callername = modgetsymname((uintptr_t)caller(), &off); 7314 7315 if (callername == NULL) { 7316 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7317 "%s: PHY 0x%p path %s caller: unknown", __func__, 7318 (void *)phyp, phyp->path); 7319 } else { 7320 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7321 "%s: PHY 0x%p path %s caller: %s+%lx", __func__, 7322 (void *)phyp, phyp->path, callername, off); 7323 } 7324 #else 7325 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7326 "%s: PHY 0x%p path %s", __func__, (void *)phyp, phyp->path); 7327 #endif 7328 pmcs_unlock_phy_impl(phyp, 0); 7329 } 7330 7331 /* 7332 * pmcs_get_root_phy 7333 * 7334 * For a given phy pointer return its root phy. 7335 * This function must only be called during discovery in order to ensure that 7336 * the chain of PHYs from phyp up to the root PHY doesn't change. 7337 */ 7338 pmcs_phy_t * 7339 pmcs_get_root_phy(pmcs_phy_t *phyp) 7340 { 7341 ASSERT(phyp); 7342 7343 while (phyp) { 7344 if (IS_ROOT_PHY(phyp)) { 7345 break; 7346 } 7347 phyp = phyp->parent; 7348 } 7349 7350 return (phyp); 7351 } 7352 7353 /* 7354 * pmcs_free_dma_chunklist 7355 * 7356 * Free DMA S/G chunk list 7357 */ 7358 void 7359 pmcs_free_dma_chunklist(pmcs_hw_t *pwp) 7360 { 7361 pmcs_chunk_t *pchunk; 7362 7363 while (pwp->dma_chunklist) { 7364 pchunk = pwp->dma_chunklist; 7365 pwp->dma_chunklist = pwp->dma_chunklist->next; 7366 if (pchunk->dma_handle) { 7367 if (ddi_dma_unbind_handle(pchunk->dma_handle) != 7368 DDI_SUCCESS) { 7369 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 7370 "Condition failed at %s():%d", 7371 __func__, __LINE__); 7372 } 7373 ddi_dma_free_handle(&pchunk->dma_handle); 7374 ddi_dma_mem_free(&pchunk->acc_handle); 7375 } 7376 kmem_free(pchunk, sizeof (pmcs_chunk_t)); 7377 } 7378 } 7379 7380 /*ARGSUSED2*/ 7381 int 7382 pmcs_phy_constructor(void *buf, void *arg, int kmflags) 7383 { 7384 pmcs_hw_t *pwp = (pmcs_hw_t *)arg; 7385 pmcs_phy_t *phyp = (pmcs_phy_t *)buf; 7386 7387 mutex_init(&phyp->phy_lock, NULL, MUTEX_DRIVER, 7388 DDI_INTR_PRI(pwp->intr_pri)); 7389 cv_init(&phyp->abort_all_cv, NULL, CV_DRIVER, NULL); 7390 return (0); 7391 } 7392 7393 /*ARGSUSED1*/ 7394 void 7395 pmcs_phy_destructor(void *buf, void *arg) 7396 { 7397 pmcs_phy_t *phyp = (pmcs_phy_t *)buf; 7398 7399 cv_destroy(&phyp->abort_all_cv); 7400 mutex_destroy(&phyp->phy_lock); 7401 } 7402 7403 /* 7404 * Free all PHYs from the kmem_cache starting at phyp as well as everything 7405 * on the dead_phys list. 7406 * 7407 * NOTE: This function does not free root PHYs as they are not allocated 7408 * from the kmem_cache. 7409 * 7410 * No PHY locks are acquired as this should only be called during DDI_DETACH 7411 * or soft reset (while pmcs interrupts are disabled). 7412 */ 7413 void 7414 pmcs_free_all_phys(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 7415 { 7416 pmcs_phy_t *tphyp, *nphyp; 7417 7418 if (phyp == NULL) { 7419 return; 7420 } 7421 7422 tphyp = phyp; 7423 while (tphyp) { 7424 nphyp = tphyp->sibling; 7425 7426 if (tphyp->children) { 7427 pmcs_free_all_phys(pwp, tphyp->children); 7428 tphyp->children = NULL; 7429 } 7430 if (!IS_ROOT_PHY(tphyp)) { 7431 kmem_cache_free(pwp->phy_cache, tphyp); 7432 } 7433 7434 tphyp = nphyp; 7435 } 7436 7437 tphyp = pwp->dead_phys; 7438 while (tphyp) { 7439 nphyp = tphyp->sibling; 7440 kmem_cache_free(pwp->phy_cache, tphyp); 7441 tphyp = nphyp; 7442 } 7443 pwp->dead_phys = NULL; 7444 } 7445 7446 /* 7447 * Free a list of PHYs linked together by the sibling pointer back to the 7448 * kmem cache from whence they came. This function does not recurse, so the 7449 * caller must ensure there are no children. 7450 */ 7451 void 7452 pmcs_free_phys(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 7453 { 7454 pmcs_phy_t *next_phy; 7455 7456 while (phyp) { 7457 next_phy = phyp->sibling; 7458 ASSERT(!mutex_owned(&phyp->phy_lock)); 7459 kmem_cache_free(pwp->phy_cache, phyp); 7460 phyp = next_phy; 7461 } 7462 } 7463 7464 /* 7465 * Make a copy of an existing PHY structure. This is used primarily in 7466 * discovery to compare the contents of an existing PHY with what gets 7467 * reported back by an expander. 7468 * 7469 * This function must not be called from any context where sleeping is 7470 * not possible. 7471 * 7472 * The new PHY is returned unlocked. 7473 */ 7474 static pmcs_phy_t * 7475 pmcs_clone_phy(pmcs_phy_t *orig_phy) 7476 { 7477 pmcs_phy_t *local; 7478 7479 local = kmem_cache_alloc(orig_phy->pwp->phy_cache, KM_SLEEP); 7480 7481 /* 7482 * Go ahead and just copy everything... 7483 */ 7484 *local = *orig_phy; 7485 7486 /* 7487 * But the following must be set appropriately for this copy 7488 */ 7489 local->sibling = NULL; 7490 local->children = NULL; 7491 mutex_init(&local->phy_lock, NULL, MUTEX_DRIVER, 7492 DDI_INTR_PRI(orig_phy->pwp->intr_pri)); 7493 7494 return (local); 7495 } 7496 7497 int 7498 pmcs_check_acc_handle(ddi_acc_handle_t handle) 7499 { 7500 ddi_fm_error_t de; 7501 7502 if (handle == NULL) { 7503 return (DDI_FAILURE); 7504 } 7505 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0); 7506 return (de.fme_status); 7507 } 7508 7509 int 7510 pmcs_check_dma_handle(ddi_dma_handle_t handle) 7511 { 7512 ddi_fm_error_t de; 7513 7514 if (handle == NULL) { 7515 return (DDI_FAILURE); 7516 } 7517 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0); 7518 return (de.fme_status); 7519 } 7520 7521 7522 void 7523 pmcs_fm_ereport(pmcs_hw_t *pwp, char *detail) 7524 { 7525 uint64_t ena; 7526 char buf[FM_MAX_CLASS]; 7527 7528 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 7529 ena = fm_ena_generate(0, FM_ENA_FMT1); 7530 if (DDI_FM_EREPORT_CAP(pwp->fm_capabilities)) { 7531 ddi_fm_ereport_post(pwp->dip, buf, ena, DDI_NOSLEEP, 7532 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 7533 } 7534 } 7535 7536 int 7537 pmcs_check_acc_dma_handle(pmcs_hw_t *pwp) 7538 { 7539 pmcs_chunk_t *pchunk; 7540 int i; 7541 7542 /* check all acc & dma handles allocated in attach */ 7543 if ((pmcs_check_acc_handle(pwp->pci_acc_handle) != DDI_SUCCESS) || 7544 (pmcs_check_acc_handle(pwp->msg_acc_handle) != DDI_SUCCESS) || 7545 (pmcs_check_acc_handle(pwp->top_acc_handle) != DDI_SUCCESS) || 7546 (pmcs_check_acc_handle(pwp->mpi_acc_handle) != DDI_SUCCESS) || 7547 (pmcs_check_acc_handle(pwp->gsm_acc_handle) != DDI_SUCCESS)) { 7548 goto check_failed; 7549 } 7550 7551 for (i = 0; i < PMCS_NIQ; i++) { 7552 if ((pmcs_check_dma_handle( 7553 pwp->iqp_handles[i]) != DDI_SUCCESS) || 7554 (pmcs_check_acc_handle( 7555 pwp->iqp_acchdls[i]) != DDI_SUCCESS)) { 7556 goto check_failed; 7557 } 7558 } 7559 7560 for (i = 0; i < PMCS_NOQ; i++) { 7561 if ((pmcs_check_dma_handle( 7562 pwp->oqp_handles[i]) != DDI_SUCCESS) || 7563 (pmcs_check_acc_handle( 7564 pwp->oqp_acchdls[i]) != DDI_SUCCESS)) { 7565 goto check_failed; 7566 } 7567 } 7568 7569 if ((pmcs_check_dma_handle(pwp->cip_handles) != DDI_SUCCESS) || 7570 (pmcs_check_acc_handle(pwp->cip_acchdls) != DDI_SUCCESS)) { 7571 goto check_failed; 7572 } 7573 7574 if (pwp->fwlog && 7575 ((pmcs_check_dma_handle(pwp->fwlog_hndl) != DDI_SUCCESS) || 7576 (pmcs_check_acc_handle(pwp->fwlog_acchdl) != DDI_SUCCESS))) { 7577 goto check_failed; 7578 } 7579 7580 if (pwp->regdump_hndl && pwp->regdump_acchdl && 7581 ((pmcs_check_dma_handle(pwp->regdump_hndl) != DDI_SUCCESS) || 7582 (pmcs_check_acc_handle(pwp->regdump_acchdl) 7583 != DDI_SUCCESS))) { 7584 goto check_failed; 7585 } 7586 7587 7588 pchunk = pwp->dma_chunklist; 7589 while (pchunk) { 7590 if ((pmcs_check_acc_handle(pchunk->acc_handle) 7591 != DDI_SUCCESS) || 7592 (pmcs_check_dma_handle(pchunk->dma_handle) 7593 != DDI_SUCCESS)) { 7594 goto check_failed; 7595 } 7596 pchunk = pchunk->next; 7597 } 7598 7599 return (0); 7600 7601 check_failed: 7602 7603 return (1); 7604 } 7605 7606 /* 7607 * pmcs_handle_dead_phys 7608 * 7609 * If the PHY has no outstanding work associated with it, remove it from 7610 * the dead PHY list and free it. 7611 * 7612 * If pwp->ds_err_recovering or pwp->configuring is set, don't run. 7613 * This keeps routines that need to submit work to the chip from having to 7614 * hold PHY locks to ensure that PHYs don't disappear while they do their work. 7615 */ 7616 void 7617 pmcs_handle_dead_phys(pmcs_hw_t *pwp) 7618 { 7619 pmcs_phy_t *phyp, *nphyp, *pphyp; 7620 7621 mutex_enter(&pwp->lock); 7622 mutex_enter(&pwp->config_lock); 7623 7624 if (pwp->configuring | pwp->ds_err_recovering) { 7625 mutex_exit(&pwp->config_lock); 7626 mutex_exit(&pwp->lock); 7627 return; 7628 } 7629 7630 /* 7631 * Check every PHY in the dead PHY list 7632 */ 7633 mutex_enter(&pwp->dead_phylist_lock); 7634 phyp = pwp->dead_phys; 7635 pphyp = NULL; /* Set previous PHY to NULL */ 7636 7637 while (phyp != NULL) { 7638 pmcs_lock_phy(phyp); 7639 ASSERT(phyp->dead); 7640 7641 nphyp = phyp->dead_next; 7642 7643 /* 7644 * Check for outstanding work 7645 */ 7646 if (phyp->ref_count > 0) { 7647 pmcs_unlock_phy(phyp); 7648 pphyp = phyp; /* This PHY becomes "previous" */ 7649 } else if (phyp->target) { 7650 pmcs_unlock_phy(phyp); 7651 pmcs_prt(pwp, PMCS_PRT_DEBUG1, phyp, phyp->target, 7652 "%s: Not freeing PHY 0x%p: target 0x%p is not free", 7653 __func__, (void *)phyp, (void *)phyp->target); 7654 pphyp = phyp; 7655 } else { 7656 /* 7657 * No outstanding work or target references. Remove it 7658 * from the list and free it 7659 */ 7660 pmcs_prt(pwp, PMCS_PRT_DEBUG, phyp, phyp->target, 7661 "%s: Freeing inactive dead PHY 0x%p @ %s " 7662 "target = 0x%p", __func__, (void *)phyp, 7663 phyp->path, (void *)phyp->target); 7664 /* 7665 * If pphyp is NULL, then phyp was the head of the list, 7666 * so just reset the head to nphyp. Otherwise, the 7667 * previous PHY will now point to nphyp (the next PHY) 7668 */ 7669 if (pphyp == NULL) { 7670 pwp->dead_phys = nphyp; 7671 } else { 7672 pphyp->dead_next = nphyp; 7673 } 7674 /* 7675 * If the target still points to this PHY, remove 7676 * that linkage now. 7677 */ 7678 if (phyp->target) { 7679 mutex_enter(&phyp->target->statlock); 7680 if (phyp->target->phy == phyp) { 7681 phyp->target->phy = NULL; 7682 } 7683 mutex_exit(&phyp->target->statlock); 7684 } 7685 pmcs_unlock_phy(phyp); 7686 kmem_cache_free(pwp->phy_cache, phyp); 7687 } 7688 7689 phyp = nphyp; 7690 } 7691 7692 mutex_exit(&pwp->dead_phylist_lock); 7693 mutex_exit(&pwp->config_lock); 7694 mutex_exit(&pwp->lock); 7695 } 7696 7697 void 7698 pmcs_inc_phy_ref_count(pmcs_phy_t *phyp) 7699 { 7700 atomic_inc_32(&phyp->ref_count); 7701 } 7702 7703 void 7704 pmcs_dec_phy_ref_count(pmcs_phy_t *phyp) 7705 { 7706 ASSERT(phyp->ref_count != 0); 7707 atomic_dec_32(&phyp->ref_count); 7708 } 7709 7710 /* 7711 * pmcs_reap_dead_phy 7712 * 7713 * This function is called from pmcs_new_tport when we have a PHY 7714 * without a target pointer. It's possible in that case that this PHY 7715 * may have a "brother" on the dead_phys list. That is, it may be the same as 7716 * this one but with a different root PHY number (e.g. pp05 vs. pp04). If 7717 * that's the case, update the dead PHY and this new PHY. If that's not the 7718 * case, we should get a tran_tgt_init on this after it's reported to SCSA. 7719 * 7720 * Called with PHY locked. 7721 */ 7722 static void 7723 pmcs_reap_dead_phy(pmcs_phy_t *phyp) 7724 { 7725 pmcs_hw_t *pwp = phyp->pwp; 7726 pmcs_phy_t *ctmp; 7727 pmcs_iport_t *iport_cmp; 7728 7729 ASSERT(mutex_owned(&phyp->phy_lock)); 7730 7731 /* 7732 * Check the dead PHYs list 7733 */ 7734 mutex_enter(&pwp->dead_phylist_lock); 7735 ctmp = pwp->dead_phys; 7736 while (ctmp) { 7737 /* 7738 * If the iport is NULL, compare against last_iport. 7739 */ 7740 if (ctmp->iport) { 7741 iport_cmp = ctmp->iport; 7742 } else { 7743 iport_cmp = ctmp->last_iport; 7744 } 7745 7746 if ((iport_cmp != phyp->iport) || 7747 (memcmp((void *)&ctmp->sas_address[0], 7748 (void *)&phyp->sas_address[0], 8))) { 7749 ctmp = ctmp->dead_next; 7750 continue; 7751 } 7752 7753 /* 7754 * Same SAS address on same iport. Now check to see if 7755 * the PHY path is the same with the possible exception 7756 * of the root PHY number. 7757 * The "5" is the string length of "pp00." 7758 */ 7759 if ((strnlen(phyp->path, 5) >= 5) && 7760 (strnlen(ctmp->path, 5) >= 5)) { 7761 if (memcmp((void *)&phyp->path[5], 7762 (void *)&ctmp->path[5], 7763 strnlen(phyp->path, 32) - 5) == 0) { 7764 break; 7765 } 7766 } 7767 7768 ctmp = ctmp->dead_next; 7769 } 7770 mutex_exit(&pwp->dead_phylist_lock); 7771 7772 /* 7773 * Found a match. Remove the target linkage and drop the 7774 * ref count on the old PHY. Then, increment the ref count 7775 * on the new PHY to compensate. 7776 */ 7777 if (ctmp) { 7778 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 7779 "%s: Found match in dead PHY list (0x%p) for new PHY %s", 7780 __func__, (void *)ctmp, phyp->path); 7781 /* 7782 * If there is a pointer to the target in the dead PHY, move 7783 * all reference counts to the new PHY. 7784 */ 7785 if (ctmp->target) { 7786 mutex_enter(&ctmp->target->statlock); 7787 phyp->target = ctmp->target; 7788 7789 while (ctmp->ref_count != 0) { 7790 pmcs_inc_phy_ref_count(phyp); 7791 pmcs_dec_phy_ref_count(ctmp); 7792 } 7793 /* 7794 * Update the target's linkage as well 7795 */ 7796 phyp->target->phy = phyp; 7797 phyp->target->dtype = phyp->dtype; 7798 ctmp->target = NULL; 7799 mutex_exit(&phyp->target->statlock); 7800 } 7801 } 7802 } 7803 7804 /* 7805 * Called with iport lock held 7806 */ 7807 void 7808 pmcs_add_phy_to_iport(pmcs_iport_t *iport, pmcs_phy_t *phyp) 7809 { 7810 ASSERT(mutex_owned(&iport->lock)); 7811 ASSERT(phyp); 7812 ASSERT(!list_link_active(&phyp->list_node)); 7813 iport->nphy++; 7814 list_insert_tail(&iport->phys, phyp); 7815 pmcs_smhba_add_iport_prop(iport, DATA_TYPE_INT32, PMCS_NUM_PHYS, 7816 &iport->nphy); 7817 mutex_enter(&iport->refcnt_lock); 7818 iport->refcnt++; 7819 mutex_exit(&iport->refcnt_lock); 7820 } 7821 7822 /* 7823 * Called with the iport lock held 7824 */ 7825 void 7826 pmcs_remove_phy_from_iport(pmcs_iport_t *iport, pmcs_phy_t *phyp) 7827 { 7828 pmcs_phy_t *pptr, *next_pptr; 7829 7830 ASSERT(mutex_owned(&iport->lock)); 7831 7832 /* 7833 * If phyp is NULL, remove all PHYs from the iport 7834 */ 7835 if (phyp == NULL) { 7836 for (pptr = list_head(&iport->phys); pptr != NULL; 7837 pptr = next_pptr) { 7838 next_pptr = list_next(&iport->phys, pptr); 7839 mutex_enter(&pptr->phy_lock); 7840 pptr->iport = NULL; 7841 pmcs_update_phy_pm_props(pptr, pptr->att_port_pm_tmp, 7842 pptr->tgt_port_pm_tmp, B_FALSE); 7843 mutex_exit(&pptr->phy_lock); 7844 pmcs_rele_iport(iport); 7845 list_remove(&iport->phys, pptr); 7846 pmcs_smhba_add_iport_prop(iport, DATA_TYPE_INT32, 7847 PMCS_NUM_PHYS, &iport->nphy); 7848 } 7849 iport->nphy = 0; 7850 return; 7851 } 7852 7853 ASSERT(phyp); 7854 ASSERT(iport->nphy > 0); 7855 ASSERT(list_link_active(&phyp->list_node)); 7856 iport->nphy--; 7857 list_remove(&iport->phys, phyp); 7858 pmcs_update_phy_pm_props(phyp, phyp->att_port_pm_tmp, 7859 phyp->tgt_port_pm_tmp, B_FALSE); 7860 pmcs_smhba_add_iport_prop(iport, DATA_TYPE_INT32, PMCS_NUM_PHYS, 7861 &iport->nphy); 7862 pmcs_rele_iport(iport); 7863 } 7864 7865 /* 7866 * This function checks to see if the target pointed to by phyp is still 7867 * correct. This is done by comparing the target's unit address with the 7868 * SAS address in phyp. 7869 * 7870 * Called with PHY locked and target statlock held 7871 */ 7872 static boolean_t 7873 pmcs_phy_target_match(pmcs_phy_t *phyp) 7874 { 7875 uint64_t wwn; 7876 char unit_address[PMCS_MAX_UA_SIZE]; 7877 boolean_t rval = B_FALSE; 7878 7879 ASSERT(phyp); 7880 ASSERT(phyp->target); 7881 ASSERT(mutex_owned(&phyp->phy_lock)); 7882 ASSERT(mutex_owned(&phyp->target->statlock)); 7883 7884 wwn = pmcs_barray2wwn(phyp->sas_address); 7885 (void) scsi_wwn_to_wwnstr(wwn, 1, unit_address); 7886 7887 if (memcmp((void *)unit_address, (void *)phyp->target->unit_address, 7888 strnlen(phyp->target->unit_address, PMCS_MAX_UA_SIZE)) == 0) { 7889 rval = B_TRUE; 7890 } 7891 7892 return (rval); 7893 } 7894 /* 7895 * Commands used to serialize SMP requests. 7896 * 7897 * The SPC only allows 2 SMP commands per SMP target: 1 cmd pending and 1 cmd 7898 * queued for the same SMP target. If a third SMP cmd is sent to the SPC for an 7899 * SMP target that already has a SMP cmd pending and one queued, then the 7900 * SPC responds with the ERROR_INTERNAL_SMP_RESOURCE response. 7901 * 7902 * Additionally, the SPC has an 8 entry deep cmd queue and the number of SMP 7903 * cmds that can be queued is controlled by the PORT_CONTROL IOMB. The 7904 * SPC default is 1 SMP command/port (iport). These 2 queued SMP cmds would 7905 * have to be for different SMP targets. The INTERNAL_SMP_RESOURCE error will 7906 * also be returned if a 2nd SMP cmd is sent to the controller when there is 7907 * already 1 SMP cmd queued for that port or if a 3rd SMP cmd is sent to the 7908 * queue if there are already 2 queued SMP cmds. 7909 */ 7910 void 7911 pmcs_smp_acquire(pmcs_iport_t *iport) 7912 { 7913 if (iport == NULL) { 7914 return; 7915 } 7916 7917 mutex_enter(&iport->smp_lock); 7918 while (iport->smp_active) { 7919 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_IPORT, NULL, NULL, 7920 "%s: SMP is active on thread 0x%p, waiting", __func__, 7921 (void *)iport->smp_active_thread); 7922 cv_wait(&iport->smp_cv, &iport->smp_lock); 7923 } 7924 iport->smp_active = B_TRUE; 7925 iport->smp_active_thread = curthread; 7926 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG3, NULL, NULL, 7927 "%s: SMP acquired by thread 0x%p", __func__, 7928 (void *)iport->smp_active_thread); 7929 mutex_exit(&iport->smp_lock); 7930 } 7931 7932 void 7933 pmcs_smp_release(pmcs_iport_t *iport) 7934 { 7935 if (iport == NULL) { 7936 return; 7937 } 7938 7939 mutex_enter(&iport->smp_lock); 7940 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG3, NULL, NULL, 7941 "%s: SMP released by thread 0x%p", __func__, (void *)curthread); 7942 iport->smp_active = B_FALSE; 7943 iport->smp_active_thread = NULL; 7944 cv_signal(&iport->smp_cv); 7945 mutex_exit(&iport->smp_lock); 7946 } 7947 7948 /* 7949 * Update a PHY's attached-port-pm and target-port-pm properties 7950 * 7951 * phyp: PHY whose properties are to be updated 7952 * 7953 * att_bv: Bit value of the attached-port-pm property to be updated in the 7954 * 64-bit holding area for the PHY. 7955 * 7956 * tgt_bv: Bit value of the target-port-pm property to update in the 64-bit 7957 * holding area for the PHY. 7958 * 7959 * prop_add_val: If TRUE, we're adding bits into the property value. 7960 * Otherwise, we're taking them out. Either way, the properties for this 7961 * PHY will be updated. 7962 */ 7963 void 7964 pmcs_update_phy_pm_props(pmcs_phy_t *phyp, uint64_t att_bv, uint64_t tgt_bv, 7965 boolean_t prop_add_val) 7966 { 7967 if (prop_add_val) { 7968 /* 7969 * If the values are currently 0, then we're setting the 7970 * phymask for just this PHY as well. 7971 */ 7972 if (phyp->att_port_pm_tmp == 0) { 7973 phyp->att_port_pm = att_bv; 7974 phyp->tgt_port_pm = tgt_bv; 7975 } 7976 phyp->att_port_pm_tmp |= att_bv; 7977 phyp->tgt_port_pm_tmp |= tgt_bv; 7978 (void) snprintf(phyp->att_port_pm_str, PMCS_PM_MAX_NAMELEN, 7979 "%"PRIx64, phyp->att_port_pm_tmp); 7980 (void) snprintf(phyp->tgt_port_pm_str, PMCS_PM_MAX_NAMELEN, 7981 "%"PRIx64, phyp->tgt_port_pm_tmp); 7982 } else { 7983 phyp->att_port_pm_tmp &= ~att_bv; 7984 phyp->tgt_port_pm_tmp &= ~tgt_bv; 7985 if (phyp->att_port_pm_tmp) { 7986 (void) snprintf(phyp->att_port_pm_str, 7987 PMCS_PM_MAX_NAMELEN, "%"PRIx64, 7988 phyp->att_port_pm_tmp); 7989 } else { 7990 phyp->att_port_pm_str[0] = '\0'; 7991 phyp->att_port_pm = 0; 7992 } 7993 if (phyp->tgt_port_pm_tmp) { 7994 (void) snprintf(phyp->tgt_port_pm_str, 7995 PMCS_PM_MAX_NAMELEN, "%"PRIx64, 7996 phyp->tgt_port_pm_tmp); 7997 } else { 7998 phyp->tgt_port_pm_str[0] = '\0'; 7999 phyp->tgt_port_pm = 0; 8000 } 8001 } 8002 8003 if (phyp->target == NULL) { 8004 return; 8005 } 8006 8007 mutex_enter(&phyp->target->statlock); 8008 if (!list_is_empty(&phyp->target->lun_list)) { 8009 pmcs_lun_t *lunp; 8010 8011 lunp = list_head(&phyp->target->lun_list); 8012 while (lunp) { 8013 (void) scsi_device_prop_update_string(lunp->sd, 8014 SCSI_DEVICE_PROP_PATH, 8015 SCSI_ADDR_PROP_ATTACHED_PORT_PM, 8016 phyp->att_port_pm_str); 8017 (void) scsi_device_prop_update_string(lunp->sd, 8018 SCSI_DEVICE_PROP_PATH, 8019 SCSI_ADDR_PROP_TARGET_PORT_PM, 8020 phyp->tgt_port_pm_str); 8021 lunp = list_next(&phyp->target->lun_list, lunp); 8022 } 8023 } else if (phyp->target->smpd) { 8024 (void) smp_device_prop_update_string(phyp->target->smpd, 8025 SCSI_ADDR_PROP_ATTACHED_PORT_PM, 8026 phyp->att_port_pm_str); 8027 (void) smp_device_prop_update_string(phyp->target->smpd, 8028 SCSI_ADDR_PROP_TARGET_PORT_PM, 8029 phyp->tgt_port_pm_str); 8030 } 8031 mutex_exit(&phyp->target->statlock); 8032 } 8033 8034 /* ARGSUSED */ 8035 void 8036 pmcs_deregister_device_work(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 8037 { 8038 pmcs_phy_t *pptr; 8039 8040 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 8041 pmcs_lock_phy(pptr); 8042 if (pptr->deregister_wait) { 8043 pmcs_deregister_device(pwp, pptr); 8044 } 8045 pmcs_unlock_phy(pptr); 8046 } 8047 } 8048 8049 /* 8050 * pmcs_iport_active 8051 * 8052 * Mark this iport as active. Called with the iport lock held. 8053 */ 8054 static void 8055 pmcs_iport_active(pmcs_iport_t *iport) 8056 { 8057 ASSERT(mutex_owned(&iport->lock)); 8058 8059 iport->ua_state = UA_ACTIVE; 8060 iport->smp_active = B_FALSE; 8061 iport->smp_active_thread = NULL; 8062 } 8063 8064 /* ARGSUSED */ 8065 static void 8066 pmcs_tgtmap_activate_cb(void *tgtmap_priv, char *tgt_addr, 8067 scsi_tgtmap_tgt_type_t tgt_type, void **tgt_privp) 8068 { 8069 pmcs_iport_t *iport = (pmcs_iport_t *)tgtmap_priv; 8070 pmcs_hw_t *pwp = iport->pwp; 8071 pmcs_xscsi_t *target; 8072 8073 /* 8074 * Look up the target. If there is one, and it doesn't have a PHY 8075 * pointer, re-establish that linkage here. 8076 */ 8077 mutex_enter(&pwp->lock); 8078 target = pmcs_get_target(iport, tgt_addr, B_FALSE); 8079 mutex_exit(&pwp->lock); 8080 8081 /* 8082 * If we got a target, it will now have a PHY pointer and the PHY 8083 * will point to the target. The PHY will be locked, so we'll need 8084 * to unlock it. 8085 */ 8086 if (target) { 8087 pmcs_unlock_phy(target->phy); 8088 } 8089 8090 /* 8091 * Update config_restart_time so we don't try to restart discovery 8092 * while enumeration is still in progress. 8093 */ 8094 mutex_enter(&pwp->config_lock); 8095 pwp->config_restart_time = ddi_get_lbolt() + 8096 drv_usectohz(PMCS_REDISCOVERY_DELAY); 8097 mutex_exit(&pwp->config_lock); 8098 } 8099 8100 /* ARGSUSED */ 8101 static boolean_t 8102 pmcs_tgtmap_deactivate_cb(void *tgtmap_priv, char *tgt_addr, 8103 scsi_tgtmap_tgt_type_t tgt_type, void *tgt_priv, 8104 scsi_tgtmap_deact_rsn_t tgt_deact_rsn) 8105 { 8106 pmcs_iport_t *iport = (pmcs_iport_t *)tgtmap_priv; 8107 pmcs_phy_t *phyp; 8108 boolean_t rediscover = B_FALSE; 8109 8110 ASSERT(iport); 8111 8112 phyp = pmcs_find_phy_by_sas_address(iport->pwp, iport, NULL, tgt_addr); 8113 if (phyp == NULL) { 8114 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_IPORT, NULL, NULL, 8115 "%s: Couldn't find PHY at %s", __func__, tgt_addr); 8116 return (rediscover); 8117 } 8118 /* phyp is locked */ 8119 8120 if (!phyp->reenumerate && phyp->configured) { 8121 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_CONFIG, phyp, phyp->target, 8122 "%s: PHY @ %s is configured... re-enumerate", __func__, 8123 tgt_addr); 8124 phyp->reenumerate = 1; 8125 } 8126 8127 /* 8128 * Check to see if reenumerate is set, and if so, if we've reached our 8129 * maximum number of retries. 8130 */ 8131 if (phyp->reenumerate) { 8132 if (phyp->enum_attempts == PMCS_MAX_REENUMERATE) { 8133 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_CONFIG, phyp, 8134 phyp->target, 8135 "%s: No more enumeration attempts for %s", __func__, 8136 tgt_addr); 8137 } else { 8138 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_CONFIG, phyp, 8139 phyp->target, "%s: Re-attempt enumeration for %s", 8140 __func__, tgt_addr); 8141 ++phyp->enum_attempts; 8142 rediscover = B_TRUE; 8143 } 8144 8145 phyp->reenumerate = 0; 8146 } 8147 8148 pmcs_unlock_phy(phyp); 8149 8150 mutex_enter(&iport->pwp->config_lock); 8151 iport->pwp->config_restart_time = ddi_get_lbolt() + 8152 drv_usectohz(PMCS_REDISCOVERY_DELAY); 8153 if (rediscover) { 8154 iport->pwp->config_restart = B_TRUE; 8155 } else if (iport->pwp->config_restart == B_TRUE) { 8156 /* 8157 * If we aren't asking for rediscovery because of this PHY, 8158 * check to see if we're already asking for it on behalf of 8159 * some other PHY. If so, we'll want to return TRUE, so reset 8160 * "rediscover" here. 8161 */ 8162 rediscover = B_TRUE; 8163 } 8164 8165 mutex_exit(&iport->pwp->config_lock); 8166 8167 return (rediscover); 8168 } 8169 8170 void 8171 pmcs_status_disposition(pmcs_phy_t *phyp, uint32_t status) 8172 { 8173 ASSERT(phyp); 8174 ASSERT(!mutex_owned(&phyp->phy_lock)); 8175 8176 if (phyp == NULL) { 8177 return; 8178 } 8179 8180 pmcs_lock_phy(phyp); 8181 8182 /* 8183 * XXX: Do we need to call this function from an SSP_EVENT? 8184 */ 8185 8186 switch (status) { 8187 case PMCOUT_STATUS_NO_DEVICE: 8188 case PMCOUT_STATUS_ERROR_HW_TIMEOUT: 8189 case PMCOUT_STATUS_XFER_ERR_BREAK: 8190 case PMCOUT_STATUS_XFER_ERR_PHY_NOT_READY: 8191 case PMCOUT_STATUS_OPEN_CNX_PROTOCOL_NOT_SUPPORTED: 8192 case PMCOUT_STATUS_OPEN_CNX_ERROR_ZONE_VIOLATION: 8193 case PMCOUT_STATUS_OPEN_CNX_ERROR_BREAK: 8194 case PMCOUT_STATUS_OPENCNX_ERROR_BAD_DESTINATION: 8195 case PMCOUT_STATUS_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 8196 case PMCOUT_STATUS_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 8197 case PMCOUT_STATUS_OPEN_CNX_ERROR_WRONG_DESTINATION: 8198 case PMCOUT_STATUS_OPEN_CNX_ERROR_UNKNOWN_ERROR: 8199 case PMCOUT_STATUS_IO_XFER_ERROR_NAK_RECEIVED: 8200 case PMCOUT_STATUS_XFER_ERROR_RX_FRAME: 8201 case PMCOUT_STATUS_IO_XFER_OPEN_RETRY_TIMEOUT: 8202 case PMCOUT_STATUS_ERROR_INTERNAL_SMP_RESOURCE: 8203 case PMCOUT_STATUS_IO_PORT_IN_RESET: 8204 case PMCOUT_STATUS_IO_DS_NON_OPERATIONAL: 8205 case PMCOUT_STATUS_IO_DS_IN_RECOVERY: 8206 case PMCOUT_STATUS_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 8207 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG, phyp, phyp->target, 8208 "%s: status = 0x%x for " SAS_ADDR_FMT ", reenumerate", 8209 __func__, status, SAS_ADDR_PRT(phyp->sas_address)); 8210 phyp->reenumerate = 1; 8211 break; 8212 8213 default: 8214 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG, phyp, phyp->target, 8215 "%s: status = 0x%x for " SAS_ADDR_FMT ", no reenumeration", 8216 __func__, status, SAS_ADDR_PRT(phyp->sas_address)); 8217 break; 8218 } 8219 8220 pmcs_unlock_phy(phyp); 8221 } 8222 8223 /* 8224 * Add the list of PHYs pointed to by phyp to the dead_phys_list 8225 * 8226 * Called with all PHYs in the list locked 8227 */ 8228 static void 8229 pmcs_add_dead_phys(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 8230 { 8231 mutex_enter(&pwp->dead_phylist_lock); 8232 while (phyp) { 8233 pmcs_phy_t *nxt = phyp->sibling; 8234 ASSERT(phyp->dead); 8235 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, phyp, NULL, 8236 "%s: dead PHY 0x%p (%s) (ref_count %d)", __func__, 8237 (void *)phyp, phyp->path, phyp->ref_count); 8238 /* 8239 * Put this PHY on the dead PHY list for the watchdog to 8240 * clean up after any outstanding work has completed. 8241 */ 8242 phyp->dead_next = pwp->dead_phys; 8243 pwp->dead_phys = phyp; 8244 pmcs_unlock_phy(phyp); 8245 phyp = nxt; 8246 } 8247 mutex_exit(&pwp->dead_phylist_lock); 8248 } 8249