1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 1997, 1998, 1999 8 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Bill Paul. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 39 #ifndef _SYS_PCAN_H 40 #define _SYS_PCAN_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #define AN_TIMEOUT 600000 47 48 /* 49 * Size of Aironet I/O space. 50 */ 51 #define AN_IOSIZ 0x40 52 53 #define PCAN_DEVICE_PCI 0x100 54 #define PCAN_DEVICE_PCCARD 0x200 55 56 /* 57 * Hermes register definitions and what little I know about them. 58 */ 59 60 /* 61 * Hermes command/status registers. 62 */ 63 #define AN_COMMAND(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x00 : 0x00) 64 #define AN_PARAM0(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x04 : 0x02) 65 #define AN_PARAM1(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x08 : 0x04) 66 #define AN_PARAM2(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x0c : 0x06) 67 #define AN_STATUS(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x10 : 0x08) 68 #define AN_RESP0(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x14 : 0x0A) 69 #define AN_RESP1(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x18 : 0x0C) 70 #define AN_RESP2(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x1c : 0x0E) 71 #define AN_LINKSTAT(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x20 : 0x10) 72 73 /* 74 * Command register 75 */ 76 #define AN_CMD_BUSY 0x8000 /* busy bit */ 77 #define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */ 78 #define AN_CMD_CODE_MASK 0x003F 79 #define AN_CMD_QUAL_MASK 0x7F00 80 81 /* 82 * Command codes 83 */ 84 #define AN_CMD_NOOP 0x0000 /* no-op */ 85 #define AN_CMD_ENABLE 0x0001 /* enable */ 86 #define AN_CMD_DISABLE 0x0002 /* disable */ 87 #define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */ 88 #define AN_CMD_FW_RESTART 0x0004 /* firmware resrart */ 89 #define AN_CMD_HOST_SLEEP 0x0005 90 #define AN_CMD_MAGIC_PKT 0x0006 91 #define AN_CMD_READCFG 0x0008 92 #define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */ 93 #define AN_CMD_TX 0x000B /* transmit */ 94 #define AN_CMD_DEALLOC_MEM 0x000C 95 #define AN_CMD_NOOP2 0x0010 96 #define AN_CMD_ALLOC_DESC 0x0020 97 #define AN_CMD_ACCESS 0x0021 98 #define AN_CMD_ALLOC_BUF 0x0028 99 #define AN_CMD_PSP_NODES 0x0030 100 #define AN_CMD_SET_PHYREG 0x003E 101 #define AN_CMD_TX_TEST 0x003F 102 #define AN_CMD_SLEEP 0x0085 103 #define AN_CMD_SCAN 0x0103 104 #define AN_CMD_SAVECFG 0x0108 105 106 /* 107 * Reclaim qualifier bit, applicable to the 108 * TX command. 109 */ 110 #define AN_RECLAIM 0x0100 /* reclaim NIC memory */ 111 112 /* 113 * MPI 350 DMA descriptor information 114 */ 115 #define AN_DESCRIPTOR_TX 0x01 116 #define AN_DESCRIPTOR_RX 0x02 117 #define AN_DESCRIPTOR_TXCMP 0x04 118 #define AN_DESCRIPTOR_HOSTWRITE 0x08 119 #define AN_DESCRIPTOR_HOSTREAD 0x10 120 #define AN_DESCRIPTOR_HOSTRW 0x20 121 122 #define AN_MAX_RX_DESC 1 123 #define AN_MAX_TX_DESC 1 124 #define AN_HOSTBUFSIZ 1840 125 126 /* 127 * dma descriptor definition for miniPci card. 128 * the miniPci card only works on x86. 129 */ 130 struct an_card_rid_desc 131 { 132 uint32_t an_rid:16; 133 uint32_t an_len:15; 134 uint32_t an_valid:1; 135 uint64_t an_phys; 136 }; 137 138 struct an_card_rx_desc 139 { 140 uint32_t an_ctrl:15; 141 uint32_t an_done:1; 142 uint32_t an_len:15; 143 uint32_t an_valid:1; 144 uint64_t an_phys; 145 }; 146 147 struct an_card_tx_desc 148 { 149 uint32_t an_offset:15; 150 uint32_t an_eoc:1; 151 uint32_t an_len:15; 152 uint32_t an_valid:1; 153 uint64_t an_phys; 154 }; 155 156 #define AN_MAX_DATALEN 4096 157 #define AN_RID_BUFFER_SIZE AN_MAX_DATALEN 158 #define AN_RX_BUFFER_SIZE AN_HOSTBUFSIZ 159 #define AN_TX_BUFFER_SIZE AN_HOSTBUFSIZ 160 #define AN_HOST_DESC_OFFSET 0x800 161 #define AN_RX_DESC_OFFSET (AN_HOST_DESC_OFFSET + \ 162 sizeof (struct an_card_rid_desc)) 163 #define AN_TX_DESC_OFFSET (AN_RX_DESC_OFFSET + \ 164 (AN_MAX_RX_DESC * sizeof (struct an_card_rx_desc))) 165 166 /* 167 * ACCESS command qualifier bits. 168 */ 169 #define AN_ACCESS_READ 0x0000 170 #define AN_ACCESS_WRITE 0x0100 171 172 /* 173 * PROGRAM command qualifier bits. 174 */ 175 #define AN_PROGRAM_DISABLE 0x0000 176 #define AN_PROGRAM_ENABLE_RAM 0x0100 177 #define AN_PROGRAM_ENABLE_NVRAM 0x0200 178 #define AN_PROGRAM_NVRAM 0x0300 179 180 /* 181 * Status register values 182 */ 183 #define AN_STAT_CMD_CODE 0x003F 184 #define AN_STAT_CMD_RESULT 0x7F00 185 186 /* 187 * Linkstat register 188 */ 189 #define AN_LINKSTAT_ASSOCIATED 0x0400 190 #define AN_LINKSTAT_AUTHFAIL 0x0300 191 #define AN_LINKSTAT_ASSOC_FAIL 0x8400 /* (low byte is reason code) */ 192 #define AN_LINKSTAT_DISASSOC 0x8200 /* (low byte is reason code) */ 193 #define AN_LINKSTAT_DEAUTH 0x8100 /* (low byte is reason code) */ 194 #define AN_LINKSTAT_SYNCLOST_TSF 0x8004 195 #define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003 196 #define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002 197 #define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001 198 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000 199 200 /* 201 * Link stat low byte reason code 202 */ 203 #define AN_LINKSTAT_RC_RESERVED 0 /* Reserved return code */ 204 #define AN_LINKSTAT_RC_NOREASON 1 /* Unspecified reason */ 205 #define AN_LINKSTAT_RC_AUTHINV 2 /* Prev auth invalid */ 206 #define AN_LINKSTAT_RC_DEAUTH 3 /* Deauth due sender leaving */ 207 #define AN_LINKSTAT_RC_NOACT 4 /* Disassociated due inactivity */ 208 #define AN_LINKSTAT_RC_MAXLOAD 5 /* Disassociated due 2many stations */ 209 /* 210 * Class 2 frame received from non-Authenticated station 211 */ 212 #define AN_LINKSTAT_RC_BADCLASS2 6 213 /* 214 * Class 3 frame received from non-Associated station 215 */ 216 #define AN_LINKSTAT_RC_BADCLASS3 7 217 /* 218 * Disassociated because sending station is leaving BSS 219 */ 220 #define AN_LINKSTAT_RC_STATLEAVE 8 221 /* 222 * Station requesting (Re)Association not Authenticated w/responding station 223 */ 224 #define AN_LINKSTAT_RC_NOAUTH 9 225 226 /* 227 * memory handle management registers 228 */ 229 #define AN_RX_FID 0x20 230 #define AN_ALLOC_FID 0x22 231 #define AN_TX_CMP_FID(p) \ 232 (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x1a : 0x24) 233 234 #define AN_INVALID_FID 0xffff /* invalid fid value */ 235 236 /* 237 * Buffer Access Path (BAP) registers. 238 * These are I/O channels. I believe you can use each one for 239 * any desired purpose independently of the other. In general 240 * though, we use BAP1 for reading and writing LTV records and 241 * reading received data frames, and BAP0 for writing transmit 242 * frames. This is a convention though, not a rule. 243 */ 244 #define AN_SEL0 0x18 245 #define AN_SEL1 0x1A 246 #define AN_OFF0 0x1C 247 #define AN_OFF1 0x1E 248 #define AN_DATA0 0x36 249 #define AN_DATA1 0x38 250 #define AN_BAP0 AN_DATA0 251 #define AN_BAP1 AN_DATA1 252 253 #define AN_OFF_BUSY 0x8000 254 #define AN_OFF_ERR 0x4000 255 #define AN_OFF_DONE 0x2000 256 #define AN_OFF_DATAOFF 0x0FFF 257 258 /* 259 * Event registers 260 */ 261 #define AN_EVENT_STAT(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x60 : 0x30) 262 /* 263 * Interrupt enable/disable 264 */ 265 #define AN_INT_EN(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x64 : 0x32) 266 #define AN_EVENT_ACK(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x68 : 0x34) 267 268 /* 269 * Events - AN_EVENT_ACK register only 270 */ 271 #define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */ 272 #define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */ 273 /* Events shared by all 3 event regs: */ 274 #define AN_EV_MIC 0x1000 /* Message Integrity Check */ 275 #define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode */ 276 #define AN_EV_LINKSTAT 0x0080 /* link status available */ 277 #define AN_EV_CMD 0x0010 /* command completed */ 278 #define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */ 279 #define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */ 280 #define AN_EV_TX 0x0002 /* async xmit completed succesfully */ 281 #define AN_EV_RX 0x0001 /* async rx completed */ 282 #define AN_EV_TX_CPY 0x0400 283 284 #define AN_EV_ALL 0xffff /* all events */ 285 #define AN_INTRS(p) \ 286 (p->pcan_device_type == PCAN_DEVICE_PCI ? \ 287 (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC|AN_EV_LINKSTAT|AN_EV_MIC \ 288 |AN_EV_TX_CPY) : \ 289 (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC|AN_EV_LINKSTAT|AN_EV_MIC)) 290 291 /* 292 * Host software registers 293 */ 294 #define AN_SW0(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x50 : 0x28) 295 #define AN_SW1(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x54 : 0x2A) 296 #define AN_SW2(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x58 : 0x2C) 297 #define AN_SW3(p) (p->pcan_device_type == PCAN_DEVICE_PCI ? 0x5c : 0x2E) 298 299 #define AN_CNTL 0x14 300 301 #define AN_CNTL_AUX_ENA 0xC000 302 #define AN_CNTL_AUX_ENA_STAT 0xC000 303 #define AN_CNTL_AUX_DIS_STAT 0x0000 304 #define AN_CNTL_AUX_ENA_CNTL 0x8000 305 #define AN_CNTL_AUX_DIS_CNTL 0x4000 306 307 #define AN_AUX_PAGE 0x3A 308 #define AN_AUX_OFFSET 0x3C 309 #define AN_AUX_DATA 0x3E 310 311 struct an_ltv_gen { 312 uint16_t an_len; 313 uint16_t an_type; 314 uint16_t an_val; 315 }; 316 317 /* 318 * General configuration information. 319 */ 320 #define AN_RID_GENCONFIG 0xFF10 321 struct an_ltv_genconfig { 322 uint16_t an_len; /* 0x00 */ 323 uint16_t an_opmode; /* 0x02 */ 324 uint16_t an_rxmode; /* 0x04 */ 325 uint16_t an_fragthresh; /* 0x06 */ 326 uint16_t an_rtsthresh; /* 0x08 */ 327 uint8_t an_macaddr[6]; /* 0x0A */ 328 uint8_t an_rates[8]; /* 0x10 */ 329 uint16_t an_shortretry_limit; /* 0x18 */ 330 uint16_t an_longretry_limit; /* 0x1A */ 331 uint16_t an_tx_msdu_lifetime; /* 0x1C */ 332 uint16_t an_rx_msdu_lifetime; /* 0x1E */ 333 uint16_t an_stationary; /* 0x20 */ 334 uint16_t an_ordering; /* 0x22 */ 335 uint16_t an_devtype; /* 0x24 */ 336 uint16_t an_rsvd0[5]; /* 0x26 */ 337 /* 338 * Scanning associating. 339 */ 340 uint16_t an_scanmode; /* 0x30 */ 341 uint16_t an_probedelay; /* 0x32 */ 342 uint16_t an_probe_energy_timeout; /* 0x34 */ 343 uint16_t an_probe_response_timeout; /* 0x36 */ 344 uint16_t an_beacon_listen_timeout; /* 0x38 */ 345 uint16_t an_ibss_join_net_timeout; /* 0x3A */ 346 uint16_t an_auth_timeout; /* 0x3C */ 347 uint16_t an_authtype; /* 0x3E */ 348 uint16_t an_assoc_timeout; /* 0x40 */ 349 uint16_t an_specified_ap_timeout; /* 0x42 */ 350 uint16_t an_offline_scan_interval; /* 0x44 */ 351 uint16_t an_offline_scan_duration; /* 0x46 */ 352 uint16_t an_link_loss_delay; /* 0x48 */ 353 uint16_t an_max_beacon_lost_time; /* 0x4A */ 354 uint16_t an_refresh_interval; /* 0x4C */ 355 uint16_t an_rsvd1; /* 0x4E */ 356 /* 357 * Power save operation 358 */ 359 uint16_t an_psave_mode; /* 0x50 */ 360 uint16_t an_sleep_for_dtims; /* 0x52 */ 361 uint16_t an_listen_interval; /* 0x54 */ 362 uint16_t an_fast_listen_interval; /* 0x56 */ 363 uint16_t an_listen_decay; /* 0x58 */ 364 uint16_t an_fast_listen_decay; /* 0x5A */ 365 uint16_t an_rsvd2[2]; /* 0x5C */ 366 /* 367 * Ad-hoc (or AP) operation. 368 */ 369 uint16_t an_beacon_period; /* 0x60 */ 370 uint16_t an_atim_duration; /* 0x62 */ 371 uint16_t an_rsvd3; /* 0x64 */ 372 uint16_t an_ds_channel; /* 0x66 */ 373 uint16_t an_rsvd4; /* 0x68 */ 374 uint16_t an_dtim_period; /* 0x6A */ 375 uint16_t an_rsvd5[2]; /* 0x6C */ 376 /* 377 * Radio operation. 378 */ 379 uint16_t an_radiotype; /* 0x70 */ 380 uint16_t an_diversity; /* 0x72 */ 381 uint16_t an_tx_power; /* 0x74 */ 382 uint16_t an_rss_thresh; /* 0x76 */ 383 uint16_t an_rsvd6[4]; /* 0x78 */ 384 /* 385 * Aironet extensions. 386 */ 387 uint8_t an_nodename[16]; /* 0x80 */ 388 uint16_t an_arl_thresh; /* 0x90 */ 389 uint16_t an_arl_decay; /* 0x92 */ 390 uint16_t an_arl_delay; /* 0x94 */ 391 uint8_t an_rsvd7; /* 0x96 */ 392 uint8_t an_rsvd8; /* 0x97 */ 393 uint8_t an_magic_packet_action; /* 0x98 */ 394 uint8_t an_magic_packet_ctl; /* 0x99 */ 395 uint16_t an_auto_wake; /* 0x9A */ 396 uint16_t an_pad[20]; 397 }; 398 399 #define AN_OPMODE_IBSS_ADHOC 0x0000 400 #define AN_OPMODE_INFR_STATION 0x0001 401 #define AN_OPMODE_AP 0x0002 402 #define AN_OPMODE_AP_REPEATER 0x0003 403 #define AN_OPMODE_UNMODIFIED_PAYLOAD 0x0100 404 #define AN_OPMODE_AIRONET_EXTENSIONS 0x0200 405 #define AN_OPMODE_AP_EXTENSIONS 0x0400 406 407 #define AN_RXMODE_BC_MC_ADDR 0x0000 408 #define AN_RXMODE_BC_ADDR 0x0001 409 #define AN_RXMODE_ADDR 0x0002 410 #define AN_RXMODE_80211_MONITOR_CURBSS 0x0003 411 #define AN_RXMODE_80211_MONITOR_ANYBSS 0x0004 412 #define AN_RXMODE_LAN_MONITOR_CURBSS 0x0005 413 #define AN_RXMODE_NO_8023_HEADER 0x0100 414 #define AN_RXMODE_USE_8023_HEADER 0x0000 415 416 #define AN_RATE_1MBPS 0x0002 417 #define AN_RATE_2MBPS 0x0004 418 #define AN_RATE_5_5MBPS 0x000B 419 #define AN_RATE_11MBPS 0x0016 420 421 #define AN_DEVTYPE_PC4500 0x0065 422 #define AN_DEVTYPE_PC4800 0x006D 423 424 #define AN_SCANMODE_ACTIVE 0x0000 425 #define AN_SCANMODE_PASSIVE 0x0001 426 #define AN_SCANMODE_AIRONET_ACTIVE 0x0002 427 428 #define AN_AUTHTYPE_NONE 0x0000 429 #define AN_AUTHTYPE_OPEN 0x0001 430 #define AN_AUTHTYPE_SHAREDKEY 0x0002 431 #define AN_AUTHTYPE_EXCLUDE_UNENCRYPTED 0x0004 432 #define AN_AUTHTYPE_ENABLEWEP 0x0100 433 #define AN_AUTHTYPE_ALLOW_UNENCRYPTED 0x0200 434 435 #define AN_PSAVE_NONE 0x0000 436 #define AN_PSAVE_CAM 0x0001 437 #define AN_PSAVE_PSP 0x0002 438 #define AN_PSAVE_PSP_CAM 0x0003 439 440 #define AN_RADIOTYPE_80211_FH 0x0001 441 #define AN_RADIOTYPE_80211_DS 0x0002 442 #define AN_RADIOTYPE_LM2000_DS 0x0004 443 444 #define AN_DIVERSITY_FACTORY_DEFAULT 0x0000 445 #define AN_DIVERSITY_ANTENNA_1_ONLY 0x0001 446 #define AN_DIVERSITY_ANTENNA_2_ONLY 0x0002 447 #define AN_DIVERSITY_ANTENNA_1_AND_2 0x0003 448 449 #define AN_TXPOWER_FACTORY_DEFAULT 0x0000 450 #define AN_TXPOWER_50MW 50 451 #define AN_TXPOWER_100MW 100 452 #define AN_TXPOWER_250MW 250 453 454 /* 455 * Valid SSID list. You can specify up to three SSIDs denoting 456 * the service sets that you want to join. The first SSID always 457 * defaults to "tsunami" which is a handy way to detect the 458 * card. 459 */ 460 #define AN_RID_SSIDLIST 0xFF11 461 struct an_ltv_ssidlist { 462 uint16_t an_len; 463 uint16_t an_ssid1_len; 464 char an_ssid1[32]; 465 uint16_t an_ssid2_len; 466 char an_ssid2[32]; 467 uint16_t an_ssid3_len; 468 char an_ssid3[32]; 469 uint8_t an_pad[748]; 470 }; 471 472 #define AN_DEF_SSID_LEN 7 473 #define AN_DEF_SSID "tsunami" 474 475 /* 476 * Valid AP list. 477 */ 478 #define AN_RID_APLIST 0xFF12 479 struct an_ltv_aplist { 480 uint16_t an_len; 481 uint8_t an_ap1[6]; 482 uint8_t an_ap2[6]; 483 uint8_t an_ap3[6]; 484 uint8_t an_ap4[6]; 485 }; 486 487 /* 488 * Driver name. 489 */ 490 #define AN_RID_DRVNAME 0xFF13 491 struct an_ltv_drvname { 492 uint16_t an_len; 493 uint8_t an_drvname[16]; 494 }; 495 496 /* 497 * Frame encapsulation. 498 */ 499 #define AN_RID_ENCAP 0xFF14 500 struct an_rid_encap { 501 uint16_t an_len; 502 uint16_t an_ethertype_default; 503 uint16_t an_action_default; 504 uint16_t an_ethertype0; 505 uint16_t an_action0; 506 uint16_t an_ethertype1; 507 uint16_t an_action1; 508 uint16_t an_ethertype2; 509 uint16_t an_action2; 510 uint16_t an_ethertype3; 511 uint16_t an_action3; 512 uint16_t an_ethertype4; 513 uint16_t an_action4; 514 uint16_t an_ethertype5; 515 uint16_t an_action5; 516 uint16_t an_ethertype6; 517 uint16_t an_action6; 518 }; 519 520 #define AN_ENCAP_ACTION_RX 0x0001 521 #define AN_ENCAP_ACTION_TX 0x0002 522 523 #define AN_RXENCAP_NONE 0x0000 524 #define AN_RXENCAP_RFC1024 0x0001 525 526 #define AN_TXENCAP_RFC1024 0x0000 527 #define AN_TXENCAP_80211 0x0002 528 529 #define AN_RID_WEPKEY 0xFF15 530 #define AN_RID_WEPKEY2 0xFF16 531 struct an_ltv_wepkey { 532 uint16_t an_len; 533 uint16_t an_index; 534 uint8_t an_macaddr[6]; 535 uint16_t an_keylen; /* WEP40: 5, WEP128: 13 bytes */ 536 uint8_t an_key[16]; /* key value */ 537 }; 538 539 #define AN_RID_CRYPT 0xFF18 540 struct an_ltv_crypt { 541 uint16_t an_operation; /* 0: enable 1: disable */ 542 uint8_t an_optionmask[2]; /* 1: WEP40 2: WEP128 */ 543 uint8_t an_filler[8]; /* put struct 6 bytes longer */ 544 }; 545 546 /* 547 * Actual config, same structure as general config (read only). 548 */ 549 #define AN_RID_ACTUALCFG 0xFF20 550 551 /* 552 * Card capabilities (read only). 553 */ 554 #define AN_RID_CAPABILITIES 0xFF00 555 struct an_ltv_caps { 556 uint16_t an_len; 557 uint8_t an_oui[3]; /* 0x02 */ 558 uint8_t an_pad0; /* 0x05 */ 559 uint16_t an_prodnum; /* 0x06 */ 560 uint8_t an_manufname[32]; /* 0x08 */ 561 uint8_t an_prodname[16]; /* 0x28 */ 562 uint8_t an_prodvers[8]; /* 0x38 */ 563 uint8_t an_oemaddr[6]; /* 0x40 */ 564 uint8_t an_aironetaddr[6]; /* 0x46 */ 565 uint16_t an_radiotype; /* 0x4C */ 566 uint16_t an_country; /* 0x4E */ 567 uint8_t an_callid[6]; /* 0x50 */ 568 uint8_t an_supported_rates[8]; /* 0x56 */ 569 uint8_t an_rx_diversity; /* 0x5E */ 570 uint8_t an_tx_diversity; /* 0x5F */ 571 uint16_t an_tx_powerlevels[8]; /* 0x60 */ 572 uint16_t an_hwver; /* 0x70 */ 573 uint16_t an_hwcaps; /* 0x72 */ 574 uint16_t an_temprange; /* 0x74 */ 575 uint16_t an_fwrev; /* 0x76 */ 576 uint16_t an_fwsubrev; /* 0x78 */ 577 uint16_t an_interfacerev; /* 0x7A */ 578 uint16_t an_softcap; /* 0x7C */ 579 uint16_t an_bootblockrev; /* 0x7E */ 580 uint16_t an_requiredhw; /* 0x80 */ 581 uint16_t an_pad; 582 }; 583 584 /* 585 * Access point (read only) 586 */ 587 #define AN_RID_APINFO 0xFF01 588 struct an_ltv_apinfo { 589 uint16_t an_len; 590 uint16_t an_tim_addr; 591 uint16_t an_airo_addr; 592 }; 593 594 /* 595 * Radio info (read only). 596 */ 597 #define AN_RID_RADIOINFO 0xFF02 598 struct an_ltv_radioinfo { 599 uint16_t an_len; 600 /* 601 * some more fields here, waiting for freebsd code update. 602 */ 603 }; 604 605 /* 606 * Status (read only). Note: the manual claims this RID is 108 bytes 607 * long (0x6A is the last datum, which is 2 bytes long) however when 608 * this RID is read from the NIC, it returns a length of 110. To be 609 * on the safe side, this structure is padded with an extra 16-bit 610 * word. (There is a misprint in the manual which says the macaddr 611 * field is 8 bytes long.) 612 * 613 * Also, the channel_set and current_channel fields appear to be 614 * reversed. Either that, or the hop_period field is unused. 615 */ 616 #define AN_RID_STATUS 0xFF50 617 struct an_ltv_status { 618 uint16_t an_len; 619 uint8_t an_macaddr[6]; /* 0x02 */ 620 uint16_t an_opmode; /* 0x08 */ 621 uint16_t an_errcode; /* 0x0A */ 622 uint16_t an_cur_signal_quality; /* 0x0C */ 623 uint16_t an_ssidlen; /* 0x0E */ 624 uint8_t an_ssid[32]; /* 0x10 */ 625 uint8_t an_ap_name[16]; /* 0x30 */ 626 uint8_t an_cur_bssid[6]; /* 0x40 */ 627 uint8_t an_prev_bssid1[6]; /* 0x46 */ 628 uint8_t an_prev_bssid2[6]; /* 0x4C */ 629 uint8_t an_prev_bssid3[6]; /* 0x52 */ 630 uint16_t an_beacon_period; /* 0x58 */ 631 uint16_t an_dtim_period; /* 0x5A */ 632 uint16_t an_atim_duration; /* 0x5C */ 633 uint16_t an_hop_period; /* 0x5E */ 634 uint16_t an_channel_set; /* 0x60 */ 635 uint16_t an_cur_channel; /* 0x62 */ 636 uint16_t an_hops_to_backbone; /* 0x64 */ 637 uint16_t an_ap_total_load; /* 0x66 */ 638 uint16_t an_our_generated_load; /* 0x68 */ 639 uint16_t an_accumulated_arl; /* 0x6A */ 640 uint16_t an_signale_quality; /* 0x6C */ 641 uint16_t an_cur_tx_rate; /* 0x6E */ 642 uint16_t an_ap_device; /* 0x70 */ 643 uint16_t an_normallized_rssi; /* 0x72 */ 644 uint16_t an_short_preamble; /* 0x74 */ 645 uint8_t an_ap_ip_address[4]; /* 0x76 */ 646 uint8_t an_noise_pct; /* 0x7A */ 647 uint8_t an_noise_dbm; /* 0x7B */ 648 uint8_t an_noise_average_pct; /* 0x7C */ 649 uint8_t an_noise_average_dbm; /* 0x7D */ 650 uint8_t an_noise_max_pct; /* 0x7E */ 651 uint8_t an_noise_max_dbm; /* 0x7F */ 652 uint16_t an_load; /* 0x80 */ 653 uint8_t an_carrier[4]; /* 0x82 */ 654 uint16_t an_assoc_status; /* 0x86 */ 655 uint16_t an_pad; 656 }; 657 658 #define AN_STATUS_OPMODE_CONFIGURED 0x0001 659 #define AN_STATUS_OPMODE_MAC_ENABLED 0x0002 660 #define AN_STATUS_OPMODE_RX_ENABLED 0x0004 661 #define AN_STATUS_OPMODE_IN_SYNC 0x0010 662 #define AN_STATUS_OPMODE_ASSOCIATED 0x0020 663 #define AN_STATUS_OPMODE_ERROR 0x8000 664 665 666 /* 667 * Statistics 668 */ 669 #define AN_RID_16BITS_CUM 0xFF60 /* Cumulative 16-bit stats counters */ 670 #define AN_RID_16BITS_DELTA 0xFF61 /* 16-bit stats (since last clear) */ 671 #define AN_RID_16BITS_DELTACLR 0xFF62 /* 16-bit stats, clear on read */ 672 #define AN_RID_32BITS_CUM 0xFF68 /* Cumulative 32-bit stats counters */ 673 #define AN_RID_32BITS_DELTA 0xFF69 /* 32-bit stats (since last clear) */ 674 #define AN_RID_32BITS_DELTACLR 0xFF6A /* 32-bit stats, clear on read */ 675 676 /* 677 * Grrr. The manual says the statistics record is 384 bytes in length, 678 * but the card says the record is 404 bytes. There's some padding left 679 * at the end of this structure to account for any discrepancies. 680 */ 681 struct an_ltv_stats { 682 uint16_t an_len; 683 uint16_t an_rx_overruns; /* 0x02 */ 684 uint16_t an_rx_plcp_csum_errs; /* 0x04 */ 685 uint16_t an_rx_plcp_format_errs; /* 0x06 */ 686 uint16_t an_rx_plcp_len_errs; /* 0x08 */ 687 uint16_t an_rx_mac_crc_errs; /* 0x0A */ 688 uint16_t an_rx_mac_crc_ok; /* 0x0C */ 689 uint16_t an_rx_wep_errs; /* 0x0E */ 690 uint16_t an_rx_wep_ok; /* 0x10 */ 691 uint16_t an_retry_long; /* 0x12 */ 692 uint16_t an_retry_short; /* 0x14 */ 693 uint16_t an_retry_max; /* 0x16 */ 694 uint16_t an_no_ack; /* 0x18 */ 695 uint16_t an_no_cts; /* 0x1A */ 696 uint16_t an_rx_ack_ok; /* 0x1C */ 697 uint16_t an_rx_cts_ok; /* 0x1E */ 698 uint16_t an_tx_ack_ok; /* 0x20 */ 699 uint16_t an_tx_rts_ok; /* 0x22 */ 700 uint16_t an_tx_cts_ok; /* 0x24 */ 701 uint16_t an_tx_lmac_mcasts; /* 0x26 */ 702 uint16_t an_tx_lmac_bcasts; /* 0x28 */ 703 uint16_t an_tx_lmac_ucast_frags; /* 0x2A */ 704 uint16_t an_tx_lmac_ucasts; /* 0x2C */ 705 uint16_t an_tx_beacons; /* 0x2E */ 706 uint16_t an_rx_beacons; /* 0x30 */ 707 uint16_t an_tx_single_cols; /* 0x32 */ 708 uint16_t an_tx_multi_cols; /* 0x34 */ 709 uint16_t an_tx_defers_no; /* 0x36 */ 710 uint16_t an_tx_defers_prot; /* 0x38 */ 711 uint16_t an_tx_defers_energy; /* 0x3A */ 712 uint16_t an_rx_dups; /* 0x3C */ 713 uint16_t an_rx_partial; /* 0x3E */ 714 uint16_t an_tx_too_old; /* 0x40 */ 715 uint16_t an_rx_too_old; /* 0x42 */ 716 uint16_t an_lostsync_max_retries; /* 0x44 */ 717 uint16_t an_lostsync_missed_beacons; /* 0x46 */ 718 uint16_t an_lostsync_arl_exceeded; /* 0x48 */ 719 uint16_t an_lostsync_deauthed; /* 0x4A */ 720 uint16_t an_lostsync_disassociated; /* 0x4C */ 721 uint16_t an_lostsync_tsf_timing; /* 0x4E */ 722 uint16_t an_tx_host_mcasts; /* 0x50 */ 723 uint16_t an_tx_host_bcasts; /* 0x52 */ 724 uint16_t an_tx_host_ucasts; /* 0x54 */ 725 uint16_t an_tx_host_failed; /* 0x56 */ 726 uint16_t an_rx_host_mcasts; /* 0x58 */ 727 uint16_t an_rx_host_bcasts; /* 0x5A */ 728 uint16_t an_rx_host_ucasts; /* 0x5C */ 729 uint16_t an_rx_host_discarded; /* 0x5E */ 730 uint16_t an_tx_hmac_mcasts; /* 0x60 */ 731 uint16_t an_tx_hmac_bcasts; /* 0x62 */ 732 uint16_t an_tx_hmac_ucasts; /* 0x64 */ 733 uint16_t an_tx_hmac_failed; /* 0x66 */ 734 uint16_t an_rx_hmac_mcasts; /* 0x68 */ 735 uint16_t an_rx_hmac_bcasts; /* 0x6A */ 736 uint16_t an_rx_hmac_ucasts; /* 0x6C */ 737 uint16_t an_rx_hmac_discarded; /* 0x6E */ 738 uint16_t an_tx_hmac_accepted; /* 0x70 */ 739 uint16_t an_ssid_mismatches; /* 0x72 */ 740 uint16_t an_ap_mismatches; /* 0x74 */ 741 uint16_t an_rates_mismatches; /* 0x76 */ 742 uint16_t an_auth_rejects; /* 0x78 */ 743 uint16_t an_auth_timeouts; /* 0x7A */ 744 uint16_t an_assoc_rejects; /* 0x7C */ 745 uint16_t an_assoc_timeouts; /* 0x7E */ 746 uint16_t an_reason_outside_table; /* 0x80 */ 747 uint16_t an_reason1; /* 0x82 */ 748 uint16_t an_reason2; /* 0x84 */ 749 uint16_t an_reason3; /* 0x86 */ 750 uint16_t an_reason4; /* 0x88 */ 751 uint16_t an_reason5; /* 0x8A */ 752 uint16_t an_reason6; /* 0x8C */ 753 uint16_t an_reason7; /* 0x8E */ 754 uint16_t an_reason8; /* 0x90 */ 755 uint16_t an_reason9; /* 0x92 */ 756 uint16_t an_reason10; /* 0x94 */ 757 uint16_t an_reason11; /* 0x96 */ 758 uint16_t an_reason12; /* 0x98 */ 759 uint16_t an_reason13; /* 0x9A */ 760 uint16_t an_reason14; /* 0x9C */ 761 uint16_t an_reason15; /* 0x9E */ 762 uint16_t an_reason16; /* 0xA0 */ 763 uint16_t an_reason17; /* 0xA2 */ 764 uint16_t an_reason18; /* 0xA4 */ 765 uint16_t an_reason19; /* 0xA6 */ 766 uint16_t an_rx_mgmt_pkts; /* 0xA8 */ 767 uint16_t an_tx_mgmt_pkts; /* 0xAA */ 768 uint16_t an_rx_refresh_pkts; /* 0xAC */ 769 uint16_t an_tx_refresh_pkts; /* 0xAE */ 770 uint16_t an_rx_poll_pkts; /* 0xB0 */ 771 uint16_t an_tx_poll_pkts; /* 0xB2 */ 772 uint16_t an_host_retries; /* 0xB4 */ 773 uint16_t an_lostsync_hostreq; /* 0xB6 */ 774 uint16_t an_host_tx_bytes; /* 0xB8 */ 775 uint16_t an_host_rx_bytes; /* 0xBA */ 776 uint16_t an_uptime_usecs; /* 0xBC */ 777 uint16_t an_uptime_secs; /* 0xBE */ 778 uint16_t an_lostsync_better_ap; /* 0xC0 */ 779 uint16_t an_privacy_mismatch; /* 0xC2 */ 780 uint16_t an_jammed; /* 0xC4 */ 781 uint16_t an_rx_disc_wep_off; /* 0xC6 */ 782 uint16_t an_phy_ele_mismatch; /* 0xC8 */ 783 uint16_t an_leap_success; /* 0xCA */ 784 uint16_t an_leap_failure; /* 0xCC */ 785 uint16_t an_leap_timeouts; /* 0xCE */ 786 uint16_t an_leap_keylen_fail; /* 0xD0 */ 787 }; 788 789 #define AN_RID_ESSIDLIST_FIRST 0xFF72 790 #define AN_RID_ESSIDLIST_NEXT 0xFF73 791 792 struct an_ltv_scanresult { 793 uint16_t an_len; 794 uint16_t an_index; 795 uint16_t an_radiotype; 796 uint8_t an_bssid[6]; 797 #ifdef _BIG_ENDIAN 798 uint8_t an_ssidlen; 799 uint8_t an_zero; 800 #else 801 uint8_t an_zero; 802 uint8_t an_ssidlen; 803 #endif 804 char an_ssid[32]; 805 uint16_t an_rssi; 806 uint16_t an_cap; 807 uint16_t an_beaconinterval; 808 uint8_t an_rates[8]; 809 struct { 810 uint16_t dwell; 811 uint8_t hopset; 812 uint8_t hoppattern; 813 uint8_t hopindex; 814 uint8_t pad; 815 } an_fh; 816 uint16_t an_dschannel; 817 uint16_t an_atimwindow; 818 }; 819 820 /* 821 * seconds after which the scan item ages 822 */ 823 #define AN_SCAN_TIMEOUT_MAX 30 824 825 /* 826 * threshold of scan result items below which scan will run again. 827 */ 828 #define AN_SCAN_AGAIN_THRESHOLD 5 829 830 typedef struct an_scan_list { 831 struct an_ltv_scanresult an_val; 832 uint32_t an_timeout; 833 list_node_t an_scan_node; 834 } an_scan_list_t; 835 836 /* 837 * Receive frame structure. 838 */ 839 typedef struct an_rxframe { 840 uint32_t an_rx_time; /* 0x00 */ 841 uint16_t an_rx_status; /* 0x04 */ 842 uint16_t an_rx_payload_len; /* 0x06 */ 843 uint8_t an_rsvd0; /* 0x08 */ 844 uint8_t an_rx_signal_strength; /* 0x09 */ 845 uint8_t an_rx_rate; /* 0x0A */ 846 uint8_t an_rx_chan; /* 0x0B */ 847 uint8_t an_rx_assoc_cnt; /* 0x0C */ 848 uint8_t an_rsvd1[3]; /* 0x0D */ 849 uint8_t an_plcp_hdr[4]; /* 0x10 */ 850 uint16_t an_frame_ctl; /* 0x14 */ 851 uint16_t an_duration; /* 0x16 */ 852 uint8_t an_addr1[6]; /* 0x18 */ 853 uint8_t an_addr2[6]; /* 0x1E */ 854 uint8_t an_addr3[6]; /* 0x24 */ 855 uint16_t an_seq_ctl; /* 0x2A */ 856 uint8_t an_addr4[6]; /* 0x2C */ 857 uint16_t an_gaplen; /* 0x32 */ 858 } an_rxfrm_t; 859 860 #define AN_RXGAP_MAX 8 861 862 /* 863 * Transmit frame structure. 864 */ 865 typedef struct an_txframe { 866 uint32_t an_tx_sw; /* 0x00 */ 867 uint16_t an_tx_status; /* 0x04 */ 868 uint16_t an_tx_payload_len; /* 0x06 */ 869 uint16_t an_tx_ctl; /* 0x08 */ 870 uint16_t an_tx_assoc_id; /* 0x0A */ 871 uint16_t an_tx_retry; /* 0x0C */ 872 uint8_t an_tx_assoc_cnt; /* 0x0E */ 873 uint8_t an_tx_rate; /* 0x0F */ 874 uint8_t an_tx_max_long_retries; /* 0x10 */ 875 uint8_t an_tx_max_short_retries; /* 0x11 */ 876 uint8_t an_rsvd0[2]; /* 0x12 */ 877 uint16_t an_frame_ctl; /* 0x14 */ 878 uint16_t an_duration; /* 0x16 */ 879 uint8_t an_addr1[6]; /* 0x18 */ 880 uint8_t an_addr2[6]; /* 0x1E */ 881 uint8_t an_addr3[6]; /* 0x24 */ 882 uint16_t an_seq_ctl; /* 0x2A */ 883 uint8_t an_addr4[6]; /* 0x2C */ 884 uint16_t an_gaplen; /* 0x32 */ 885 } an_txfrm_t; 886 887 typedef struct an_frame { 888 union { 889 an_rxfrm_t rxfrm; 890 an_txfrm_t txfrm; 891 } frm; 892 } an_frm_t; 893 894 #define AN_TXSTAT_EXCESS_RETRY 0x0002 895 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004 896 #define AN_TXSTAT_AID_FAIL 0x0008 897 #define AN_TXSTAT_MAC_DISABLED 0x0010 898 #define AN_TXSTAT_ASSOC_LOST 0x0020 899 900 #define AN_TXCTL_RSVD 0x0001 901 #define AN_TXCTL_TXOK_INTR 0x0002 902 #define AN_TXCTL_TXERR_INTR 0x0004 903 #define AN_TXCTL_HEADER_TYPE 0x0008 904 #define AN_TXCTL_PAYLOAD_TYPE 0x0010 905 #define AN_TXCTL_NORELEASE 0x0020 906 #define AN_TXCTL_NORETRIES 0x0040 907 #define AN_TXCTL_CLEAR_AID 0x0080 908 #define AN_TXCTL_STRICT_ORDER 0x0100 909 #define AN_TXCTL_USE_RTS 0x0200 910 911 #define AN_HEADERTYPE_8023 0x0000 912 #define AN_HEADERTYPE_80211 0x0008 913 914 #define AN_PAYLOADTYPE_ETHER 0x0000 915 #define AN_PAYLOADTYPE_LLC 0x0010 916 917 typedef enum { 918 ANC_RX_OVERRUNS, /* 0x04 */ 919 ANC_RX_PLCP_CSUM_ERRS, /* 0x08 */ 920 ANC_RX_PLCP_FORMAT_ERRS, /* 0x0c */ 921 ANC_RX_PLCP_LEN_ERRS, /* 0x10 */ 922 ANC_RX_MAC_CRC_ERRS, /* 0x14 */ 923 ANC_RX_MAC_CRC_OK, /* 0x18 */ 924 ANC_RX_WEP_ERRS, /* 0x1c */ 925 ANC_RX_WEP_OK, /* 0x20 */ 926 ANC_RETRY_LONG, /* 0x24 */ 927 ANC_RETRY_SHORT, /* 0x28 */ 928 ANC_RETRY_MAX, /* 0x2c */ 929 ANC_NO_ACK, /* 0x30 */ 930 ANC_NO_CTS, /* 0x34 */ 931 ANC_RX_ACK_OK, /* 0x38 */ 932 ANC_RX_CTS_OK, /* 0x3c */ 933 ANC_TX_ACK_OK, /* 0x40 */ 934 ANC_TX_RTS_OK, /* 0x44 */ 935 ANC_TX_CTS_OK, /* 0x48 */ 936 ANC_TX_LMAC_MCASTS, /* 0x4c */ 937 ANC_TX_LMAC_BCASTS, /* 0x50 */ 938 ANC_TX_LMAC_UCAST_FRAGS, /* 0x54 */ 939 ANC_TX_LMAC_UCASTS, /* 0x58 */ 940 ANC_TX_BEACONS, /* 0x5c */ 941 ANC_RX_BEACONS, /* 0x60 */ 942 ANC_TX_SINGLE_COLS, /* 0x64 */ 943 ANC_TX_MULTI_COLS, /* 0x68 */ 944 ANC_TX_DEFERS_NO, /* 0x6c */ 945 ANC_TX_DEFERS_PROT, /* 0x70 */ 946 ANC_TX_DEFERS_ENERGY, /* 0x74 */ 947 ANC_RX_DUPS, /* 0x78 */ 948 ANC_RX_PARTIAL, /* 0x7c */ 949 ANC_TX_TOO_OLD, /* 0x80 */ 950 ANC_RX_TOO_OLD, /* 0x84 */ 951 ANC_LOSTSYNC_MAX_RETRIES, /* 0x88 */ 952 ANC_LOSTSYNC_MISSED_BEACONS, /* 0x8c */ 953 ANC_LOSTSYNC_ARL_EXCEEDED, /* 0x90 */ 954 ANC_LOSTSYNC_DEAUTHED, /* 0x94 */ 955 ANC_LOSTSYNC_DISASSOCIATED, /* 0x98 */ 956 ANC_LOSTSYNC_TSF_TIMING, /* 0x9c */ 957 ANC_TX_HOST_MCASTS, /* 0xa0 */ 958 ANC_TX_HOST_BCASTS, /* 0xa4 */ 959 ANC_TX_HOST_UCASTS, /* 0xa8 */ 960 ANC_TX_HOST_FAILED, /* 0xac */ 961 ANC_RX_HOST_MCASTS, /* 0xb0 */ 962 ANC_RX_HOST_BCASTS, /* 0xb4 */ 963 ANC_RX_HOST_UCASTS, /* 0xb8 */ 964 ANC_RX_HOST_DISCARDED, /* 0xbc */ 965 ANC_TX_HMAC_MCASTS, /* 0xc0 */ 966 ANC_TX_HMAC_BCASTS, /* 0xc4 */ 967 ANC_TX_HMAC_UCASTS, /* 0xc8 */ 968 ANC_TX_HMAC_FAILED, /* 0xcc */ 969 ANC_RX_HMAC_MCASTS, /* 0xd0 */ 970 ANC_RX_HMAC_BCASTS, /* 0xd4 */ 971 ANC_RX_HMAC_UCASTS, /* 0xd8 */ 972 ANC_RX_HMAC_DISCARDED, /* 0xdc */ 973 ANC_TX_HMAC_ACCEPTED, /* 0xe0 */ 974 ANC_SSID_MISMATCHES, /* 0xe4 */ 975 ANC_AP_MISMATCHES, /* 0xe8 */ 976 ANC_RATES_MISMATCHES, /* 0xec */ 977 ANC_AUTH_REJECTS, /* 0xf0 */ 978 ANC_AUTH_TIMEOUTS, /* 0xf4 */ 979 ANC_ASSOC_REJECTS, /* 0xf8 */ 980 ANC_ASSOC_TIMEOUTS, /* 0xfc */ 981 ANC_REASON_OUTSIDE_TABLE, /* 0x100 */ 982 ANC_REASON1, /* 0x104 */ 983 ANC_REASON2, /* 0x108 */ 984 ANC_REASON3, /* 0x10c */ 985 ANC_REASON4, /* 0x110 */ 986 ANC_REASON5, /* 0x114 */ 987 ANC_REASON6, /* 0x118 */ 988 ANC_REASON7, /* 0x11c */ 989 ANC_REASON8, /* 0x120 */ 990 ANC_REASON9, /* 0x124 */ 991 ANC_REASON10, /* 0x128 */ 992 ANC_REASON11, /* 0x12c */ 993 ANC_REASON12, /* 0x130 */ 994 ANC_REASON13, /* 0x134 */ 995 ANC_REASON14, /* 0x138 */ 996 ANC_REASON15, /* 0x13c */ 997 ANC_REASON16, /* 0x140 */ 998 ANC_REASON17, /* 0x144 */ 999 ANC_REASON18, /* 0x148 */ 1000 ANC_REASON19, /* 0x14c */ 1001 ANC_RX_MGMT_PKTS, /* 0x150 */ 1002 ANC_TX_MGMT_PKTS, /* 0x154 */ 1003 ANC_RX_REFRESH_PKTS, /* 0x158 */ 1004 ANC_TX_REFRESH_PKTS, /* 0x15c */ 1005 ANC_RX_POLL_PKTS, /* 0x160 */ 1006 ANC_TX_POLL_PKTS, /* 0x164 */ 1007 ANC_HOST_RETRIES, /* 0x168 */ 1008 ANC_LOSTSYNC_HOSTREQ, /* 0x16c */ 1009 ANC_HOST_TX_BYTES, /* 0x170 */ 1010 ANC_HOST_RX_BYTES, /* 0x174 */ 1011 ANC_UPTIME_USECS, /* 0x178 */ 1012 ANC_UPTIME_SECS, /* 0x17c */ 1013 ANC_LOSTSYNC_BETTER_AP, /* 0x180 */ 1014 ANC_PRIVACY_MISMATCH, /* 0x184 */ 1015 ANC_JAMMED, /* 0x188 */ 1016 ANC_RX_DISC_WEP_OFF, /* 0x18c */ 1017 ANC_PHY_ELE_MISMATCH, /* 0x190 */ 1018 ANC_LEAP_SUCCESS, /* 0x194 */ 1019 ANC_LEAP_FAILURE, /* 0x198 */ 1020 ANC_LEAP_TIMEOUTS, /* 0x19c */ 1021 ANC_LEAP_KEYLEN_FAIL, /* 0x1a0 */ 1022 ANC_STAT_CNT /* - keep it as the last entry */ 1023 } pcan_cntr_offset; 1024 1025 #define AN_TXCTL_80211 (AN_TXCTL_TXOK_INTR | AN_TXCTL_TXERR_INTR | \ 1026 AN_HEADERTYPE_80211 | AN_PAYLOADTYPE_LLC | AN_TXCTL_NORELEASE) 1027 1028 #define AN_TXCTL_8023 (AN_TXCTL_TXOK_INTR | AN_TXCTL_TXERR_INTR |\ 1029 AN_HEADERTYPE_8023 | AN_PAYLOADTYPE_ETHER | AN_TXCTL_NORELEASE) 1030 1031 #define AN_TXGAP_80211 6 1032 #define AN_TXGAP_8023 0 1033 1034 #define AN_NORMAL_RXMODE (AN_RXMODE_BC_MC_ADDR | \ 1035 AN_RXMODE_USE_8023_HEADER) 1036 #define AN_MONITOR_RXMODE (AN_RXMODE_LAN_MONITOR_CURBSS | \ 1037 AN_RXMODE_USE_8023_HEADER) 1038 struct an_802_3_hdr { 1039 uint16_t an_8023_status; 1040 uint16_t an_8023_payload_len; 1041 uint8_t an_8023_dst_addr[6]; 1042 uint8_t an_8023_src_addr[6]; 1043 uint16_t an_8023_dat[3]; /* SNAP header */ 1044 uint16_t an_8023_type; 1045 }; 1046 1047 typedef struct an_snap_hdr { 1048 uint16_t an_snap_dat[3]; /* SNAP header */ 1049 uint16_t an_snap_type; 1050 } pcan_snaphdr_t; 1051 1052 #define AN_TX_RING_CNT 4 1053 #define AN_TX_RING_MASK (4 - 1) 1054 #define AN_INC(x, y) (x) = (x + 1) % (y) 1055 1056 typedef struct an_tx_ring_data { 1057 uint16_t an_tx_fids[AN_TX_RING_CNT]; 1058 uint16_t an_tx_ring[AN_TX_RING_CNT]; 1059 int an_tx_prod; 1060 int an_tx_cons; 1061 kmutex_t an_tx_lock; /* for send only */ 1062 } pcan_txring_t; 1063 1064 #define AN_802_3_OFFSET 0x2E 1065 #define AN_802_11_OFFSET 0x44 1066 #define AN_802_11_OFFSET_RAW 0x3C 1067 1068 #define AN_STAT_BADCRC 0x0001 1069 #define AN_STAT_UNDECRYPTABLE 0x0002 1070 #define AN_STAT_ERRSTAT 0x0003 1071 #define AN_STAT_MAC_PORT 0x0700 1072 #define AN_STAT_1042 0x2000 /* RFC1042 encoded */ 1073 #define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */ 1074 #define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */ 1075 #define AN_RXSTAT_MSG_TYPE 0xE000 1076 1077 #define AN_ENC_TX_802_3 0x00 1078 #define AN_ENC_TX_802_11 0x11 1079 #define AN_ENC_TX_E_II 0x0E 1080 1081 #define AN_ENC_TX_1042 0x00 1082 #define AN_ENC_TX_TUNNEL 0xF8 1083 1084 #define AN_TXCNTL_MACPORT 0x00FF 1085 #define AN_TXCNTL_STRUCTTYPE 0xFF00 1086 1087 /* 1088 * SNAP (sub-network access protocol) constants for transmission 1089 * of IP datagrams over IEEE 802 networks, taken from RFC1042. 1090 * We need these for the LLC/SNAP header fields in the TX/RX frame 1091 * structure. 1092 */ 1093 #define AN_SNAP_K1 0xaa /* assigned global SAP for SNAP */ 1094 #define AN_SNAP_K2 0x00 1095 #define AN_SNAP_CONTROL 0x03 /* unnumbered information format */ 1096 #define AN_SNAP_WORD0 (AN_SNAP_K1 | (AN_SNAP_K1 << 8)) 1097 #define AN_SNAP_WORD1 (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8)) 1098 #define AN_SNAPHDR_LEN 0x6 1099 1100 #define AN_FTYPE_DATA 0x8 1101 #define ETH_HDRLEN (sizeof (struct ether_header)) /* 14 bytes */ 1102 #define MLEN(mp) ((mp)->b_wptr - (mp)->b_rptr) 1103 1104 typedef struct pcan_dma_info { 1105 ddi_dma_handle_t dma_handle; 1106 ddi_acc_handle_t dma_acc_handle; 1107 uint32_t dma_physaddr; 1108 caddr_t dma_virtaddr; 1109 uint_t ncookies; 1110 } pcan_dma_info_t; 1111 1112 #define PCAN_DMA_SYNC(hdl, len, flag) ((void) ddi_dma_sync(hdl, 0, len, (flag))) 1113 1114 /* 1115 * The macinfo is really used as the softstate structure. 1116 * 1117 * pcan_mh - mac_handle_t structure 1118 * pcan_cslock - lock for card services request. Used with pcan_cscv 1119 * pcan_cscv - condition variable to wait for card events 1120 * pcan_chdl - client handle, an uint32_t bit mask encoding for socket, 1121 * function, and client info. 1122 * See cs_priv.h MAKE_CLIENT_HANDLE. 1123 * pcan_log_sock - holds the logical to physical translation for this card. 1124 * Specifically has physical adapter and socket #. 1125 * Socket # is the same as part of the pcan_chdl encoding. 1126 * Physical adapter # is from card service socket impl. 1127 */ 1128 typedef struct pcan_macinfo { 1129 mac_handle_t pcan_mh; 1130 dev_info_t *pcan_dip; 1131 1132 kmutex_t pcan_cslock; /* for card services */ 1133 kcondvar_t pcan_cscv; /* for card services */ 1134 client_handle_t pcan_chdl; /* s,f,c encoding, cs_priv.h */ 1135 map_log_socket_t pcan_log_sock; /* logical/phys socket map */ 1136 int pcan_socket; /* socket number */ 1137 int pcan_config_hi; /* cfttbl index */ 1138 int pcan_config; /* default config index */ 1139 int pcan_vcc; /* vcc level */ 1140 int pcan_iodecode; /* # of address lines */ 1141 int pcan_usewep; 1142 int pcan_reset_delay; 1143 1144 caddr_t pcan_cfg_base; 1145 ddi_acc_handle_t pcan_cfg_handle; 1146 caddr_t pcan_bar0; 1147 ddi_acc_handle_t pcan_handle0; 1148 caddr_t pcan_bar1; 1149 ddi_acc_handle_t pcan_handle1; 1150 caddr_t pcan_bar2; 1151 ddi_acc_handle_t pcan_handle2; 1152 int pcan_device_type; /* pci or pcmcia card */ 1153 1154 uint8_t pcan_mac_addr[ETHERADDRL]; 1155 uint32_t pcan_flag; 1156 uint32_t pcan_reschedule_need; 1157 uint32_t glds_nocarrier; 1158 uint32_t glds_noxmtbuf; 1159 uint32_t glds_norcvbuf; 1160 uint32_t glds_intr; 1161 1162 pcan_dma_info_t pcan_cmd; 1163 pcan_dma_info_t pcan_rx[AN_MAX_RX_DESC]; 1164 pcan_dma_info_t pcan_tx[AN_MAX_TX_DESC]; 1165 1166 kmutex_t pcan_glock; /* generic lock */ 1167 kmutex_t pcan_scanlist_lock; /* scanlist lock */ 1168 pcan_txring_t pcan_txring; 1169 1170 struct an_ltv_ssidlist an_ssidlist; 1171 struct an_ltv_aplist an_aplist; 1172 struct an_ltv_caps an_caps; 1173 struct an_ltv_crypt an_crypt; 1174 struct an_ltv_wepkey an_wepkey[4]; 1175 struct an_ltv_scanresult an_scanresult[32]; 1176 uint16_t an_cur_wepkey; 1177 uint16_t an_scan_num; 1178 timeout_id_t an_scanlist_timeout_id; 1179 list_t an_scan_list; 1180 struct an_ltv_status an_status; 1181 struct an_ltv_genconfig an_config; 1182 struct an_ltv_genconfig an_actual_config; 1183 struct an_ltv_stats an_stats; 1184 uint64_t pcan_cntrs_s[ANC_STAT_CNT]; 1185 1186 ddi_acc_handle_t pcan_port; 1187 ddi_iblock_cookie_t pcan_ib_cookie; 1188 ddi_softintr_t pcan_softint_id; 1189 1190 ddi_softintr_t pcan_info_softint_id; 1191 uint32_t pcan_info_softint_pending; 1192 1193 timeout_id_t pcan_connect_timeout_id; 1194 timeout_id_t pcan_linkdown_timeout_id; 1195 int pcan_badrids_len; 1196 prop_1275_cell_t *pcan_badrids; 1197 } pcan_maci_t; 1198 1199 #define PCAN_IDENT_STRING modldrv.drv_linkinfo 1200 1201 #define HDL(pcan_p) ((pcan_p)->pcan_port) 1202 #define GLD3(pcan_p) ((pcan_p)->pcan_mh) 1203 #define DIP(pcan_p) ((pcan_p)->pcan_dip) 1204 1205 #define PCAN_CARD_INTREN 0x1 1206 #define PCAN_CARD_LINKUP 0x2 1207 #define PCAN_ATTACHED 0x4 1208 #define PCAN_CS_REGISTERED 0x8 1209 #define PCAN_ENABLED 0x10 1210 #define PCAN_CARD_SEND 0x20 1211 #define PCAN_CARD_READY 0x40 1212 #define PCAN_CARD_FAILED 0x80 1213 #define PCAN_PLUMBED 0x100 1214 #define PCAN_SUSPENDED 0x200 1215 1216 #define PCAN_STATE_IDLE 0x1 1217 1218 #define PCAN_NICMEM_SZ (2048) /* 80211MTU set as 1500, so 2k here */ 1219 1220 static int pcan_probe(dev_info_t *dip); 1221 static int pcan_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 1222 static int pcan_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 1223 1224 static int pcan_register_cs(dev_info_t *dip, pcan_maci_t *pcan_p); 1225 static void pcan_unregister_cs(pcan_maci_t *pcan_p); 1226 static void pcan_destroy_locks(pcan_maci_t *pcan_p); 1227 static void pcan_reset_backend(pcan_maci_t *pcan_p, int timeout); 1228 static uint32_t pcan_get_cap(pcan_maci_t *pcan_p); 1229 static int pcan_card_insert(pcan_maci_t *pcan_p); 1230 static int pcan_ev_hdlr(event_t ev, int pri, event_callback_args_t *arg); 1231 static void pcan_card_remove(pcan_maci_t *pcan_p); 1232 static int pcan_init_nicmem(pcan_maci_t *pcan_p); 1233 static void pcan_do_suspend(pcan_maci_t *pcan_p); 1234 1235 /* 1236 * high level device access primitives, glock must held before calling 1237 */ 1238 static uint16_t pcan_set_cmd0(pcan_maci_t *pcan_p, uint16_t cmd, uint16_t p0, 1239 uint16_t p1, uint16_t p2); 1240 static uint16_t pcan_set_cmd(pcan_maci_t *pcan_p, uint16_t cmd, uint16_t param); 1241 static uint16_t pcan_set_ch(pcan_maci_t *, uint16_t, uint16_t, uint16_t); 1242 static int pcan_init_dma_desc(pcan_maci_t *pcan_p); 1243 static int pcan_init_dma(dev_info_t *dip, pcan_maci_t *pcan_p); 1244 static void pcan_free_dma(pcan_maci_t *pcan_p); 1245 static uint16_t pcan_put_ltv(pcan_maci_t *pcan_p, uint16_t len, uint16_t type, 1246 uint16_t *val_p); 1247 static uint16_t pcan_get_ltv(pcan_maci_t *pcan_p, uint16_t len, uint16_t type, 1248 uint16_t *val_p); 1249 #define PCAN_READ_LTV 0 1250 #define PCAN_WRITE_LTV 1 1251 static uint16_t pcan_status_ltv(int rw, pcan_maci_t *pcan_p, 1252 struct an_ltv_status *status_p); 1253 static uint16_t pcan_cfg_ltv(int rw, pcan_maci_t *pcan_p, 1254 struct an_ltv_genconfig *cfg_p); 1255 static uint16_t pcan_cap_ltv(int rw, pcan_maci_t *pcan_p); 1256 static uint16_t pcan_ssid_ltv(int rw, pcan_maci_t *pcan_p); 1257 static uint16_t pcan_aplist_ltv(int rw, pcan_maci_t *pcan_p); 1258 static uint16_t pcan_scanresult_ltv(int rw, pcan_maci_t *pcan_p, uint16_t type, 1259 struct an_ltv_scanresult *scanresult_p); 1260 static uint16_t pcan_wepkey_ltv(int rw, pcan_maci_t *pcan_p); 1261 static uint16_t pcan_rdch0(pcan_maci_t *pcan_p, uint16_t type, uint16_t off, 1262 uint16_t *buf_p, int len, int order); 1263 static uint16_t pcan_wrch1(pcan_maci_t *pcan_p, uint16_t type, uint16_t off, 1264 uint16_t *buf_p, int len, int order); 1265 static int pcan_config_mac(pcan_maci_t *pcan_p); 1266 static void pcan_start_locked(pcan_maci_t *pcan_p); 1267 static void pcan_stop_locked(pcan_maci_t *pcan_p); 1268 static uint16_t pcan_alloc_nicmem(pcan_maci_t *pcan_p, uint16_t len, 1269 uint16_t *id_p); 1270 1271 /* 1272 * Required driver entry points for gld 1273 */ 1274 static int pcan_start(void *); 1275 static void pcan_stop(void *); 1276 static int pcan_saddr(void *, const uint8_t *); 1277 static mblk_t *pcan_tx(void *, mblk_t *); 1278 static int pcan_send(pcan_maci_t *, mblk_t *); 1279 static int pcian_send(pcan_maci_t *, mblk_t *); 1280 static int pcan_prom(void *, boolean_t); 1281 static int pcan_gstat(void *, uint_t, uint64_t *); 1282 static int pcan_sdmulti(void *, boolean_t, const uint8_t *); 1283 static void pcan_ioctl(void *, queue_t *, mblk_t *); 1284 1285 static uint_t pcan_intr(caddr_t arg); 1286 static uint_t pcan_intr_hi(caddr_t arg); 1287 static void pcan_rcv(pcan_maci_t *pcan_p); 1288 static void pcian_rcv(pcan_maci_t *pcan_p); 1289 static uint_t pcan_info_softint(caddr_t arg); 1290 static uint32_t pcan_txdone(pcan_maci_t *pcan_p, uint16_t err); 1291 static int pcan_getset(mblk_t *mp, pcan_maci_t *pcan_p, uint32_t cmd); 1292 static void pcan_wlan_ioctl(pcan_maci_t *pcan_p, queue_t *wq, 1293 mblk_t *mp, uint32_t cmd); 1294 static int pcan_loaddef(pcan_maci_t *pcan_p); 1295 1296 static void pcan_scanlist_timeout(void *); 1297 static void pcan_delete_scan_item(pcan_maci_t *, an_scan_list_t *); 1298 static int pcan_add_scan_item(pcan_maci_t *, struct an_ltv_scanresult); 1299 static void pcan_connect_timeout(void *arg); 1300 1301 #define RDCH0(h, t, o, bufp, l) pcan_rdch0(h, t, o, bufp, l, 1) 1302 #define WRCH1(h, t, o, bufp, l) pcan_wrch1(h, t, o, bufp, l, 1) 1303 #define RDPKT(h, t, o, bufp, l) pcan_rdch0(h, t, o, bufp, l, 0) 1304 #define WRPKT(h, t, o, bufp, l) pcan_wrch1(h, t, o, bufp, l, 0) 1305 1306 #define PCAN_READ(p, o, v) { \ 1307 if (p->pcan_device_type == PCAN_DEVICE_PCI) { \ 1308 uint16_t t = ddi_get16(p->pcan_handle0, \ 1309 (uint16_t *)(p->pcan_bar0 + o)); \ 1310 v = LE_16(t); \ 1311 } else { \ 1312 uint16_t t = csx_Get16(HDL(p), o); \ 1313 v = LE_16(t); \ 1314 }\ 1315 } 1316 #define PCAN_WRITE(p, o, v) { \ 1317 if (p->pcan_device_type == PCAN_DEVICE_PCI) { \ 1318 ddi_put16(p->pcan_handle0, \ 1319 (uint16_t *)(p->pcan_bar0 + o), LE_16(v)); \ 1320 } else { \ 1321 csx_Put16(HDL(p), o, LE_16(v)); \ 1322 }\ 1323 } 1324 #define PCAN_READ_P(p, o, v, h) { \ 1325 if (p->pcan_device_type == PCAN_DEVICE_PCI) { \ 1326 uint16_t t = ddi_get16(p->pcan_handle0, \ 1327 (uint16_t *)(p->pcan_bar0 + o)); \ 1328 *(v) = h ? LE_16(t) : t; \ 1329 } else { \ 1330 uint16_t t = csx_Get16(HDL(p), o); \ 1331 *(v) = h ? LE_16(t) : t; \ 1332 }\ 1333 } 1334 #define PCAN_WRITE_P(p, o, v, h) { \ 1335 if (p->pcan_device_type == PCAN_DEVICE_PCI) { \ 1336 ddi_put16(p->pcan_handle0, (uint16_t *)(p->pcan_bar0 + o), \ 1337 h ? LE_16(*(v)) : (*(v))); \ 1338 } else {\ 1339 csx_Put16(HDL(p), o, h ? LE_16(*(v)) : (*(v))); \ 1340 }\ 1341 } 1342 1343 #ifdef _BIG_ENDIAN 1344 #define PCAN_SWAP16(buf_p, len) { \ 1345 uint16_t pcan_swap_len = len; \ 1346 for (pcan_swap_len = (pcan_swap_len + 1) >> 1; pcan_swap_len; ) { \ 1347 uint16_t val; \ 1348 pcan_swap_len--; \ 1349 val = *((uint16_t *)(buf_p) + pcan_swap_len); \ 1350 *((uint16_t *)(buf_p) + pcan_swap_len) = LE_16(val); \ 1351 } \ 1352 } 1353 #define PCAN_SWAP16_BUF(buf_p) PCAN_SWAP16(buf_p, sizeof (buf_p)) 1354 #else /* _BIG_ENDIAN */ 1355 #define PCAN_SWAP16(buf_p, len) 1356 #define PCAN_SWAP16_BUF(buf_p) 1357 #endif /* _BIG_ENDIAN */ 1358 1359 #define PCAN_ENABLE_INTR(pcan_p) {\ 1360 PCAN_WRITE(pcan_p, AN_INT_EN(pcan_p), AN_INTRS(pcan_p));\ 1361 } 1362 #define PCAN_DISABLE_INTR(pcan_p) { \ 1363 PCAN_WRITE(pcan_p, AN_INT_EN(pcan_p), 0); \ 1364 } 1365 #define PCAN_DISABLE_INTR_CLEAR(pcan_p) { \ 1366 PCAN_WRITE(pcan_p, AN_INT_EN(pcan_p), 0); \ 1367 PCAN_WRITE(pcan_p, AN_EVENT_ACK(pcan_p), 0xffff);\ 1368 } 1369 1370 #define PCAN_AUX_PUT32(p, o, v)\ 1371 ddi_put32(p->pcan_handle2, (uint32_t *)(p->pcan_bar2 + o), v) 1372 #define PCAN_AUX_GET32(p, o, v) {\ 1373 v = ddi_get32(p->pcan_handle2, (uint32_t *)(p->pcan_bar2 + o));\ 1374 } 1375 1376 /* 1377 * 16-bit driver private status code 1378 */ 1379 #define PCAN_SUCCESS 0 1380 #define PCAN_FAIL 1 1381 #define PCAN_TIMEDOUT_CMD 0x10 1382 #define PCAN_TIMEDOUT_ACCESS 0x11 1383 #define PCAN_TIMEDOUT_TARGET 0x12 1384 #define PCAN_BADLEN 0x13 1385 #define PCAN_BADTYPE 0x14 1386 #define PCAN_TIMEDOUT_ALLOC 0x15 1387 1388 #define PCAN_STATUS_MAX 0xffff 1389 1390 #ifdef __cplusplus 1391 } 1392 #endif 1393 1394 #endif /* _SYS_PCAN_H */ 1395