1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 */ 29 30 /* IntelVersion: 1.81 v3_3_14_3_BHSW1 */ 31 32 #ifndef _IGB_PHY_H 33 #define _IGB_PHY_H 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 void e1000_init_phy_ops_generic(struct e1000_hw *hw); 40 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data); 41 void e1000_null_phy_generic(struct e1000_hw *hw); 42 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active); 43 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data); 44 s32 e1000_check_downshift_generic(struct e1000_hw *hw); 45 s32 e1000_check_polarity_m88(struct e1000_hw *hw); 46 s32 e1000_check_polarity_igp(struct e1000_hw *hw); 47 s32 e1000_check_polarity_ife(struct e1000_hw *hw); 48 s32 e1000_check_reset_block_generic(struct e1000_hw *hw); 49 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); 50 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); 51 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); 52 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); 53 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 54 s32 e1000_get_cable_length_m88(struct e1000_hw *hw); 55 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); 56 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw); 57 s32 e1000_get_phy_id(struct e1000_hw *hw); 58 s32 e1000_get_phy_info_igp(struct e1000_hw *hw); 59 s32 e1000_get_phy_info_m88(struct e1000_hw *hw); 60 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); 61 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 62 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); 63 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); 64 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); 65 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); 66 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 67 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); 68 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 69 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); 70 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); 71 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); 72 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); 73 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); 74 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 75 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); 76 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 77 s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 78 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 79 u32 usec_interval, bool *success); 80 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); 81 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); 82 s32 e1000_determine_phy_address(struct e1000_hw *hw); 83 void e1000_power_up_phy_copper(struct e1000_hw *hw); 84 void e1000_power_down_phy_copper(struct e1000_hw *hw); 85 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 86 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 87 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); 88 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); 89 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 90 s32 e1000_check_polarity_82577(struct e1000_hw *hw); 91 s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 92 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 93 s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 94 95 #define E1000_MAX_PHY_ADDR 4 96 97 /* IGP01E1000 Specific Registers */ 98 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 99 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 100 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 101 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 102 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 103 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ 104 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 105 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 106 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 107 #define IGP_PAGE_SHIFT 5 108 #define PHY_REG_MASK 0x1F 109 110 #define HV_INTC_FC_PAGE_START 768 111 #define I82578_ADDR_REG 29 112 #define I82577_ADDR_REG 16 113 #define I82577_CFG_REG 22 114 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 115 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 116 #define I82577_CTRL_REG 23 117 118 /* 82577 specific PHY registers */ 119 #define I82577_PHY_CTRL_2 18 120 #define I82577_PHY_LBK_CTRL 19 121 #define I82577_PHY_STATUS_2 26 122 #define I82577_PHY_DIAG_STATUS 31 123 124 /* I82577 PHY Status 2 */ 125 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 126 #define I82577_PHY_STATUS2_MDIX 0x0800 127 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 128 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 129 #define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100 130 131 /* I82577 PHY Control 2 */ 132 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 133 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 134 135 /* I82577 PHY Diagnostics Status */ 136 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 137 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 138 139 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 140 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 141 142 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 143 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 144 145 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 146 147 /* Enable flexible speed on link-up */ 148 #define IGP01E1000_GMII_FLEX_SPD 0x0010 149 #define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ 150 151 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 152 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 153 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 154 155 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 156 157 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 158 #define IGP01E1000_PSSR_MDIX 0x0800 159 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 160 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 161 162 #define IGP02E1000_PHY_CHANNEL_NUM 4 163 #define IGP02E1000_PHY_AGC_A 0x11B1 164 #define IGP02E1000_PHY_AGC_B 0x12B1 165 #define IGP02E1000_PHY_AGC_C 0x14B1 166 #define IGP02E1000_PHY_AGC_D 0x18B1 167 168 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ 169 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 170 #define IGP02E1000_AGC_RANGE 15 171 172 #define IGP03E1000_PHY_MISC_CTRL 0x1B 173 #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ 174 175 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 176 177 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 178 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 179 #define E1000_KMRNCTRLSTA_REN 0x00200000 180 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 181 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 182 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 183 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 184 185 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 186 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ 187 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ 188 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 189 190 /* IFE PHY Extended Status Control */ 191 #define IFE_PESC_POLARITY_REVERSED 0x0100 192 193 /* IFE PHY Special Control */ 194 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 195 #define IFE_PSC_FORCE_POLARITY 0x0020 196 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 197 198 /* IFE PHY Special Control and LED Control */ 199 #define IFE_PSCL_PROBE_MODE 0x0020 200 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 201 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 202 203 /* IFE PHY MDIX Control */ 204 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 205 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 206 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ 207 208 #ifdef __cplusplus 209 } 210 #endif 211 212 #endif /* _IGB_PHY_H */ 213