1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.71 v2007-12-10_dragonlake5 */ 30 31 #pragma ident "%Z%%M% %I% %E% SMI" 32 33 #include "igb_api.h" 34 #include "igb_phy.h" 35 36 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 37 static void e1000_release_phy(struct e1000_hw *hw); 38 static s32 e1000_acquire_phy(struct e1000_hw *hw); 39 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 40 41 /* Cable length tables */ 42 static const u16 e1000_m88_cable_length_table[] = 43 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 44 45 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 46 (sizeof (e1000_m88_cable_length_table) / \ 47 sizeof (e1000_m88_cable_length_table[0])) 48 49 static const u16 e1000_igp_2_cable_length_table[] = 50 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 51 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 52 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 53 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 54 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 55 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 56 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 57 104, 109, 114, 118, 121, 124}; 58 59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 60 (sizeof (e1000_igp_2_cable_length_table) / \ 61 sizeof (e1000_igp_2_cable_length_table[0])) 62 63 /* 64 * e1000_check_reset_block_generic - Check if PHY reset is blocked 65 * @hw: pointer to the HW structure 66 * 67 * Read the PHY management control register and check whether a PHY reset 68 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 69 * return E1000_BLK_PHY_RESET (12). 70 */ 71 s32 72 e1000_check_reset_block_generic(struct e1000_hw *hw) 73 { 74 u32 manc; 75 76 DEBUGFUNC("e1000_check_reset_block"); 77 78 manc = E1000_READ_REG(hw, E1000_MANC); 79 80 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 81 E1000_BLK_PHY_RESET : E1000_SUCCESS; 82 } 83 84 /* 85 * e1000_get_phy_id - Retrieve the PHY ID and revision 86 * @hw: pointer to the HW structure 87 * 88 * Reads the PHY registers and stores the PHY ID and possibly the PHY 89 * revision in the hardware structure. 90 */ 91 s32 92 e1000_get_phy_id(struct e1000_hw *hw) 93 { 94 struct e1000_phy_info *phy = &hw->phy; 95 s32 ret_val = E1000_SUCCESS; 96 u16 phy_id; 97 98 DEBUGFUNC("e1000_get_phy_id"); 99 100 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id); 101 if (ret_val) 102 goto out; 103 104 phy->id = (u32)(phy_id << 16); 105 usec_delay(20); 106 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id); 107 if (ret_val) 108 goto out; 109 110 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 111 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 112 113 out: 114 return (ret_val); 115 } 116 117 /* 118 * e1000_phy_reset_dsp_generic - Reset PHY DSP 119 * @hw: pointer to the HW structure 120 * 121 * Reset the digital signal processor. 122 */ 123 s32 124 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 125 { 126 s32 ret_val; 127 128 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 129 130 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 131 if (ret_val) 132 goto out; 133 134 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 135 136 out: 137 return (ret_val); 138 } 139 140 /* 141 * e1000_read_phy_reg_mdic - Read MDI control register 142 * @hw: pointer to the HW structure 143 * @offset: register offset to be read 144 * @data: pointer to the read data 145 * 146 * Reads the MDI control regsiter in the PHY at offset and stores the 147 * information read to data. 148 */ 149 s32 150 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 151 { 152 struct e1000_phy_info *phy = &hw->phy; 153 u32 i, mdic = 0; 154 s32 ret_val = E1000_SUCCESS; 155 156 DEBUGFUNC("e1000_read_phy_reg_mdic"); 157 158 if (offset > MAX_PHY_REG_ADDRESS) { 159 DEBUGOUT1("PHY Address %d is out of range\n", offset); 160 ret_val = -E1000_ERR_PARAM; 161 goto out; 162 } 163 164 /* 165 * Set up Op-code, Phy Address, and register offset in the MDI 166 * Control register. The MAC will take care of interfacing with the 167 * PHY to retrieve the desired data. 168 */ 169 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 170 (phy->addr << E1000_MDIC_PHY_SHIFT) | 171 (E1000_MDIC_OP_READ)); 172 173 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 174 175 /* 176 * Poll the ready bit to see if the MDI read completed 177 * Increasing the time out as testing showed failures with 178 * the lower time out 179 */ 180 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 181 usec_delay(50); 182 mdic = E1000_READ_REG(hw, E1000_MDIC); 183 if (mdic & E1000_MDIC_READY) 184 break; 185 } 186 if (!(mdic & E1000_MDIC_READY)) { 187 DEBUGOUT("MDI Read did not complete\n"); 188 ret_val = -E1000_ERR_PHY; 189 goto out; 190 } 191 if (mdic & E1000_MDIC_ERROR) { 192 DEBUGOUT("MDI Error\n"); 193 ret_val = -E1000_ERR_PHY; 194 goto out; 195 } 196 *data = (u16) mdic; 197 198 out: 199 return (ret_val); 200 } 201 202 /* 203 * e1000_write_phy_reg_mdic - Write MDI control register 204 * @hw: pointer to the HW structure 205 * @offset: register offset to write to 206 * @data: data to write to register at offset 207 * 208 * Writes data to MDI control register in the PHY at offset. 209 */ 210 s32 211 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 212 { 213 struct e1000_phy_info *phy = &hw->phy; 214 u32 i, mdic = 0; 215 s32 ret_val = E1000_SUCCESS; 216 217 DEBUGFUNC("e1000_write_phy_reg_mdic"); 218 219 if (offset > MAX_PHY_REG_ADDRESS) { 220 DEBUGOUT1("PHY Address %d is out of range\n", offset); 221 ret_val = -E1000_ERR_PARAM; 222 goto out; 223 } 224 225 /* 226 * Set up Op-code, Phy Address, and register offset in the MDI 227 * Control register. The MAC will take care of interfacing with the 228 * PHY to retrieve the desired data. 229 */ 230 mdic = (((u32)data) | 231 (offset << E1000_MDIC_REG_SHIFT) | 232 (phy->addr << E1000_MDIC_PHY_SHIFT) | 233 (E1000_MDIC_OP_WRITE)); 234 235 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 236 237 /* 238 * Poll the ready bit to see if the MDI read completed 239 * Increasing the time out as testing showed failures with 240 * the lower time out 241 */ 242 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 243 usec_delay(50); 244 mdic = E1000_READ_REG(hw, E1000_MDIC); 245 if (mdic & E1000_MDIC_READY) 246 break; 247 } 248 if (!(mdic & E1000_MDIC_READY)) { 249 DEBUGOUT("MDI Write did not complete\n"); 250 ret_val = -E1000_ERR_PHY; 251 goto out; 252 } 253 if (mdic & E1000_MDIC_ERROR) { 254 DEBUGOUT("MDI Error\n"); 255 ret_val = -E1000_ERR_PHY; 256 goto out; 257 } 258 259 out: 260 return (ret_val); 261 } 262 263 /* 264 * e1000_read_phy_reg_m88 - Read m88 PHY register 265 * @hw: pointer to the HW structure 266 * @offset: register offset to be read 267 * @data: pointer to the read data 268 * 269 * Acquires semaphore, if necessary, then reads the PHY register at offset 270 * and storing the retrieved information in data. Release any acquired 271 * semaphores before exiting. 272 */ 273 s32 274 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 275 { 276 s32 ret_val; 277 278 DEBUGFUNC("e1000_read_phy_reg_m88"); 279 280 ret_val = e1000_acquire_phy(hw); 281 if (ret_val) 282 goto out; 283 284 ret_val = e1000_read_phy_reg_mdic(hw, 285 MAX_PHY_REG_ADDRESS & offset, data); 286 287 e1000_release_phy(hw); 288 289 out: 290 return (ret_val); 291 } 292 293 /* 294 * e1000_write_phy_reg_m88 - Write m88 PHY register 295 * @hw: pointer to the HW structure 296 * @offset: register offset to write to 297 * @data: data to write at register offset 298 * 299 * Acquires semaphore, if necessary, then writes the data to PHY register 300 * at the offset. Release any acquired semaphores before exiting. 301 */ 302 s32 303 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 304 { 305 s32 ret_val; 306 307 DEBUGFUNC("e1000_write_phy_reg_m88"); 308 309 ret_val = e1000_acquire_phy(hw); 310 if (ret_val) 311 goto out; 312 313 ret_val = e1000_write_phy_reg_mdic(hw, 314 MAX_PHY_REG_ADDRESS & offset, data); 315 316 e1000_release_phy(hw); 317 318 out: 319 return (ret_val); 320 } 321 322 /* 323 * e1000_read_phy_reg_igp - Read igp PHY register 324 * @hw: pointer to the HW structure 325 * @offset: register offset to be read 326 * @data: pointer to the read data 327 * 328 * Acquires semaphore, if necessary, then reads the PHY register at offset 329 * and storing the retrieved information in data. Release any acquired 330 * semaphores before exiting. 331 */ 332 s32 333 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 334 { 335 s32 ret_val; 336 337 DEBUGFUNC("e1000_read_phy_reg_igp"); 338 339 ret_val = e1000_acquire_phy(hw); 340 if (ret_val) 341 goto out; 342 343 if (offset > MAX_PHY_MULTI_PAGE_REG) { 344 ret_val = e1000_write_phy_reg_mdic(hw, 345 IGP01E1000_PHY_PAGE_SELECT, (u16)offset); 346 if (ret_val) { 347 e1000_release_phy(hw); 348 goto out; 349 } 350 } 351 352 ret_val = e1000_read_phy_reg_mdic(hw, 353 MAX_PHY_REG_ADDRESS & offset, data); 354 355 e1000_release_phy(hw); 356 357 out: 358 return (ret_val); 359 } 360 361 /* 362 * e1000_write_phy_reg_igp - Write igp PHY register 363 * @hw: pointer to the HW structure 364 * @offset: register offset to write to 365 * @data: data to write at register offset 366 * 367 * Acquires semaphore, if necessary, then writes the data to PHY register 368 * at the offset. Release any acquired semaphores before exiting. 369 */ 370 s32 371 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 372 { 373 s32 ret_val; 374 375 DEBUGFUNC("e1000_write_phy_reg_igp"); 376 377 ret_val = e1000_acquire_phy(hw); 378 if (ret_val) 379 goto out; 380 381 if (offset > MAX_PHY_MULTI_PAGE_REG) { 382 ret_val = e1000_write_phy_reg_mdic(hw, 383 IGP01E1000_PHY_PAGE_SELECT, (u16)offset); 384 if (ret_val) { 385 e1000_release_phy(hw); 386 goto out; 387 } 388 } 389 390 ret_val = e1000_write_phy_reg_mdic(hw, 391 MAX_PHY_REG_ADDRESS & offset, data); 392 393 e1000_release_phy(hw); 394 395 out: 396 return (ret_val); 397 } 398 399 /* 400 * e1000_read_kmrn_reg_generic - Read kumeran register 401 * @hw: pointer to the HW structure 402 * @offset: register offset to be read 403 * @data: pointer to the read data 404 * 405 * Acquires semaphore, if necessary. Then reads the PHY register at offset 406 * using the kumeran interface. The information retrieved is stored in data. 407 * Release any acquired semaphores before exiting. 408 */ 409 s32 410 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 411 { 412 u32 kmrnctrlsta; 413 s32 ret_val; 414 415 DEBUGFUNC("e1000_read_kmrn_reg_generic"); 416 417 ret_val = e1000_acquire_phy(hw); 418 if (ret_val) 419 goto out; 420 421 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 422 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 423 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 424 425 usec_delay(2); 426 427 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 428 *data = (u16)kmrnctrlsta; 429 430 e1000_release_phy(hw); 431 432 out: 433 return (ret_val); 434 } 435 436 /* 437 * e1000_write_kmrn_reg_generic - Write kumeran register 438 * @hw: pointer to the HW structure 439 * @offset: register offset to write to 440 * @data: data to write at register offset 441 * 442 * Acquires semaphore, if necessary. Then write the data to PHY register 443 * at the offset using the kumeran interface. Release any acquired semaphores 444 * before exiting. 445 */ 446 s32 447 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 448 { 449 u32 kmrnctrlsta; 450 s32 ret_val; 451 452 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 453 454 ret_val = e1000_acquire_phy(hw); 455 if (ret_val) 456 goto out; 457 458 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 459 E1000_KMRNCTRLSTA_OFFSET) | data; 460 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 461 462 usec_delay(2); 463 e1000_release_phy(hw); 464 465 out: 466 return (ret_val); 467 } 468 469 /* 470 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 471 * @hw: pointer to the HW structure 472 * 473 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 474 * and downshift values are set also. 475 */ 476 s32 477 e1000_copper_link_setup_m88(struct e1000_hw *hw) 478 { 479 struct e1000_phy_info *phy = &hw->phy; 480 s32 ret_val; 481 u16 phy_data; 482 483 DEBUGFUNC("e1000_copper_link_setup_m88"); 484 485 if (phy->reset_disable) { 486 ret_val = E1000_SUCCESS; 487 goto out; 488 } 489 490 /* Enable CRS on TX. This must be set for half-duplex operation. */ 491 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 492 if (ret_val) 493 goto out; 494 495 /* For newer PHYs this bit is downshift enable */ 496 if (phy->type == e1000_phy_m88) 497 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 498 499 /* 500 * Options: 501 * MDI/MDI-X = 0 (default) 502 * 0 - Auto for all speeds 503 * 1 - MDI mode 504 * 2 - MDI-X mode 505 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 506 */ 507 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 508 509 switch (phy->mdix) { 510 case 1: 511 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 512 break; 513 case 2: 514 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 515 break; 516 case 3: 517 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 518 break; 519 case 0: 520 default: 521 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 522 break; 523 } 524 525 /* 526 * Options: 527 * disable_polarity_correction = 0 (default) 528 * Automatic Correction for Reversed Cable Polarity 529 * 0 - Disabled 530 * 1 - Enabled 531 */ 532 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 533 if (phy->disable_polarity_correction == 1) 534 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 535 536 /* Enable downshift on BM (disabled by default) */ 537 if (phy->type == e1000_phy_bm) 538 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 539 540 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 541 if (ret_val) 542 goto out; 543 544 if ((phy->type == e1000_phy_m88) && 545 (phy->revision < E1000_REVISION_4) && 546 (phy->id != BME1000_E_PHY_ID_R2)) { 547 /* 548 * Force TX_CLK in the Extended PHY Specific Control Register 549 * to 25MHz clock. 550 */ 551 ret_val = e1000_read_phy_reg(hw, 552 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 553 if (ret_val) 554 goto out; 555 556 phy_data |= M88E1000_EPSCR_TX_CLK_25; 557 558 if ((phy->revision == E1000_REVISION_2) && 559 (phy->id == M88E1111_I_PHY_ID)) { 560 /* 82573L PHY - set the downshift counter to 5x. */ 561 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 562 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 563 } else { 564 /* Configure Master and Slave downshift values */ 565 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 566 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 567 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 568 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 569 } 570 ret_val = e1000_write_phy_reg(hw, 571 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 572 if (ret_val) 573 goto out; 574 } 575 576 /* Commit the changes. */ 577 ret_val = e1000_phy_commit(hw); 578 if (ret_val) { 579 DEBUGOUT("Error committing the PHY changes\n"); 580 goto out; 581 } 582 583 out: 584 return (ret_val); 585 } 586 587 /* 588 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 589 * @hw: pointer to the HW structure 590 * 591 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 592 * igp PHY's. 593 */ 594 s32 595 e1000_copper_link_setup_igp(struct e1000_hw *hw) 596 { 597 struct e1000_phy_info *phy = &hw->phy; 598 s32 ret_val; 599 u16 data; 600 601 DEBUGFUNC("e1000_copper_link_setup_igp"); 602 603 if (phy->reset_disable) { 604 ret_val = E1000_SUCCESS; 605 goto out; 606 } 607 608 ret_val = e1000_phy_hw_reset(hw); 609 if (ret_val) { 610 DEBUGOUT("Error resetting the PHY.\n"); 611 goto out; 612 } 613 614 /* Wait 15ms for MAC to configure PHY from NVM settings. */ 615 msec_delay(15); 616 617 /* 618 * The NVM settings will configure LPLU in D3 for 619 * non-IGP1 PHYs. 620 */ 621 if (phy->type == e1000_phy_igp) { 622 /* disable lplu d3 during driver init */ 623 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 624 if (ret_val) { 625 DEBUGOUT("Error Disabling LPLU D3\n"); 626 goto out; 627 } 628 } 629 630 /* disable lplu d0 during driver init */ 631 ret_val = e1000_set_d0_lplu_state(hw, FALSE); 632 if (ret_val) { 633 DEBUGOUT("Error Disabling LPLU D0\n"); 634 goto out; 635 } 636 /* Configure mdi-mdix settings */ 637 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 638 if (ret_val) 639 goto out; 640 641 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 642 643 switch (phy->mdix) { 644 case 1: 645 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 646 break; 647 case 2: 648 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 649 break; 650 case 0: 651 default: 652 data |= IGP01E1000_PSCR_AUTO_MDIX; 653 break; 654 } 655 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 656 if (ret_val) 657 goto out; 658 659 /* set auto-master slave resolution settings */ 660 if (hw->mac.autoneg) { 661 /* 662 * when autonegotiation advertisement is only 1000Mbps then we 663 * should disable SmartSpeed and enable Auto MasterSlave 664 * resolution as hardware default. 665 */ 666 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 667 /* Disable SmartSpeed */ 668 ret_val = e1000_read_phy_reg(hw, 669 IGP01E1000_PHY_PORT_CONFIG, &data); 670 if (ret_val) 671 goto out; 672 673 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 674 ret_val = e1000_write_phy_reg(hw, 675 IGP01E1000_PHY_PORT_CONFIG, data); 676 if (ret_val) 677 goto out; 678 679 /* Set auto Master/Slave resolution process */ 680 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data); 681 if (ret_val) 682 goto out; 683 684 data &= ~CR_1000T_MS_ENABLE; 685 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data); 686 if (ret_val) 687 goto out; 688 } 689 690 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data); 691 if (ret_val) 692 goto out; 693 694 /* load defaults for future use */ 695 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 696 ((data & CR_1000T_MS_VALUE) ? 697 e1000_ms_force_master : 698 e1000_ms_force_slave) : 699 e1000_ms_auto; 700 701 switch (phy->ms_type) { 702 case e1000_ms_force_master: 703 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 704 break; 705 case e1000_ms_force_slave: 706 data |= CR_1000T_MS_ENABLE; 707 data &= ~(CR_1000T_MS_VALUE); 708 break; 709 case e1000_ms_auto: 710 data &= ~CR_1000T_MS_ENABLE; 711 default: 712 break; 713 } 714 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data); 715 if (ret_val) 716 goto out; 717 } 718 719 out: 720 return (ret_val); 721 } 722 723 /* 724 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 725 * @hw: pointer to the HW structure 726 * 727 * Performs initial bounds checking on autoneg advertisement parameter, then 728 * configure to advertise the full capability. Setup the PHY to autoneg 729 * and restart the negotiation process between the link partner. If 730 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 731 */ 732 s32 733 e1000_copper_link_autoneg(struct e1000_hw *hw) 734 { 735 struct e1000_phy_info *phy = &hw->phy; 736 s32 ret_val; 737 u16 phy_ctrl; 738 739 DEBUGFUNC("e1000_copper_link_autoneg"); 740 741 /* 742 * Perform some bounds checking on the autoneg advertisement 743 * parameter. 744 */ 745 phy->autoneg_advertised &= phy->autoneg_mask; 746 747 /* 748 * If autoneg_advertised is zero, we assume it was not defaulted 749 * by the calling code so we set to advertise full capability. 750 */ 751 if (phy->autoneg_advertised == 0) 752 phy->autoneg_advertised = phy->autoneg_mask; 753 754 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 755 ret_val = e1000_phy_setup_autoneg(hw); 756 if (ret_val) { 757 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 758 goto out; 759 } 760 DEBUGOUT("Restarting Auto-Neg\n"); 761 762 /* 763 * Restart auto-negotiation by setting the Auto Neg Enable bit and 764 * the Auto Neg Restart bit in the PHY control register. 765 */ 766 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 767 if (ret_val) 768 goto out; 769 770 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 771 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 772 if (ret_val) 773 goto out; 774 775 /* 776 * Does the user want to wait for Auto-Neg to complete here, or 777 * check at a later time (for example, callback routine). 778 */ 779 if (phy->autoneg_wait_to_complete) { 780 ret_val = e1000_wait_autoneg(hw); 781 if (ret_val) { 782 DEBUGOUT("Error while waiting for " 783 "autoneg to complete\n"); 784 goto out; 785 } 786 } 787 788 hw->mac.get_link_status = TRUE; 789 790 out: 791 return (ret_val); 792 } 793 794 /* 795 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 796 * @hw: pointer to the HW structure 797 * 798 * Reads the MII auto-neg advertisement register and/or the 1000T control 799 * register and if the PHY is already setup for auto-negotiation, then 800 * return successful. Otherwise, setup advertisement and flow control to 801 * the appropriate values for the wanted auto-negotiation. 802 */ 803 s32 804 e1000_phy_setup_autoneg(struct e1000_hw *hw) 805 { 806 struct e1000_phy_info *phy = &hw->phy; 807 s32 ret_val; 808 u16 mii_autoneg_adv_reg; 809 u16 mii_1000t_ctrl_reg = 0; 810 811 DEBUGFUNC("e1000_phy_setup_autoneg"); 812 813 phy->autoneg_advertised &= phy->autoneg_mask; 814 815 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 816 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 817 if (ret_val) 818 goto out; 819 820 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 821 /* Read the MII 1000Base-T Control Register (Address 9). */ 822 ret_val = e1000_read_phy_reg(hw, 823 PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 824 if (ret_val) 825 goto out; 826 } 827 828 /* 829 * Need to parse both autoneg_advertised and fc and set up 830 * the appropriate PHY registers. First we will parse for 831 * autoneg_advertised software override. Since we can advertise 832 * a plethora of combinations, we need to check each bit 833 * individually. 834 */ 835 836 /* 837 * First we clear all the 10/100 mb speed bits in the Auto-Neg 838 * Advertisement Register (Address 4) and the 1000 mb speed bits in 839 * the 1000Base-T Control Register (Address 9). 840 */ 841 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 842 NWAY_AR_100TX_HD_CAPS | 843 NWAY_AR_10T_FD_CAPS | 844 NWAY_AR_10T_HD_CAPS); 845 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 846 847 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 848 849 /* Do we want to advertise 10 Mb Half Duplex? */ 850 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 851 DEBUGOUT("Advertise 10mb Half duplex\n"); 852 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 853 } 854 855 /* Do we want to advertise 10 Mb Full Duplex? */ 856 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 857 DEBUGOUT("Advertise 10mb Full duplex\n"); 858 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 859 } 860 861 /* Do we want to advertise 100 Mb Half Duplex? */ 862 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 863 DEBUGOUT("Advertise 100mb Half duplex\n"); 864 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 865 } 866 867 /* Do we want to advertise 100 Mb Full Duplex? */ 868 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 869 DEBUGOUT("Advertise 100mb Full duplex\n"); 870 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 871 } 872 873 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 874 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) { 875 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 876 } 877 878 /* Do we want to advertise 1000 Mb Full Duplex? */ 879 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 880 DEBUGOUT("Advertise 1000mb Full duplex\n"); 881 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 882 } 883 884 /* 885 * Check for a software override of the flow control settings, and 886 * setup the PHY advertisement registers accordingly. If 887 * auto-negotiation is enabled, then software will have to set the 888 * "PAUSE" bits to the correct value in the Auto-Negotiation 889 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 890 * negotiation. 891 * 892 * The possible values of the "fc" parameter are: 893 * 0: Flow control is completely disabled 894 * 1: Rx flow control is enabled (we can receive pause frames 895 * but not send pause frames). 896 * 2: Tx flow control is enabled (we can send pause frames 897 * but we do not support receiving pause frames). 898 * 3: Both Rx and Tx flow control (symmetric) are enabled. 899 * other: No software override. The flow control configuration 900 * in the EEPROM is used. 901 */ 902 switch (hw->fc.type) { 903 case e1000_fc_none: 904 /* 905 * Flow control (Rx & Tx) is completely disabled by a 906 * software over-ride. 907 */ 908 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 909 break; 910 case e1000_fc_rx_pause: 911 /* 912 * Rx Flow control is enabled, and Tx Flow control is 913 * disabled, by a software over-ride. 914 * 915 * Since there really isn't a way to advertise that we are 916 * capable of Rx Pause ONLY, we will advertise that we 917 * support both symmetric and asymmetric Rx PAUSE. Later 918 * (in e1000_config_fc_after_link_up) we will disable the 919 * hw's ability to send PAUSE frames. 920 */ 921 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 922 break; 923 case e1000_fc_tx_pause: 924 /* 925 * Tx Flow control is enabled, and Rx Flow control is 926 * disabled, by a software over-ride. 927 */ 928 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 929 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 930 break; 931 case e1000_fc_full: 932 /* 933 * Flow control (both Rx and Tx) is enabled by a software 934 * over-ride. 935 */ 936 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 937 break; 938 default: 939 DEBUGOUT("Flow control param set incorrectly\n"); 940 ret_val = -E1000_ERR_CONFIG; 941 goto out; 942 } 943 944 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 945 if (ret_val) 946 goto out; 947 948 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 949 950 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 951 ret_val = e1000_write_phy_reg(hw, 952 PHY_1000T_CTRL, mii_1000t_ctrl_reg); 953 if (ret_val) 954 goto out; 955 } 956 957 out: 958 return (ret_val); 959 } 960 961 /* 962 * e1000_setup_copper_link_generic - Configure copper link settings 963 * @hw: pointer to the HW structure 964 * 965 * Calls the appropriate function to configure the link for auto-neg or forced 966 * speed and duplex. Then we check for link, once link is established calls 967 * to configure collision distance and flow control are called. If link is 968 * not established, we return -E1000_ERR_PHY (-2). 969 */ 970 s32 971 e1000_setup_copper_link_generic(struct e1000_hw *hw) 972 { 973 s32 ret_val; 974 bool link; 975 976 DEBUGFUNC("e1000_setup_copper_link_generic"); 977 978 if (hw->mac.autoneg) { 979 /* 980 * Setup autoneg and flow control advertisement and perform 981 * autonegotiation. 982 */ 983 ret_val = e1000_copper_link_autoneg(hw); 984 if (ret_val) 985 goto out; 986 } else { 987 /* 988 * PHY will be set to 10H, 10F, 100H or 100F 989 * depending on user settings. 990 */ 991 DEBUGOUT("Forcing Speed and Duplex\n"); 992 ret_val = e1000_phy_force_speed_duplex(hw); 993 if (ret_val) { 994 DEBUGOUT("Error Forcing Speed and Duplex\n"); 995 goto out; 996 } 997 } 998 999 /* 1000 * Check link status. Wait up to 100 microseconds for link to become 1001 * valid. 1002 */ 1003 ret_val = e1000_phy_has_link_generic(hw, 1004 COPPER_LINK_UP_LIMIT, 1005 10, 1006 &link); 1007 if (ret_val) 1008 goto out; 1009 1010 if (link) { 1011 DEBUGOUT("Valid link established!!!\n"); 1012 e1000_config_collision_dist_generic(hw); 1013 ret_val = e1000_config_fc_after_link_up_generic(hw); 1014 } else { 1015 DEBUGOUT("Unable to establish link!!!\n"); 1016 } 1017 1018 out: 1019 return (ret_val); 1020 } 1021 1022 /* 1023 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1024 * @hw: pointer to the HW structure 1025 * 1026 * Calls the PHY setup function to force speed and duplex. Clears the 1027 * auto-crossover to force MDI manually. Waits for link and returns 1028 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1029 */ 1030 s32 1031 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1032 { 1033 struct e1000_phy_info *phy = &hw->phy; 1034 s32 ret_val; 1035 u16 phy_data; 1036 bool link; 1037 1038 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1039 1040 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 1041 if (ret_val) 1042 goto out; 1043 1044 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1045 1046 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 1047 if (ret_val) 1048 goto out; 1049 1050 /* 1051 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1052 * forced whenever speed and duplex are forced. 1053 */ 1054 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1055 if (ret_val) 1056 goto out; 1057 1058 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1059 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1060 1061 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1062 if (ret_val) 1063 goto out; 1064 1065 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1066 1067 usec_delay(1); 1068 1069 if (phy->autoneg_wait_to_complete) { 1070 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1071 1072 ret_val = e1000_phy_has_link_generic(hw, 1073 PHY_FORCE_LIMIT, 1074 100000, 1075 &link); 1076 if (ret_val) 1077 goto out; 1078 1079 if (!link) { 1080 DEBUGOUT("Link taking longer than expected.\n"); 1081 } 1082 1083 /* Try once more */ 1084 ret_val = e1000_phy_has_link_generic(hw, 1085 PHY_FORCE_LIMIT, 1086 100000, 1087 &link); 1088 if (ret_val) 1089 goto out; 1090 } 1091 1092 out: 1093 return (ret_val); 1094 } 1095 1096 /* 1097 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1098 * @hw: pointer to the HW structure 1099 * 1100 * Calls the PHY setup function to force speed and duplex. Clears the 1101 * auto-crossover to force MDI manually. Resets the PHY to commit the 1102 * changes. If time expires while waiting for link up, we reset the DSP. 1103 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1104 * successful completion, else return corresponding error code. 1105 */ 1106 s32 1107 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1108 { 1109 struct e1000_phy_info *phy = &hw->phy; 1110 s32 ret_val; 1111 u16 phy_data; 1112 bool link; 1113 1114 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1115 1116 /* 1117 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1118 * forced whenever speed and duplex are forced. 1119 */ 1120 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1121 if (ret_val) 1122 goto out; 1123 1124 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1125 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1126 if (ret_val) 1127 goto out; 1128 1129 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1130 1131 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 1132 if (ret_val) 1133 goto out; 1134 1135 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1136 1137 /* Reset the phy to commit changes. */ 1138 phy_data |= MII_CR_RESET; 1139 1140 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 1141 if (ret_val) 1142 goto out; 1143 1144 usec_delay(1); 1145 1146 if (phy->autoneg_wait_to_complete) { 1147 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1148 1149 ret_val = e1000_phy_has_link_generic(hw, 1150 PHY_FORCE_LIMIT, 1151 100000, 1152 &link); 1153 if (ret_val) 1154 goto out; 1155 1156 if (!link) { 1157 /* 1158 * We didn't get link. 1159 * Reset the DSP and cross our fingers. 1160 */ 1161 ret_val = e1000_write_phy_reg(hw, 1162 M88E1000_PHY_PAGE_SELECT, 1163 0x001d); 1164 if (ret_val) 1165 goto out; 1166 ret_val = e1000_phy_reset_dsp_generic(hw); 1167 if (ret_val) 1168 goto out; 1169 } 1170 1171 /* Try once more */ 1172 ret_val = e1000_phy_has_link_generic(hw, 1173 PHY_FORCE_LIMIT, 1174 100000, 1175 &link); 1176 if (ret_val) 1177 goto out; 1178 } 1179 1180 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1181 if (ret_val) 1182 goto out; 1183 1184 /* 1185 * Resetting the phy means we need to re-force TX_CLK in the 1186 * Extended PHY Specific Control Register to 25MHz clock from 1187 * the reset value of 2.5MHz. 1188 */ 1189 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1190 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1191 if (ret_val) 1192 goto out; 1193 1194 /* 1195 * In addition, we must re-enable CRS on Tx for both half and full 1196 * duplex. 1197 */ 1198 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1199 if (ret_val) 1200 goto out; 1201 1202 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1203 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1204 1205 out: 1206 return (ret_val); 1207 } 1208 1209 /* 1210 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1211 * @hw: pointer to the HW structure 1212 * @phy_ctrl: pointer to current value of PHY_CONTROL 1213 * 1214 * Forces speed and duplex on the PHY by doing the following: disable flow 1215 * control, force speed/duplex on the MAC, disable auto speed detection, 1216 * disable auto-negotiation, configure duplex, configure speed, configure 1217 * the collision distance, write configuration to CTRL register. The 1218 * caller must write to the PHY_CONTROL register for these settings to 1219 * take affect. 1220 */ 1221 void 1222 e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1223 { 1224 struct e1000_mac_info *mac = &hw->mac; 1225 u32 ctrl; 1226 1227 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1228 1229 /* Turn off flow control when forcing speed/duplex */ 1230 hw->fc.type = e1000_fc_none; 1231 1232 /* Force speed/duplex on the mac */ 1233 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1234 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1235 ctrl &= ~E1000_CTRL_SPD_SEL; 1236 1237 /* Disable Auto Speed Detection */ 1238 ctrl &= ~E1000_CTRL_ASDE; 1239 1240 /* Disable autoneg on the phy */ 1241 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1242 1243 /* Forcing Full or Half Duplex? */ 1244 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1245 ctrl &= ~E1000_CTRL_FD; 1246 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1247 DEBUGOUT("Half Duplex\n"); 1248 } else { 1249 ctrl |= E1000_CTRL_FD; 1250 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1251 DEBUGOUT("Full Duplex\n"); 1252 } 1253 1254 /* Forcing 10mb or 100mb? */ 1255 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1256 ctrl |= E1000_CTRL_SPD_100; 1257 *phy_ctrl |= MII_CR_SPEED_100; 1258 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1259 DEBUGOUT("Forcing 100mb\n"); 1260 } else { 1261 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1262 /* LINTED */ 1263 *phy_ctrl |= MII_CR_SPEED_10; 1264 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1265 DEBUGOUT("Forcing 10mb\n"); 1266 } 1267 1268 e1000_config_collision_dist_generic(hw); 1269 1270 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1271 } 1272 1273 /* 1274 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1275 * @hw: pointer to the HW structure 1276 * @active: boolean used to enable/disable lplu 1277 * 1278 * Success returns 0, Failure returns 1 1279 * 1280 * The low power link up (lplu) state is set to the power management level D3 1281 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1282 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1283 * is used during Dx states where the power conservation is most important. 1284 * During driver activity, SmartSpeed should be enabled so performance is 1285 * maintained. 1286 */ 1287 s32 1288 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1289 { 1290 struct e1000_phy_info *phy = &hw->phy; 1291 s32 ret_val; 1292 u16 data; 1293 1294 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1295 1296 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1297 if (ret_val) 1298 goto out; 1299 1300 if (!active) { 1301 data &= ~IGP02E1000_PM_D3_LPLU; 1302 ret_val = e1000_write_phy_reg(hw, 1303 IGP02E1000_PHY_POWER_MGMT, 1304 data); 1305 if (ret_val) 1306 goto out; 1307 /* 1308 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1309 * during Dx states where the power conservation is most 1310 * important. During driver activity we should enable 1311 * SmartSpeed, so performance is maintained. 1312 */ 1313 if (phy->smart_speed == e1000_smart_speed_on) { 1314 ret_val = e1000_read_phy_reg(hw, 1315 IGP01E1000_PHY_PORT_CONFIG, 1316 &data); 1317 if (ret_val) 1318 goto out; 1319 1320 data |= IGP01E1000_PSCFR_SMART_SPEED; 1321 ret_val = e1000_write_phy_reg(hw, 1322 IGP01E1000_PHY_PORT_CONFIG, 1323 data); 1324 if (ret_val) 1325 goto out; 1326 } else if (phy->smart_speed == e1000_smart_speed_off) { 1327 ret_val = e1000_read_phy_reg(hw, 1328 IGP01E1000_PHY_PORT_CONFIG, 1329 &data); 1330 if (ret_val) 1331 goto out; 1332 1333 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1334 ret_val = e1000_write_phy_reg(hw, 1335 IGP01E1000_PHY_PORT_CONFIG, 1336 data); 1337 if (ret_val) 1338 goto out; 1339 } 1340 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1341 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1342 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1343 data |= IGP02E1000_PM_D3_LPLU; 1344 ret_val = e1000_write_phy_reg(hw, 1345 IGP02E1000_PHY_POWER_MGMT, 1346 data); 1347 if (ret_val) 1348 goto out; 1349 1350 /* When LPLU is enabled, we should disable SmartSpeed */ 1351 ret_val = e1000_read_phy_reg(hw, 1352 IGP01E1000_PHY_PORT_CONFIG, 1353 &data); 1354 if (ret_val) 1355 goto out; 1356 1357 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1358 ret_val = e1000_write_phy_reg(hw, 1359 IGP01E1000_PHY_PORT_CONFIG, 1360 data); 1361 } 1362 1363 out: 1364 return (ret_val); 1365 } 1366 1367 /* 1368 * e1000_check_downshift_generic - Checks whether a downshift in speed occured 1369 * @hw: pointer to the HW structure 1370 * 1371 * Success returns 0, Failure returns 1 1372 * 1373 * A downshift is detected by querying the PHY link health. 1374 */ 1375 s32 1376 e1000_check_downshift_generic(struct e1000_hw *hw) 1377 { 1378 struct e1000_phy_info *phy = &hw->phy; 1379 s32 ret_val; 1380 u16 phy_data, offset, mask; 1381 1382 DEBUGFUNC("e1000_check_downshift_generic"); 1383 1384 switch (phy->type) { 1385 case e1000_phy_m88: 1386 case e1000_phy_gg82563: 1387 case e1000_phy_bm: 1388 offset = M88E1000_PHY_SPEC_STATUS; 1389 mask = M88E1000_PSSR_DOWNSHIFT; 1390 break; 1391 case e1000_phy_igp_2: 1392 case e1000_phy_igp: 1393 case e1000_phy_igp_3: 1394 offset = IGP01E1000_PHY_LINK_HEALTH; 1395 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1396 break; 1397 default: 1398 /* speed downshift not supported */ 1399 phy->speed_downgraded = FALSE; 1400 ret_val = E1000_SUCCESS; 1401 goto out; 1402 } 1403 1404 ret_val = e1000_read_phy_reg(hw, offset, &phy_data); 1405 1406 if (!ret_val) 1407 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1408 1409 out: 1410 return (ret_val); 1411 } 1412 1413 /* 1414 * e1000_check_polarity_m88 - Checks the polarity. 1415 * @hw: pointer to the HW structure 1416 * 1417 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1418 * 1419 * Polarity is determined based on the PHY specific status register. 1420 */ 1421 s32 1422 e1000_check_polarity_m88(struct e1000_hw *hw) 1423 { 1424 struct e1000_phy_info *phy = &hw->phy; 1425 s32 ret_val; 1426 u16 data; 1427 1428 DEBUGFUNC("e1000_check_polarity_m88"); 1429 1430 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1431 1432 if (!ret_val) 1433 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1434 ? e1000_rev_polarity_reversed 1435 : e1000_rev_polarity_normal; 1436 1437 return (ret_val); 1438 } 1439 1440 /* 1441 * e1000_check_polarity_igp - Checks the polarity. 1442 * @hw: pointer to the HW structure 1443 * 1444 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1445 * 1446 * Polarity is determined based on the PHY port status register, and the 1447 * current speed (since there is no polarity at 100Mbps). 1448 */ 1449 s32 1450 e1000_check_polarity_igp(struct e1000_hw *hw) 1451 { 1452 struct e1000_phy_info *phy = &hw->phy; 1453 s32 ret_val; 1454 u16 data, offset, mask; 1455 1456 DEBUGFUNC("e1000_check_polarity_igp"); 1457 1458 /* 1459 * Polarity is determined based on the speed of 1460 * our connection. 1461 */ 1462 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1463 if (ret_val) 1464 goto out; 1465 1466 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1467 IGP01E1000_PSSR_SPEED_1000MBPS) { 1468 offset = IGP01E1000_PHY_PCS_INIT_REG; 1469 mask = IGP01E1000_PHY_POLARITY_MASK; 1470 } else { 1471 /* 1472 * This really only applies to 10Mbps since 1473 * there is no polarity for 100Mbps (always 0). 1474 */ 1475 offset = IGP01E1000_PHY_PORT_STATUS; 1476 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1477 } 1478 1479 ret_val = e1000_read_phy_reg(hw, offset, &data); 1480 1481 if (!ret_val) 1482 phy->cable_polarity = (data & mask) 1483 ? e1000_rev_polarity_reversed 1484 : e1000_rev_polarity_normal; 1485 1486 out: 1487 return (ret_val); 1488 } 1489 1490 /* 1491 * e1000_wait_autoneg_generic - Wait for auto-neg compeletion 1492 * @hw: pointer to the HW structure 1493 * 1494 * Waits for auto-negotiation to complete or for the auto-negotiation time 1495 * limit to expire, which ever happens first. 1496 */ 1497 s32 1498 e1000_wait_autoneg_generic(struct e1000_hw *hw) 1499 { 1500 s32 ret_val = E1000_SUCCESS; 1501 u16 i, phy_status; 1502 1503 DEBUGFUNC("e1000_wait_autoneg_generic"); 1504 1505 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1506 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1507 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1508 if (ret_val) 1509 break; 1510 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1511 if (ret_val) 1512 break; 1513 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1514 break; 1515 msec_delay(100); 1516 } 1517 1518 /* 1519 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1520 * has completed. 1521 */ 1522 return (ret_val); 1523 } 1524 1525 /* 1526 * e1000_phy_has_link_generic - Polls PHY for link 1527 * @hw: pointer to the HW structure 1528 * @iterations: number of times to poll for link 1529 * @usec_interval: delay between polling attempts 1530 * @success: pointer to whether polling was successful or not 1531 * 1532 * Polls the PHY status register for link, 'iterations' number of times. 1533 */ 1534 s32 1535 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1536 u32 usec_interval, bool *success) 1537 { 1538 s32 ret_val = E1000_SUCCESS; 1539 u16 i, phy_status; 1540 1541 DEBUGFUNC("e1000_phy_has_link_generic"); 1542 1543 for (i = 0; i < iterations; i++) { 1544 /* 1545 * Some PHYs require the PHY_STATUS register to be read 1546 * twice due to the link bit being sticky. No harm doing 1547 * it across the board. 1548 */ 1549 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1550 if (ret_val) 1551 break; 1552 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1553 if (ret_val) 1554 break; 1555 if (phy_status & MII_SR_LINK_STATUS) 1556 break; 1557 if (usec_interval >= 1000) 1558 msec_delay_irq(usec_interval/1000); 1559 else 1560 usec_delay(usec_interval); 1561 } 1562 1563 *success = (i < iterations) ? TRUE : FALSE; 1564 1565 return (ret_val); 1566 } 1567 1568 /* 1569 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1570 * @hw: pointer to the HW structure 1571 * 1572 * Reads the PHY specific status register to retrieve the cable length 1573 * information. The cable length is determined by averaging the minimum and 1574 * maximum values to get the "average" cable length. The m88 PHY has four 1575 * possible cable length values, which are: 1576 * Register Value Cable Length 1577 * 0 < 50 meters 1578 * 1 50 - 80 meters 1579 * 2 80 - 110 meters 1580 * 3 110 - 140 meters 1581 * 4 > 140 meters 1582 */ 1583 s32 1584 e1000_get_cable_length_m88(struct e1000_hw *hw) 1585 { 1586 struct e1000_phy_info *phy = &hw->phy; 1587 s32 ret_val; 1588 u16 phy_data, index; 1589 1590 DEBUGFUNC("e1000_get_cable_length_m88"); 1591 1592 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1593 if (ret_val) 1594 goto out; 1595 1596 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1597 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1598 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1599 phy->max_cable_length = e1000_m88_cable_length_table[index+1]; 1600 1601 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1602 1603 out: 1604 return (ret_val); 1605 } 1606 1607 /* 1608 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1609 * @hw: pointer to the HW structure 1610 * 1611 * The automatic gain control (agc) normalizes the amplitude of the 1612 * received signal, adjusting for the attenuation produced by the 1613 * cable. By reading the AGC registers, which reperesent the 1614 * cobination of course and fine gain value, the value can be put 1615 * into a lookup table to obtain the approximate cable length 1616 * for each channel. 1617 */ 1618 s32 1619 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 1620 { 1621 struct e1000_phy_info *phy = &hw->phy; 1622 s32 ret_val = E1000_SUCCESS; 1623 u16 phy_data, i, agc_value = 0; 1624 u16 cur_agc_index, max_agc_index = 0; 1625 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1626 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 1627 {IGP02E1000_PHY_AGC_A, 1628 IGP02E1000_PHY_AGC_B, 1629 IGP02E1000_PHY_AGC_C, 1630 IGP02E1000_PHY_AGC_D}; 1631 1632 DEBUGFUNC("e1000_get_cable_length_igp_2"); 1633 1634 /* Read the AGC registers for all channels */ 1635 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1636 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 1637 if (ret_val) 1638 goto out; 1639 1640 /* 1641 * Getting bits 15:9, which represent the combination of 1642 * course and fine gain values. The result is a number 1643 * that can be put into the lookup table to obtain the 1644 * approximate cable length. 1645 */ 1646 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1647 IGP02E1000_AGC_LENGTH_MASK; 1648 1649 /* Array index bound check. */ 1650 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1651 (cur_agc_index == 0)) { 1652 ret_val = -E1000_ERR_PHY; 1653 goto out; 1654 } 1655 1656 /* Remove min & max AGC values from calculation. */ 1657 if (e1000_igp_2_cable_length_table[min_agc_index] > 1658 e1000_igp_2_cable_length_table[cur_agc_index]) 1659 min_agc_index = cur_agc_index; 1660 if (e1000_igp_2_cable_length_table[max_agc_index] < 1661 e1000_igp_2_cable_length_table[cur_agc_index]) 1662 max_agc_index = cur_agc_index; 1663 1664 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1665 } 1666 1667 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1668 e1000_igp_2_cable_length_table[max_agc_index]); 1669 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1670 1671 /* Calculate cable length with the error range of +/- 10 meters. */ 1672 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1673 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1674 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1675 1676 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1677 1678 out: 1679 return (ret_val); 1680 } 1681 1682 /* 1683 * e1000_get_phy_info_m88 - Retrieve PHY information 1684 * @hw: pointer to the HW structure 1685 * 1686 * Valid for only copper links. Read the PHY status register (sticky read) 1687 * to verify that link is up. Read the PHY special control register to 1688 * determine the polarity and 10base-T extended distance. Read the PHY 1689 * special status register to determine MDI/MDIx and current speed. If 1690 * speed is 1000, then determine cable length, local and remote receiver. 1691 */ 1692 s32 1693 e1000_get_phy_info_m88(struct e1000_hw *hw) 1694 { 1695 struct e1000_phy_info *phy = &hw->phy; 1696 s32 ret_val; 1697 u16 phy_data; 1698 bool link; 1699 1700 DEBUGFUNC("e1000_get_phy_info_m88"); 1701 1702 if (hw->phy.media_type != e1000_media_type_copper) { 1703 DEBUGOUT("Phy info is only valid for copper media\n"); 1704 ret_val = -E1000_ERR_CONFIG; 1705 goto out; 1706 } 1707 1708 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1709 if (ret_val) 1710 goto out; 1711 1712 if (!link) { 1713 DEBUGOUT("Phy info is only valid if link is up\n"); 1714 ret_val = -E1000_ERR_CONFIG; 1715 goto out; 1716 } 1717 1718 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1719 if (ret_val) 1720 goto out; 1721 1722 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1723 ? TRUE 1724 : FALSE; 1725 1726 ret_val = e1000_check_polarity_m88(hw); 1727 if (ret_val) 1728 goto out; 1729 1730 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1731 if (ret_val) 1732 goto out; 1733 1734 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 1735 1736 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1737 ret_val = e1000_get_cable_length(hw); 1738 if (ret_val) 1739 goto out; 1740 1741 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 1742 if (ret_val) 1743 goto out; 1744 1745 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1746 ? e1000_1000t_rx_status_ok 1747 : e1000_1000t_rx_status_not_ok; 1748 1749 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1750 ? e1000_1000t_rx_status_ok 1751 : e1000_1000t_rx_status_not_ok; 1752 } else { 1753 /* Set values to "undefined" */ 1754 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1755 phy->local_rx = e1000_1000t_rx_status_undefined; 1756 phy->remote_rx = e1000_1000t_rx_status_undefined; 1757 } 1758 1759 out: 1760 return (ret_val); 1761 } 1762 1763 /* 1764 * e1000_get_phy_info_igp - Retrieve igp PHY information 1765 * @hw: pointer to the HW structure 1766 * 1767 * Read PHY status to determine if link is up. If link is up, then 1768 * set/determine 10base-T extended distance and polarity correction. Read 1769 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1770 * determine on the cable length, local and remote receiver. 1771 */ 1772 s32 1773 e1000_get_phy_info_igp(struct e1000_hw *hw) 1774 { 1775 struct e1000_phy_info *phy = &hw->phy; 1776 s32 ret_val; 1777 u16 data; 1778 bool link; 1779 1780 DEBUGFUNC("e1000_get_phy_info_igp"); 1781 1782 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1783 if (ret_val) 1784 goto out; 1785 1786 if (!link) { 1787 DEBUGOUT("Phy info is only valid if link is up\n"); 1788 ret_val = -E1000_ERR_CONFIG; 1789 goto out; 1790 } 1791 1792 phy->polarity_correction = TRUE; 1793 1794 ret_val = e1000_check_polarity_igp(hw); 1795 if (ret_val) 1796 goto out; 1797 1798 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1799 if (ret_val) 1800 goto out; 1801 1802 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 1803 1804 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1805 IGP01E1000_PSSR_SPEED_1000MBPS) { 1806 ret_val = e1000_get_cable_length(hw); 1807 if (ret_val) 1808 goto out; 1809 1810 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &data); 1811 if (ret_val) 1812 goto out; 1813 1814 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 1815 ? e1000_1000t_rx_status_ok 1816 : e1000_1000t_rx_status_not_ok; 1817 1818 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 1819 ? e1000_1000t_rx_status_ok 1820 : e1000_1000t_rx_status_not_ok; 1821 } else { 1822 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1823 phy->local_rx = e1000_1000t_rx_status_undefined; 1824 phy->remote_rx = e1000_1000t_rx_status_undefined; 1825 } 1826 1827 out: 1828 return (ret_val); 1829 } 1830 1831 /* 1832 * e1000_phy_sw_reset_generic - PHY software reset 1833 * @hw: pointer to the HW structure 1834 * 1835 * Does a software reset of the PHY by reading the PHY control register and 1836 * setting/write the control register reset bit to the PHY. 1837 */ 1838 s32 1839 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 1840 { 1841 s32 ret_val; 1842 u16 phy_ctrl; 1843 1844 DEBUGFUNC("e1000_phy_sw_reset_generic"); 1845 1846 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 1847 if (ret_val) 1848 goto out; 1849 1850 phy_ctrl |= MII_CR_RESET; 1851 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 1852 if (ret_val) 1853 goto out; 1854 1855 usec_delay(1); 1856 1857 out: 1858 return (ret_val); 1859 } 1860 1861 /* 1862 * e1000_phy_hw_reset_generic - PHY hardware reset 1863 * @hw: pointer to the HW structure 1864 * 1865 * Verify the reset block is not blocking us from resetting. Acquire 1866 * semaphore (if necessary) and read/set/write the device control reset 1867 * bit in the PHY. Wait the appropriate delay time for the device to 1868 * reset and relase the semaphore (if necessary). 1869 */ 1870 s32 1871 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 1872 { 1873 struct e1000_phy_info *phy = &hw->phy; 1874 s32 ret_val; 1875 u32 ctrl; 1876 1877 DEBUGFUNC("e1000_phy_hw_reset_generic"); 1878 1879 ret_val = e1000_check_reset_block(hw); 1880 if (ret_val) { 1881 ret_val = E1000_SUCCESS; 1882 goto out; 1883 } 1884 1885 ret_val = e1000_acquire_phy(hw); 1886 if (ret_val) 1887 goto out; 1888 1889 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1890 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 1891 E1000_WRITE_FLUSH(hw); 1892 1893 usec_delay(phy->reset_delay_us); 1894 1895 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1896 E1000_WRITE_FLUSH(hw); 1897 1898 usec_delay(150); 1899 1900 e1000_release_phy(hw); 1901 1902 ret_val = e1000_get_phy_cfg_done(hw); 1903 1904 out: 1905 return (ret_val); 1906 } 1907 1908 /* 1909 * e1000_get_cfg_done_generic - Generic configuration done 1910 * @hw: pointer to the HW structure 1911 * 1912 * Generic function to wait 10 milli-seconds for configuration to complete 1913 * and return success. 1914 */ 1915 s32 1916 e1000_get_cfg_done_generic(struct e1000_hw *hw) 1917 { 1918 DEBUGFUNC("e1000_get_cfg_done_generic"); 1919 UNREFERENCED_PARAMETER(hw); 1920 1921 msec_delay_irq(10); 1922 1923 return (E1000_SUCCESS); 1924 } 1925 1926 /* Internal function pointers */ 1927 1928 /* 1929 * e1000_get_phy_cfg_done - Generic PHY configuration done 1930 * @hw: pointer to the HW structure 1931 * 1932 * Return success if silicon family did not implement a family specific 1933 * get_cfg_done function. 1934 */ 1935 static s32 1936 e1000_get_phy_cfg_done(struct e1000_hw *hw) 1937 { 1938 if (hw->func.get_cfg_done) 1939 return (hw->func.get_cfg_done(hw)); 1940 1941 return (E1000_SUCCESS); 1942 } 1943 1944 /* 1945 * e1000_release_phy - Generic release PHY 1946 * @hw: pointer to the HW structure 1947 * 1948 * Return if silicon family does not require a semaphore when accessing the 1949 * PHY. 1950 */ 1951 static void 1952 e1000_release_phy(struct e1000_hw *hw) 1953 { 1954 if (hw->func.release_phy) 1955 hw->func.release_phy(hw); 1956 } 1957 1958 /* 1959 * e1000_acquire_phy - Generic acquire PHY 1960 * @hw: pointer to the HW structure 1961 * 1962 * Return success if silicon family does not require a semaphore when 1963 * accessing the PHY. 1964 */ 1965 static s32 1966 e1000_acquire_phy(struct e1000_hw *hw) 1967 { 1968 if (hw->func.acquire_phy) 1969 return (hw->func.acquire_phy(hw)); 1970 1971 return (E1000_SUCCESS); 1972 } 1973 1974 /* 1975 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex 1976 * @hw: pointer to the HW structure 1977 * 1978 * When the silicon family has not implemented a forced speed/duplex 1979 * function for the PHY, simply return (E1000_SUCCESS). 1980 */ 1981 s32 1982 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1983 { 1984 if (hw->func.force_speed_duplex) 1985 return (hw->func.force_speed_duplex(hw)); 1986 1987 return (E1000_SUCCESS); 1988 } 1989 1990 /* 1991 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 1992 * @hw: pointer to the HW structure 1993 * 1994 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 1995 */ 1996 s32 1997 e1000_phy_init_script_igp3(struct e1000_hw *hw) 1998 { 1999 DEBUGOUT("Running IGP 3 PHY init script\n"); 2000 2001 /* PHY init IGP 3 */ 2002 /* Enable rise/fall, 10-mode work in class-A */ 2003 (void) e1000_write_phy_reg(hw, 0x2F5B, 0x9018); 2004 /* Remove all caps from Replica path filter */ 2005 (void) e1000_write_phy_reg(hw, 0x2F52, 0x0000); 2006 /* Bias trimming for ADC, AFE and Driver (Default) */ 2007 (void) e1000_write_phy_reg(hw, 0x2FB1, 0x8B24); 2008 /* Increase Hybrid poly bias */ 2009 (void) e1000_write_phy_reg(hw, 0x2FB2, 0xF8F0); 2010 /* Add 4% to Tx amplitude in Giga mode */ 2011 (void) e1000_write_phy_reg(hw, 0x2010, 0x10B0); 2012 /* Disable trimming (TTT) */ 2013 (void) e1000_write_phy_reg(hw, 0x2011, 0x0000); 2014 /* Poly DC correction to 94.6% + 2% for all channels */ 2015 (void) e1000_write_phy_reg(hw, 0x20DD, 0x249A); 2016 /* ABS DC correction to 95.9% */ 2017 (void) e1000_write_phy_reg(hw, 0x20DE, 0x00D3); 2018 /* BG temp curve trim */ 2019 (void) e1000_write_phy_reg(hw, 0x28B4, 0x04CE); 2020 /* Increasing ADC OPAMP stage 1 currents to max */ 2021 (void) e1000_write_phy_reg(hw, 0x2F70, 0x29E4); 2022 /* Force 1000 ( required for enabling PHY regs configuration) */ 2023 (void) e1000_write_phy_reg(hw, 0x0000, 0x0140); 2024 /* Set upd_freq to 6 */ 2025 (void) e1000_write_phy_reg(hw, 0x1F30, 0x1606); 2026 /* Disable NPDFE */ 2027 (void) e1000_write_phy_reg(hw, 0x1F31, 0xB814); 2028 /* Disable adaptive fixed FFE (Default) */ 2029 (void) e1000_write_phy_reg(hw, 0x1F35, 0x002A); 2030 /* Enable FFE hysteresis */ 2031 (void) e1000_write_phy_reg(hw, 0x1F3E, 0x0067); 2032 /* Fixed FFE for short cable lengths */ 2033 (void) e1000_write_phy_reg(hw, 0x1F54, 0x0065); 2034 /* Fixed FFE for medium cable lengths */ 2035 (void) e1000_write_phy_reg(hw, 0x1F55, 0x002A); 2036 /* Fixed FFE for long cable lengths */ 2037 (void) e1000_write_phy_reg(hw, 0x1F56, 0x002A); 2038 /* Enable Adaptive Clip Threshold */ 2039 (void) e1000_write_phy_reg(hw, 0x1F72, 0x3FB0); 2040 /* AHT reset limit to 1 */ 2041 (void) e1000_write_phy_reg(hw, 0x1F76, 0xC0FF); 2042 /* Set AHT master delay to 127 msec */ 2043 (void) e1000_write_phy_reg(hw, 0x1F77, 0x1DEC); 2044 /* Set scan bits for AHT */ 2045 (void) e1000_write_phy_reg(hw, 0x1F78, 0xF9EF); 2046 /* Set AHT Preset bits */ 2047 (void) e1000_write_phy_reg(hw, 0x1F79, 0x0210); 2048 /* Change integ_factor of channel A to 3 */ 2049 (void) e1000_write_phy_reg(hw, 0x1895, 0x0003); 2050 /* Change prop_factor of channels BCD to 8 */ 2051 (void) e1000_write_phy_reg(hw, 0x1796, 0x0008); 2052 /* Change cg_icount + enable integbp for channels BCD */ 2053 (void) e1000_write_phy_reg(hw, 0x1798, 0xD008); 2054 /* 2055 * Change cg_icount + enable integbp + change prop_factor_master 2056 * to 8 for channel A 2057 */ 2058 (void) e1000_write_phy_reg(hw, 0x1898, 0xD918); 2059 /* Disable AHT in Slave mode on channel A */ 2060 (void) e1000_write_phy_reg(hw, 0x187A, 0x0800); 2061 /* 2062 * Enable LPLU and disable AN to 1000 in non-D0a states, 2063 * Enable SPD+B2B 2064 */ 2065 (void) e1000_write_phy_reg(hw, 0x0019, 0x008D); 2066 /* Enable restart AN on an1000_dis change */ 2067 (void) e1000_write_phy_reg(hw, 0x001B, 0x2080); 2068 /* Enable wh_fifo read clock in 10/100 modes */ 2069 (void) e1000_write_phy_reg(hw, 0x0014, 0x0045); 2070 /* Restart AN, Speed selection is 1000 */ 2071 (void) e1000_write_phy_reg(hw, 0x0000, 0x1340); 2072 2073 return (E1000_SUCCESS); 2074 } 2075 2076 /* 2077 * e1000_get_phy_type_from_id - Get PHY type from id 2078 * @phy_id: phy_id read from the phy 2079 * 2080 * Returns the phy type from the id. 2081 */ 2082 e1000_phy_type 2083 e1000_get_phy_type_from_id(u32 phy_id) 2084 { 2085 e1000_phy_type phy_type = e1000_phy_unknown; 2086 2087 switch (phy_id) { 2088 case M88E1000_I_PHY_ID: 2089 case M88E1000_E_PHY_ID: 2090 case M88E1111_I_PHY_ID: 2091 case M88E1011_I_PHY_ID: 2092 phy_type = e1000_phy_m88; 2093 break; 2094 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2095 phy_type = e1000_phy_igp_2; 2096 break; 2097 case GG82563_E_PHY_ID: 2098 phy_type = e1000_phy_gg82563; 2099 break; 2100 case IGP03E1000_E_PHY_ID: 2101 phy_type = e1000_phy_igp_3; 2102 break; 2103 case IFE_E_PHY_ID: 2104 case IFE_PLUS_E_PHY_ID: 2105 case IFE_C_E_PHY_ID: 2106 phy_type = e1000_phy_ife; 2107 break; 2108 case BME1000_E_PHY_ID: 2109 case BME1000_E_PHY_ID_R2: 2110 phy_type = e1000_phy_bm; 2111 break; 2112 default: 2113 phy_type = e1000_phy_unknown; 2114 break; 2115 } 2116 return (phy_type); 2117 } 2118 2119 /* 2120 * e1000_determine_phy_address - Determines PHY address. 2121 * @hw: pointer to the HW structure 2122 * 2123 * This uses a trial and error method to loop through possible PHY 2124 * addresses. It tests each by reading the PHY ID registers and 2125 * checking for a match. 2126 */ 2127 s32 2128 e1000_determine_phy_address(struct e1000_hw *hw) 2129 { 2130 s32 ret_val = -E1000_ERR_PHY_TYPE; 2131 u32 phy_addr = 0; 2132 u32 i = 0; 2133 e1000_phy_type phy_type = e1000_phy_unknown; 2134 2135 do { 2136 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2137 hw->phy.addr = phy_addr; 2138 (void) e1000_get_phy_id(hw); 2139 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2140 2141 /* 2142 * If phy_type is valid, break - we found our 2143 * PHY address 2144 */ 2145 if (phy_type != e1000_phy_unknown) { 2146 ret_val = E1000_SUCCESS; 2147 break; 2148 } 2149 } 2150 i++; 2151 } while ((ret_val != E1000_SUCCESS) && (i < 100)); 2152 2153 return (ret_val); 2154 } 2155 2156 /* 2157 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2158 * @page: page to access 2159 * 2160 * Returns the phy address for the page requested. 2161 */ 2162 static u32 2163 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2164 { 2165 u32 phy_addr = 2; 2166 2167 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2168 phy_addr = 1; 2169 2170 return (phy_addr); 2171 } 2172 2173 /* 2174 * e1000_write_phy_reg_bm - Write BM PHY register 2175 * @hw: pointer to the HW structure 2176 * @offset: register offset to write to 2177 * @data: data to write at register offset 2178 * 2179 * Acquires semaphore, if necessary, then writes the data to PHY register 2180 * at the offset. Release any acquired semaphores before exiting. 2181 */ 2182 s32 2183 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2184 { 2185 s32 ret_val; 2186 u32 page_select = 0; 2187 u32 page = offset >> IGP_PAGE_SHIFT; 2188 u32 page_shift = 0; 2189 2190 DEBUGFUNC("e1000_write_phy_reg_bm"); 2191 2192 /* Page 800 works differently than the rest so it has its own func */ 2193 if (page == BM_WUC_PAGE) { 2194 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2195 offset, &data, FALSE); 2196 goto out; 2197 } 2198 2199 ret_val = e1000_acquire_phy(hw); 2200 if (ret_val) 2201 goto out; 2202 2203 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2204 2205 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2206 /* 2207 * Page select is register 31 for phy address 1 and 22 for 2208 * phy address 2 and 3. Page select is shifted only for 2209 * phy address 1. 2210 */ 2211 if (hw->phy.addr == 1) { 2212 page_shift = IGP_PAGE_SHIFT; 2213 page_select = IGP01E1000_PHY_PAGE_SELECT; 2214 } else { 2215 page_shift = 0; 2216 page_select = BM_PHY_PAGE_SELECT; 2217 } 2218 2219 /* Page is shifted left, PHY expects (page x 32) */ 2220 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2221 (page << page_shift)); 2222 if (ret_val) { 2223 e1000_release_phy(hw); 2224 goto out; 2225 } 2226 } 2227 2228 ret_val = e1000_write_phy_reg_mdic(hw, 2229 MAX_PHY_REG_ADDRESS & offset, 2230 data); 2231 2232 e1000_release_phy(hw); 2233 2234 out: 2235 return (ret_val); 2236 } 2237 2238 /* 2239 * e1000_read_phy_reg_bm - Read BM PHY register 2240 * @hw: pointer to the HW structure 2241 * @offset: register offset to be read 2242 * @data: pointer to the read data 2243 * 2244 * Acquires semaphore, if necessary, then reads the PHY register at offset 2245 * and storing the retrieved information in data. Release any acquired 2246 * semaphores before exiting. 2247 */ 2248 s32 2249 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2250 { 2251 s32 ret_val; 2252 u32 page_select = 0; 2253 u32 page = offset >> IGP_PAGE_SHIFT; 2254 u32 page_shift = 0; 2255 2256 DEBUGFUNC("e1000_write_phy_reg_bm"); 2257 2258 /* Page 800 works differently than the rest so it has its own func */ 2259 if (page == BM_WUC_PAGE) { 2260 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2261 offset, data, TRUE); 2262 goto out; 2263 } 2264 2265 ret_val = e1000_acquire_phy(hw); 2266 if (ret_val) 2267 goto out; 2268 2269 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2270 2271 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2272 /* 2273 * Page select is register 31 for phy address 1 and 22 for 2274 * phy address 2 and 3. Page select is shifted only for 2275 * phy address 1. 2276 */ 2277 if (hw->phy.addr == 1) { 2278 page_shift = IGP_PAGE_SHIFT; 2279 page_select = IGP01E1000_PHY_PAGE_SELECT; 2280 } else { 2281 page_shift = 0; 2282 page_select = BM_PHY_PAGE_SELECT; 2283 } 2284 2285 /* Page is shifted left, PHY expects (page x 32) */ 2286 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2287 (page << page_shift)); 2288 if (ret_val) { 2289 e1000_release_phy(hw); 2290 goto out; 2291 } 2292 } 2293 2294 ret_val = e1000_read_phy_reg_mdic(hw, 2295 MAX_PHY_REG_ADDRESS & offset, 2296 data); 2297 e1000_release_phy(hw); 2298 2299 out: 2300 return (ret_val); 2301 } 2302 2303 /* 2304 * e1000_read_phy_reg_bm2 - Read BM PHY register 2305 * @hw: pointer to the HW structure 2306 * @offset: register offset to be read 2307 * @data: pointer to the read data 2308 * 2309 * Acquires semaphore, if necessary, then reads the PHY register at offset 2310 * and storing the retrieved information in data. Release any acquired 2311 * semaphores before exiting. 2312 */ 2313 s32 2314 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2315 { 2316 s32 ret_val; 2317 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2318 2319 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2320 2321 /* Page 800 works differently than the rest so it has its own func */ 2322 if (page == BM_WUC_PAGE) { 2323 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2324 offset, data, TRUE); 2325 goto out; 2326 } 2327 2328 ret_val = e1000_acquire_phy(hw); 2329 if (ret_val) 2330 goto out; 2331 2332 hw->phy.addr = 1; 2333 2334 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2335 2336 /* Page is shifted left, PHY expects (page x 32) */ 2337 ret_val = e1000_write_phy_reg_mdic(hw, 2338 BM_PHY_PAGE_SELECT, 2339 page); 2340 2341 if (ret_val) { 2342 e1000_release_phy(hw); 2343 goto out; 2344 } 2345 } 2346 2347 ret_val = e1000_read_phy_reg_mdic(hw, 2348 MAX_PHY_REG_ADDRESS & offset, 2349 data); 2350 e1000_release_phy(hw); 2351 2352 out: 2353 return (ret_val); 2354 } 2355 2356 /* 2357 * e1000_write_phy_reg_bm2 - Write BM PHY register 2358 * @hw: pointer to the HW structure 2359 * @offset: register offset to write to 2360 * @data: data to write at register offset 2361 * 2362 * Acquires semaphore, if necessary, then writes the data to PHY register 2363 * at the offset. Release any acquired semaphores before exiting. 2364 */ 2365 s32 2366 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2367 { 2368 s32 ret_val; 2369 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2370 2371 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2372 2373 /* Page 800 works differently than the rest so it has its own func */ 2374 if (page == BM_WUC_PAGE) { 2375 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2376 offset, &data, FALSE); 2377 goto out; 2378 } 2379 2380 ret_val = e1000_acquire_phy(hw); 2381 if (ret_val) 2382 goto out; 2383 2384 hw->phy.addr = 1; 2385 2386 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2387 /* Page is shifted left, PHY expects (page x 32) */ 2388 ret_val = e1000_write_phy_reg_mdic(hw, 2389 BM_PHY_PAGE_SELECT, 2390 page); 2391 2392 if (ret_val) { 2393 e1000_release_phy(hw); 2394 goto out; 2395 } 2396 } 2397 2398 ret_val = e1000_write_phy_reg_mdic(hw, 2399 MAX_PHY_REG_ADDRESS & offset, 2400 data); 2401 2402 e1000_release_phy(hw); 2403 2404 out: 2405 return (ret_val); 2406 } 2407 2408 /* 2409 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register 2410 * @hw: pointer to the HW structure 2411 * @offset: register offset to be read or written 2412 * @data: pointer to the data to read or write 2413 * @read: determines if operation is read or write 2414 * 2415 * Acquires semaphore, if necessary, then reads the PHY register at offset 2416 * and storing the retrieved information in data. Release any acquired 2417 * semaphores before exiting. Note that procedure to read the wakeup 2418 * registers are different. It works as such: 2419 * 1) Set page 769, register 17, bit 2 = 1 2420 * 2) Set page to 800 for host (801 if we were manageability) 2421 * 3) Write the address using the address opcode (0x11) 2422 * 4) Read or write the data using the data opcode (0x12) 2423 * 5) Restore 769_17.2 to its original value 2424 */ 2425 s32 2426 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, 2427 u32 offset, u16 *data, bool read) 2428 { 2429 s32 ret_val; 2430 u16 reg = ((u16)offset) & PHY_REG_MASK; 2431 u16 phy_reg = 0; 2432 u8 phy_acquired = 1; 2433 2434 DEBUGFUNC("e1000_read_phy_wakeup_reg_bm"); 2435 2436 ret_val = e1000_acquire_phy(hw); 2437 if (ret_val) { 2438 DEBUGOUT("Couldnt acquire PHY\n"); 2439 phy_acquired = 0; 2440 goto out; 2441 } 2442 2443 /* All operations in this function are phy address 1 */ 2444 hw->phy.addr = 1; 2445 2446 /* Set page 769 */ 2447 (void) e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2448 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2449 2450 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2451 if (ret_val) { 2452 DEBUGOUT("Couldnt read PHY page 769\n"); 2453 goto out; 2454 } 2455 2456 /* First clear bit 4 to avoid a power state change */ 2457 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2458 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2459 if (ret_val) { 2460 DEBUGOUT("Couldnt clear PHY page 769 bit 4\n"); 2461 goto out; 2462 } 2463 2464 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2465 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2466 phy_reg | BM_WUC_ENABLE_BIT); 2467 if (ret_val) { 2468 DEBUGOUT("Couldnt write PHY page 769 bit 2\n"); 2469 goto out; 2470 } 2471 2472 /* Select page 800 */ 2473 ret_val = e1000_write_phy_reg_mdic(hw, 2474 IGP01E1000_PHY_PAGE_SELECT, 2475 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2476 2477 /* Write the page 800 offset value using opcode 0x11 */ 2478 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2479 if (ret_val) { 2480 DEBUGOUT("Couldnt write address opcode to page 800\n"); 2481 goto out; 2482 } 2483 2484 if (read) { 2485 /* Read the page 800 value using opcode 0x12 */ 2486 ret_val = e1000_read_phy_reg_mdic(hw, 2487 BM_WUC_DATA_OPCODE, 2488 data); 2489 } else { 2490 /* Read the page 800 value using opcode 0x12 */ 2491 ret_val = e1000_write_phy_reg_mdic(hw, 2492 BM_WUC_DATA_OPCODE, 2493 *data); 2494 } 2495 2496 if (ret_val) { 2497 DEBUGOUT("Couldnt read data value from page 800\n"); 2498 goto out; 2499 } 2500 2501 /* 2502 * Restore 769_17.2 to its original value 2503 * Set page 769 2504 */ 2505 (void) e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2506 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2507 2508 /* Clear 769_17.2 */ 2509 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2510 if (ret_val) { 2511 DEBUGOUT("Couldnt clear PHY page 769 bit 2\n"); 2512 goto out; 2513 } 2514 2515 out: 2516 if (phy_acquired == 1) 2517 e1000_release_phy(hw); 2518 return (ret_val); 2519 } 2520 2521 /* 2522 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2523 * @hw: pointer to the HW structure 2524 * 2525 * In the case of a PHY power down to save power, or to turn off link during a 2526 * driver unload, or wake on lan is not enabled, restore the link to previous 2527 * settings. 2528 */ 2529 void 2530 e1000_power_up_phy_copper(struct e1000_hw *hw) 2531 { 2532 u16 mii_reg = 0; 2533 2534 /* The PHY will retain its settings across a power down/up cycle */ 2535 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &mii_reg); 2536 mii_reg &= ~MII_CR_POWER_DOWN; 2537 (void) e1000_write_phy_reg(hw, PHY_CONTROL, mii_reg); 2538 } 2539 2540 /* 2541 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2542 * @hw: pointer to the HW structure 2543 * 2544 * In the case of a PHY power down to save power, or to turn off link during a 2545 * driver unload, or wake on lan is not enabled, restore the link to previous 2546 * settings. 2547 */ 2548 void 2549 e1000_power_down_phy_copper(struct e1000_hw *hw) 2550 { 2551 u16 mii_reg = 0; 2552 2553 /* The PHY will retain its settings across a power down/up cycle */ 2554 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &mii_reg); 2555 mii_reg |= MII_CR_POWER_DOWN; 2556 (void) e1000_write_phy_reg(hw, PHY_CONTROL, mii_reg); 2557 msec_delay(1); 2558 } 2559