1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_api.h" 32 #include "igb_phy.h" 33 34 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 35 static void e1000_release_phy(struct e1000_hw *hw); 36 static s32 e1000_acquire_phy(struct e1000_hw *hw); 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 39 /* Cable length tables */ 40 static const u16 e1000_m88_cable_length_table[] = 41 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 42 43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 44 (sizeof (e1000_m88_cable_length_table) / \ 45 sizeof (e1000_m88_cable_length_table[0])) 46 47 static const u16 e1000_igp_2_cable_length_table[] = 48 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 55 104, 109, 114, 118, 121, 124}; 56 57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 58 (sizeof (e1000_igp_2_cable_length_table) / \ 59 sizeof (e1000_igp_2_cable_length_table[0])) 60 61 /* 62 * e1000_check_reset_block_generic - Check if PHY reset is blocked 63 * @hw: pointer to the HW structure 64 * 65 * Read the PHY management control register and check whether a PHY reset 66 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 67 * return E1000_BLK_PHY_RESET (12). 68 */ 69 s32 70 e1000_check_reset_block_generic(struct e1000_hw *hw) 71 { 72 u32 manc; 73 74 DEBUGFUNC("e1000_check_reset_block"); 75 76 manc = E1000_READ_REG(hw, E1000_MANC); 77 78 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 79 E1000_BLK_PHY_RESET : E1000_SUCCESS; 80 } 81 82 /* 83 * e1000_get_phy_id - Retrieve the PHY ID and revision 84 * @hw: pointer to the HW structure 85 * 86 * Reads the PHY registers and stores the PHY ID and possibly the PHY 87 * revision in the hardware structure. 88 */ 89 s32 90 e1000_get_phy_id(struct e1000_hw *hw) 91 { 92 struct e1000_phy_info *phy = &hw->phy; 93 s32 ret_val = E1000_SUCCESS; 94 u16 phy_id; 95 96 DEBUGFUNC("e1000_get_phy_id"); 97 98 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id); 99 if (ret_val) 100 goto out; 101 102 phy->id = (u32)(phy_id << 16); 103 usec_delay(20); 104 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id); 105 if (ret_val) 106 goto out; 107 108 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 109 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 110 111 out: 112 return (ret_val); 113 } 114 115 /* 116 * e1000_phy_reset_dsp_generic - Reset PHY DSP 117 * @hw: pointer to the HW structure 118 * 119 * Reset the digital signal processor. 120 */ 121 s32 122 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 123 { 124 s32 ret_val; 125 126 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 127 128 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 129 if (ret_val) 130 goto out; 131 132 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 133 134 out: 135 return (ret_val); 136 } 137 138 /* 139 * e1000_read_phy_reg_mdic - Read MDI control register 140 * @hw: pointer to the HW structure 141 * @offset: register offset to be read 142 * @data: pointer to the read data 143 * 144 * Reads the MDI control regsiter in the PHY at offset and stores the 145 * information read to data. 146 */ 147 s32 148 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 149 { 150 struct e1000_phy_info *phy = &hw->phy; 151 u32 i, mdic = 0; 152 s32 ret_val = E1000_SUCCESS; 153 154 DEBUGFUNC("e1000_read_phy_reg_mdic"); 155 156 if (offset > MAX_PHY_REG_ADDRESS) { 157 DEBUGOUT1("PHY Address %d is out of range\n", offset); 158 ret_val = -E1000_ERR_PARAM; 159 goto out; 160 } 161 162 /* 163 * Set up Op-code, Phy Address, and register offset in the MDI 164 * Control register. The MAC will take care of interfacing with the 165 * PHY to retrieve the desired data. 166 */ 167 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 168 (phy->addr << E1000_MDIC_PHY_SHIFT) | 169 (E1000_MDIC_OP_READ)); 170 171 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 172 173 /* 174 * Poll the ready bit to see if the MDI read completed 175 * Increasing the time out as testing showed failures with 176 * the lower time out 177 */ 178 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 179 usec_delay(50); 180 mdic = E1000_READ_REG(hw, E1000_MDIC); 181 if (mdic & E1000_MDIC_READY) 182 break; 183 } 184 if (!(mdic & E1000_MDIC_READY)) { 185 DEBUGOUT("MDI Read did not complete\n"); 186 ret_val = -E1000_ERR_PHY; 187 goto out; 188 } 189 if (mdic & E1000_MDIC_ERROR) { 190 DEBUGOUT("MDI Error\n"); 191 ret_val = -E1000_ERR_PHY; 192 goto out; 193 } 194 *data = (u16) mdic; 195 196 out: 197 return (ret_val); 198 } 199 200 /* 201 * e1000_write_phy_reg_mdic - Write MDI control register 202 * @hw: pointer to the HW structure 203 * @offset: register offset to write to 204 * @data: data to write to register at offset 205 * 206 * Writes data to MDI control register in the PHY at offset. 207 */ 208 s32 209 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 210 { 211 struct e1000_phy_info *phy = &hw->phy; 212 u32 i, mdic = 0; 213 s32 ret_val = E1000_SUCCESS; 214 215 DEBUGFUNC("e1000_write_phy_reg_mdic"); 216 217 if (offset > MAX_PHY_REG_ADDRESS) { 218 DEBUGOUT1("PHY Address %d is out of range\n", offset); 219 ret_val = -E1000_ERR_PARAM; 220 goto out; 221 } 222 223 /* 224 * Set up Op-code, Phy Address, and register offset in the MDI 225 * Control register. The MAC will take care of interfacing with the 226 * PHY to retrieve the desired data. 227 */ 228 mdic = (((u32)data) | 229 (offset << E1000_MDIC_REG_SHIFT) | 230 (phy->addr << E1000_MDIC_PHY_SHIFT) | 231 (E1000_MDIC_OP_WRITE)); 232 233 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 234 235 /* 236 * Poll the ready bit to see if the MDI read completed 237 * Increasing the time out as testing showed failures with 238 * the lower time out 239 */ 240 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 241 usec_delay(50); 242 mdic = E1000_READ_REG(hw, E1000_MDIC); 243 if (mdic & E1000_MDIC_READY) 244 break; 245 } 246 if (!(mdic & E1000_MDIC_READY)) { 247 DEBUGOUT("MDI Write did not complete\n"); 248 ret_val = -E1000_ERR_PHY; 249 goto out; 250 } 251 if (mdic & E1000_MDIC_ERROR) { 252 DEBUGOUT("MDI Error\n"); 253 ret_val = -E1000_ERR_PHY; 254 goto out; 255 } 256 257 out: 258 return (ret_val); 259 } 260 261 /* 262 * e1000_read_phy_reg_m88 - Read m88 PHY register 263 * @hw: pointer to the HW structure 264 * @offset: register offset to be read 265 * @data: pointer to the read data 266 * 267 * Acquires semaphore, if necessary, then reads the PHY register at offset 268 * and storing the retrieved information in data. Release any acquired 269 * semaphores before exiting. 270 */ 271 s32 272 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 273 { 274 s32 ret_val; 275 276 DEBUGFUNC("e1000_read_phy_reg_m88"); 277 278 ret_val = e1000_acquire_phy(hw); 279 if (ret_val) 280 goto out; 281 282 ret_val = e1000_read_phy_reg_mdic(hw, 283 MAX_PHY_REG_ADDRESS & offset, data); 284 285 e1000_release_phy(hw); 286 287 out: 288 return (ret_val); 289 } 290 291 /* 292 * e1000_write_phy_reg_m88 - Write m88 PHY register 293 * @hw: pointer to the HW structure 294 * @offset: register offset to write to 295 * @data: data to write at register offset 296 * 297 * Acquires semaphore, if necessary, then writes the data to PHY register 298 * at the offset. Release any acquired semaphores before exiting. 299 */ 300 s32 301 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 302 { 303 s32 ret_val; 304 305 DEBUGFUNC("e1000_write_phy_reg_m88"); 306 307 ret_val = e1000_acquire_phy(hw); 308 if (ret_val) 309 goto out; 310 311 ret_val = e1000_write_phy_reg_mdic(hw, 312 MAX_PHY_REG_ADDRESS & offset, data); 313 314 e1000_release_phy(hw); 315 316 out: 317 return (ret_val); 318 } 319 320 /* 321 * e1000_read_phy_reg_igp - Read igp PHY register 322 * @hw: pointer to the HW structure 323 * @offset: register offset to be read 324 * @data: pointer to the read data 325 * 326 * Acquires semaphore, if necessary, then reads the PHY register at offset 327 * and storing the retrieved information in data. Release any acquired 328 * semaphores before exiting. 329 */ 330 s32 331 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 332 { 333 s32 ret_val; 334 335 DEBUGFUNC("e1000_read_phy_reg_igp"); 336 337 ret_val = e1000_acquire_phy(hw); 338 if (ret_val) 339 goto out; 340 341 if (offset > MAX_PHY_MULTI_PAGE_REG) { 342 ret_val = e1000_write_phy_reg_mdic(hw, 343 IGP01E1000_PHY_PAGE_SELECT, (u16)offset); 344 if (ret_val) { 345 e1000_release_phy(hw); 346 goto out; 347 } 348 } 349 350 ret_val = e1000_read_phy_reg_mdic(hw, 351 MAX_PHY_REG_ADDRESS & offset, data); 352 353 e1000_release_phy(hw); 354 355 out: 356 return (ret_val); 357 } 358 359 /* 360 * e1000_write_phy_reg_igp - Write igp PHY register 361 * @hw: pointer to the HW structure 362 * @offset: register offset to write to 363 * @data: data to write at register offset 364 * 365 * Acquires semaphore, if necessary, then writes the data to PHY register 366 * at the offset. Release any acquired semaphores before exiting. 367 */ 368 s32 369 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 370 { 371 s32 ret_val; 372 373 DEBUGFUNC("e1000_write_phy_reg_igp"); 374 375 ret_val = e1000_acquire_phy(hw); 376 if (ret_val) 377 goto out; 378 379 if (offset > MAX_PHY_MULTI_PAGE_REG) { 380 ret_val = e1000_write_phy_reg_mdic(hw, 381 IGP01E1000_PHY_PAGE_SELECT, (u16)offset); 382 if (ret_val) { 383 e1000_release_phy(hw); 384 goto out; 385 } 386 } 387 388 ret_val = e1000_write_phy_reg_mdic(hw, 389 MAX_PHY_REG_ADDRESS & offset, data); 390 391 e1000_release_phy(hw); 392 393 out: 394 return (ret_val); 395 } 396 397 /* 398 * e1000_read_kmrn_reg_generic - Read kumeran register 399 * @hw: pointer to the HW structure 400 * @offset: register offset to be read 401 * @data: pointer to the read data 402 * 403 * Acquires semaphore, if necessary. Then reads the PHY register at offset 404 * using the kumeran interface. The information retrieved is stored in data. 405 * Release any acquired semaphores before exiting. 406 */ 407 s32 408 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 409 { 410 u32 kmrnctrlsta; 411 s32 ret_val; 412 413 DEBUGFUNC("e1000_read_kmrn_reg_generic"); 414 415 ret_val = e1000_acquire_phy(hw); 416 if (ret_val) 417 goto out; 418 419 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 420 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 421 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 422 423 usec_delay(2); 424 425 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 426 *data = (u16)kmrnctrlsta; 427 428 e1000_release_phy(hw); 429 430 out: 431 return (ret_val); 432 } 433 434 /* 435 * e1000_write_kmrn_reg_generic - Write kumeran register 436 * @hw: pointer to the HW structure 437 * @offset: register offset to write to 438 * @data: data to write at register offset 439 * 440 * Acquires semaphore, if necessary. Then write the data to PHY register 441 * at the offset using the kumeran interface. Release any acquired semaphores 442 * before exiting. 443 */ 444 s32 445 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 446 { 447 u32 kmrnctrlsta; 448 s32 ret_val; 449 450 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 451 452 ret_val = e1000_acquire_phy(hw); 453 if (ret_val) 454 goto out; 455 456 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 457 E1000_KMRNCTRLSTA_OFFSET) | data; 458 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 459 460 usec_delay(2); 461 e1000_release_phy(hw); 462 463 out: 464 return (ret_val); 465 } 466 467 /* 468 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 469 * @hw: pointer to the HW structure 470 * 471 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 472 * and downshift values are set also. 473 */ 474 s32 475 e1000_copper_link_setup_m88(struct e1000_hw *hw) 476 { 477 struct e1000_phy_info *phy = &hw->phy; 478 s32 ret_val; 479 u16 phy_data; 480 481 DEBUGFUNC("e1000_copper_link_setup_m88"); 482 483 if (phy->reset_disable) { 484 ret_val = E1000_SUCCESS; 485 goto out; 486 } 487 488 /* Enable CRS on TX. This must be set for half-duplex operation. */ 489 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 490 if (ret_val) 491 goto out; 492 493 /* For newer PHYs this bit is downshift enable */ 494 if (phy->type == e1000_phy_m88) 495 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 496 497 /* 498 * Options: 499 * MDI/MDI-X = 0 (default) 500 * 0 - Auto for all speeds 501 * 1 - MDI mode 502 * 2 - MDI-X mode 503 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 504 */ 505 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 506 507 switch (phy->mdix) { 508 case 1: 509 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 510 break; 511 case 2: 512 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 513 break; 514 case 3: 515 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 516 break; 517 case 0: 518 default: 519 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 520 break; 521 } 522 523 /* 524 * Options: 525 * disable_polarity_correction = 0 (default) 526 * Automatic Correction for Reversed Cable Polarity 527 * 0 - Disabled 528 * 1 - Enabled 529 */ 530 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 531 if (phy->disable_polarity_correction == 1) 532 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 533 534 /* Enable downshift on BM (disabled by default) */ 535 if (phy->type == e1000_phy_bm) 536 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 537 538 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 539 if (ret_val) 540 goto out; 541 542 if ((phy->type == e1000_phy_m88) && 543 (phy->revision < E1000_REVISION_4) && 544 (phy->id != BME1000_E_PHY_ID_R2)) { 545 /* 546 * Force TX_CLK in the Extended PHY Specific Control Register 547 * to 25MHz clock. 548 */ 549 ret_val = e1000_read_phy_reg(hw, 550 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 551 if (ret_val) 552 goto out; 553 554 phy_data |= M88E1000_EPSCR_TX_CLK_25; 555 556 if ((phy->revision == E1000_REVISION_2) && 557 (phy->id == M88E1111_I_PHY_ID)) { 558 /* 82573L PHY - set the downshift counter to 5x. */ 559 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 560 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 561 } else { 562 /* Configure Master and Slave downshift values */ 563 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 564 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 565 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 566 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 567 } 568 ret_val = e1000_write_phy_reg(hw, 569 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 570 if (ret_val) 571 goto out; 572 } 573 574 /* Commit the changes. */ 575 ret_val = e1000_phy_commit(hw); 576 if (ret_val) { 577 DEBUGOUT("Error committing the PHY changes\n"); 578 goto out; 579 } 580 581 out: 582 return (ret_val); 583 } 584 585 /* 586 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 587 * @hw: pointer to the HW structure 588 * 589 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 590 * igp PHY's. 591 */ 592 s32 593 e1000_copper_link_setup_igp(struct e1000_hw *hw) 594 { 595 struct e1000_phy_info *phy = &hw->phy; 596 s32 ret_val; 597 u16 data; 598 599 DEBUGFUNC("e1000_copper_link_setup_igp"); 600 601 if (phy->reset_disable) { 602 ret_val = E1000_SUCCESS; 603 goto out; 604 } 605 606 ret_val = e1000_phy_hw_reset(hw); 607 if (ret_val) { 608 DEBUGOUT("Error resetting the PHY.\n"); 609 goto out; 610 } 611 612 /* Wait 15ms for MAC to configure PHY from NVM settings. */ 613 msec_delay(15); 614 615 /* 616 * The NVM settings will configure LPLU in D3 for 617 * non-IGP1 PHYs. 618 */ 619 if (phy->type == e1000_phy_igp) { 620 /* disable lplu d3 during driver init */ 621 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 622 if (ret_val) { 623 DEBUGOUT("Error Disabling LPLU D3\n"); 624 goto out; 625 } 626 } 627 628 /* disable lplu d0 during driver init */ 629 ret_val = e1000_set_d0_lplu_state(hw, FALSE); 630 if (ret_val) { 631 DEBUGOUT("Error Disabling LPLU D0\n"); 632 goto out; 633 } 634 /* Configure mdi-mdix settings */ 635 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 636 if (ret_val) 637 goto out; 638 639 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 640 641 switch (phy->mdix) { 642 case 1: 643 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 644 break; 645 case 2: 646 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 647 break; 648 case 0: 649 default: 650 data |= IGP01E1000_PSCR_AUTO_MDIX; 651 break; 652 } 653 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 654 if (ret_val) 655 goto out; 656 657 /* set auto-master slave resolution settings */ 658 if (hw->mac.autoneg) { 659 /* 660 * when autonegotiation advertisement is only 1000Mbps then we 661 * should disable SmartSpeed and enable Auto MasterSlave 662 * resolution as hardware default. 663 */ 664 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 665 /* Disable SmartSpeed */ 666 ret_val = e1000_read_phy_reg(hw, 667 IGP01E1000_PHY_PORT_CONFIG, &data); 668 if (ret_val) 669 goto out; 670 671 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 672 ret_val = e1000_write_phy_reg(hw, 673 IGP01E1000_PHY_PORT_CONFIG, data); 674 if (ret_val) 675 goto out; 676 677 /* Set auto Master/Slave resolution process */ 678 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data); 679 if (ret_val) 680 goto out; 681 682 data &= ~CR_1000T_MS_ENABLE; 683 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data); 684 if (ret_val) 685 goto out; 686 } 687 688 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data); 689 if (ret_val) 690 goto out; 691 692 /* load defaults for future use */ 693 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 694 ((data & CR_1000T_MS_VALUE) ? 695 e1000_ms_force_master : 696 e1000_ms_force_slave) : 697 e1000_ms_auto; 698 699 switch (phy->ms_type) { 700 case e1000_ms_force_master: 701 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 702 break; 703 case e1000_ms_force_slave: 704 data |= CR_1000T_MS_ENABLE; 705 data &= ~(CR_1000T_MS_VALUE); 706 break; 707 case e1000_ms_auto: 708 data &= ~CR_1000T_MS_ENABLE; 709 default: 710 break; 711 } 712 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data); 713 if (ret_val) 714 goto out; 715 } 716 717 out: 718 return (ret_val); 719 } 720 721 /* 722 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 723 * @hw: pointer to the HW structure 724 * 725 * Performs initial bounds checking on autoneg advertisement parameter, then 726 * configure to advertise the full capability. Setup the PHY to autoneg 727 * and restart the negotiation process between the link partner. If 728 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 729 */ 730 s32 731 e1000_copper_link_autoneg(struct e1000_hw *hw) 732 { 733 struct e1000_phy_info *phy = &hw->phy; 734 s32 ret_val; 735 u16 phy_ctrl; 736 737 DEBUGFUNC("e1000_copper_link_autoneg"); 738 739 /* 740 * Perform some bounds checking on the autoneg advertisement 741 * parameter. 742 */ 743 phy->autoneg_advertised &= phy->autoneg_mask; 744 745 /* 746 * If autoneg_advertised is zero, we assume it was not defaulted 747 * by the calling code so we set to advertise full capability. 748 */ 749 if (phy->autoneg_advertised == 0) 750 phy->autoneg_advertised = phy->autoneg_mask; 751 752 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 753 ret_val = e1000_phy_setup_autoneg(hw); 754 if (ret_val) { 755 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 756 goto out; 757 } 758 DEBUGOUT("Restarting Auto-Neg\n"); 759 760 /* 761 * Restart auto-negotiation by setting the Auto Neg Enable bit and 762 * the Auto Neg Restart bit in the PHY control register. 763 */ 764 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 765 if (ret_val) 766 goto out; 767 768 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 769 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 770 if (ret_val) 771 goto out; 772 773 /* 774 * Does the user want to wait for Auto-Neg to complete here, or 775 * check at a later time (for example, callback routine). 776 */ 777 if (phy->autoneg_wait_to_complete) { 778 ret_val = e1000_wait_autoneg(hw); 779 if (ret_val) { 780 DEBUGOUT("Error while waiting for " 781 "autoneg to complete\n"); 782 goto out; 783 } 784 } 785 786 hw->mac.get_link_status = TRUE; 787 788 out: 789 return (ret_val); 790 } 791 792 /* 793 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 794 * @hw: pointer to the HW structure 795 * 796 * Reads the MII auto-neg advertisement register and/or the 1000T control 797 * register and if the PHY is already setup for auto-negotiation, then 798 * return successful. Otherwise, setup advertisement and flow control to 799 * the appropriate values for the wanted auto-negotiation. 800 */ 801 s32 802 e1000_phy_setup_autoneg(struct e1000_hw *hw) 803 { 804 struct e1000_phy_info *phy = &hw->phy; 805 s32 ret_val; 806 u16 mii_autoneg_adv_reg; 807 u16 mii_1000t_ctrl_reg = 0; 808 809 DEBUGFUNC("e1000_phy_setup_autoneg"); 810 811 phy->autoneg_advertised &= phy->autoneg_mask; 812 813 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 814 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 815 if (ret_val) 816 goto out; 817 818 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 819 /* Read the MII 1000Base-T Control Register (Address 9). */ 820 ret_val = e1000_read_phy_reg(hw, 821 PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 822 if (ret_val) 823 goto out; 824 } 825 826 /* 827 * Need to parse both autoneg_advertised and fc and set up 828 * the appropriate PHY registers. First we will parse for 829 * autoneg_advertised software override. Since we can advertise 830 * a plethora of combinations, we need to check each bit 831 * individually. 832 */ 833 834 /* 835 * First we clear all the 10/100 mb speed bits in the Auto-Neg 836 * Advertisement Register (Address 4) and the 1000 mb speed bits in 837 * the 1000Base-T Control Register (Address 9). 838 */ 839 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 840 NWAY_AR_100TX_HD_CAPS | 841 NWAY_AR_10T_FD_CAPS | 842 NWAY_AR_10T_HD_CAPS); 843 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 844 845 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 846 847 /* Do we want to advertise 10 Mb Half Duplex? */ 848 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 849 DEBUGOUT("Advertise 10mb Half duplex\n"); 850 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 851 } 852 853 /* Do we want to advertise 10 Mb Full Duplex? */ 854 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 855 DEBUGOUT("Advertise 10mb Full duplex\n"); 856 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 857 } 858 859 /* Do we want to advertise 100 Mb Half Duplex? */ 860 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 861 DEBUGOUT("Advertise 100mb Half duplex\n"); 862 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 863 } 864 865 /* Do we want to advertise 100 Mb Full Duplex? */ 866 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 867 DEBUGOUT("Advertise 100mb Full duplex\n"); 868 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 869 } 870 871 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 872 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) { 873 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 874 } 875 876 /* Do we want to advertise 1000 Mb Full Duplex? */ 877 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 878 DEBUGOUT("Advertise 1000mb Full duplex\n"); 879 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 880 } 881 882 /* 883 * Check for a software override of the flow control settings, and 884 * setup the PHY advertisement registers accordingly. If 885 * auto-negotiation is enabled, then software will have to set the 886 * "PAUSE" bits to the correct value in the Auto-Negotiation 887 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 888 * negotiation. 889 * 890 * The possible values of the "fc" parameter are: 891 * 0: Flow control is completely disabled 892 * 1: Rx flow control is enabled (we can receive pause frames 893 * but not send pause frames). 894 * 2: Tx flow control is enabled (we can send pause frames 895 * but we do not support receiving pause frames). 896 * 3: Both Rx and Tx flow control (symmetric) are enabled. 897 * other: No software override. The flow control configuration 898 * in the EEPROM is used. 899 */ 900 switch (hw->fc.type) { 901 case e1000_fc_none: 902 /* 903 * Flow control (Rx & Tx) is completely disabled by a 904 * software over-ride. 905 */ 906 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 907 break; 908 case e1000_fc_rx_pause: 909 /* 910 * Rx Flow control is enabled, and Tx Flow control is 911 * disabled, by a software over-ride. 912 * 913 * Since there really isn't a way to advertise that we are 914 * capable of Rx Pause ONLY, we will advertise that we 915 * support both symmetric and asymmetric Rx PAUSE. Later 916 * (in e1000_config_fc_after_link_up) we will disable the 917 * hw's ability to send PAUSE frames. 918 */ 919 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 920 break; 921 case e1000_fc_tx_pause: 922 /* 923 * Tx Flow control is enabled, and Rx Flow control is 924 * disabled, by a software over-ride. 925 */ 926 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 927 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 928 break; 929 case e1000_fc_full: 930 /* 931 * Flow control (both Rx and Tx) is enabled by a software 932 * over-ride. 933 */ 934 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 935 break; 936 default: 937 DEBUGOUT("Flow control param set incorrectly\n"); 938 ret_val = -E1000_ERR_CONFIG; 939 goto out; 940 } 941 942 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 943 if (ret_val) 944 goto out; 945 946 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 947 948 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 949 ret_val = e1000_write_phy_reg(hw, 950 PHY_1000T_CTRL, mii_1000t_ctrl_reg); 951 if (ret_val) 952 goto out; 953 } 954 955 out: 956 return (ret_val); 957 } 958 959 /* 960 * e1000_setup_copper_link_generic - Configure copper link settings 961 * @hw: pointer to the HW structure 962 * 963 * Calls the appropriate function to configure the link for auto-neg or forced 964 * speed and duplex. Then we check for link, once link is established calls 965 * to configure collision distance and flow control are called. If link is 966 * not established, we return -E1000_ERR_PHY (-2). 967 */ 968 s32 969 e1000_setup_copper_link_generic(struct e1000_hw *hw) 970 { 971 s32 ret_val; 972 bool link; 973 974 DEBUGFUNC("e1000_setup_copper_link_generic"); 975 976 if (hw->mac.autoneg) { 977 /* 978 * Setup autoneg and flow control advertisement and perform 979 * autonegotiation. 980 */ 981 ret_val = e1000_copper_link_autoneg(hw); 982 if (ret_val) 983 goto out; 984 } else { 985 /* 986 * PHY will be set to 10H, 10F, 100H or 100F 987 * depending on user settings. 988 */ 989 DEBUGOUT("Forcing Speed and Duplex\n"); 990 ret_val = e1000_phy_force_speed_duplex(hw); 991 if (ret_val) { 992 DEBUGOUT("Error Forcing Speed and Duplex\n"); 993 goto out; 994 } 995 } 996 997 /* 998 * Check link status. Wait up to 100 microseconds for link to become 999 * valid. 1000 */ 1001 ret_val = e1000_phy_has_link_generic(hw, 1002 COPPER_LINK_UP_LIMIT, 1003 10, 1004 &link); 1005 if (ret_val) 1006 goto out; 1007 1008 if (link) { 1009 DEBUGOUT("Valid link established!!!\n"); 1010 e1000_config_collision_dist_generic(hw); 1011 ret_val = e1000_config_fc_after_link_up_generic(hw); 1012 } else { 1013 DEBUGOUT("Unable to establish link!!!\n"); 1014 } 1015 1016 out: 1017 return (ret_val); 1018 } 1019 1020 /* 1021 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1022 * @hw: pointer to the HW structure 1023 * 1024 * Calls the PHY setup function to force speed and duplex. Clears the 1025 * auto-crossover to force MDI manually. Waits for link and returns 1026 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1027 */ 1028 s32 1029 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1030 { 1031 struct e1000_phy_info *phy = &hw->phy; 1032 s32 ret_val; 1033 u16 phy_data; 1034 bool link; 1035 1036 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1037 1038 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 1039 if (ret_val) 1040 goto out; 1041 1042 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1043 1044 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 1045 if (ret_val) 1046 goto out; 1047 1048 /* 1049 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1050 * forced whenever speed and duplex are forced. 1051 */ 1052 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1053 if (ret_val) 1054 goto out; 1055 1056 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1057 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1058 1059 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1060 if (ret_val) 1061 goto out; 1062 1063 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1064 1065 usec_delay(1); 1066 1067 if (phy->autoneg_wait_to_complete) { 1068 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1069 1070 ret_val = e1000_phy_has_link_generic(hw, 1071 PHY_FORCE_LIMIT, 1072 100000, 1073 &link); 1074 if (ret_val) 1075 goto out; 1076 1077 if (!link) { 1078 DEBUGOUT("Link taking longer than expected.\n"); 1079 } 1080 1081 /* Try once more */ 1082 ret_val = e1000_phy_has_link_generic(hw, 1083 PHY_FORCE_LIMIT, 1084 100000, 1085 &link); 1086 if (ret_val) 1087 goto out; 1088 } 1089 1090 out: 1091 return (ret_val); 1092 } 1093 1094 /* 1095 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1096 * @hw: pointer to the HW structure 1097 * 1098 * Calls the PHY setup function to force speed and duplex. Clears the 1099 * auto-crossover to force MDI manually. Resets the PHY to commit the 1100 * changes. If time expires while waiting for link up, we reset the DSP. 1101 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1102 * successful completion, else return corresponding error code. 1103 */ 1104 s32 1105 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1106 { 1107 struct e1000_phy_info *phy = &hw->phy; 1108 s32 ret_val; 1109 u16 phy_data; 1110 bool link; 1111 1112 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1113 1114 /* 1115 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1116 * forced whenever speed and duplex are forced. 1117 */ 1118 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1119 if (ret_val) 1120 goto out; 1121 1122 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1123 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1124 if (ret_val) 1125 goto out; 1126 1127 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1128 1129 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 1130 if (ret_val) 1131 goto out; 1132 1133 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1134 1135 /* Reset the phy to commit changes. */ 1136 phy_data |= MII_CR_RESET; 1137 1138 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 1139 if (ret_val) 1140 goto out; 1141 1142 usec_delay(1); 1143 1144 if (phy->autoneg_wait_to_complete) { 1145 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1146 1147 ret_val = e1000_phy_has_link_generic(hw, 1148 PHY_FORCE_LIMIT, 1149 100000, 1150 &link); 1151 if (ret_val) 1152 goto out; 1153 1154 if (!link) { 1155 /* 1156 * We didn't get link. 1157 * Reset the DSP and cross our fingers. 1158 */ 1159 ret_val = e1000_write_phy_reg(hw, 1160 M88E1000_PHY_PAGE_SELECT, 1161 0x001d); 1162 if (ret_val) 1163 goto out; 1164 ret_val = e1000_phy_reset_dsp_generic(hw); 1165 if (ret_val) 1166 goto out; 1167 } 1168 1169 /* Try once more */ 1170 ret_val = e1000_phy_has_link_generic(hw, 1171 PHY_FORCE_LIMIT, 1172 100000, 1173 &link); 1174 if (ret_val) 1175 goto out; 1176 } 1177 1178 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1179 if (ret_val) 1180 goto out; 1181 1182 /* 1183 * Resetting the phy means we need to re-force TX_CLK in the 1184 * Extended PHY Specific Control Register to 25MHz clock from 1185 * the reset value of 2.5MHz. 1186 */ 1187 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1188 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1189 if (ret_val) 1190 goto out; 1191 1192 /* 1193 * In addition, we must re-enable CRS on Tx for both half and full 1194 * duplex. 1195 */ 1196 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1197 if (ret_val) 1198 goto out; 1199 1200 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1201 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1202 1203 out: 1204 return (ret_val); 1205 } 1206 1207 /* 1208 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1209 * @hw: pointer to the HW structure 1210 * @phy_ctrl: pointer to current value of PHY_CONTROL 1211 * 1212 * Forces speed and duplex on the PHY by doing the following: disable flow 1213 * control, force speed/duplex on the MAC, disable auto speed detection, 1214 * disable auto-negotiation, configure duplex, configure speed, configure 1215 * the collision distance, write configuration to CTRL register. The 1216 * caller must write to the PHY_CONTROL register for these settings to 1217 * take affect. 1218 */ 1219 void 1220 e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1221 { 1222 struct e1000_mac_info *mac = &hw->mac; 1223 u32 ctrl; 1224 1225 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1226 1227 /* Turn off flow control when forcing speed/duplex */ 1228 hw->fc.type = e1000_fc_none; 1229 1230 /* Force speed/duplex on the mac */ 1231 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1232 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1233 ctrl &= ~E1000_CTRL_SPD_SEL; 1234 1235 /* Disable Auto Speed Detection */ 1236 ctrl &= ~E1000_CTRL_ASDE; 1237 1238 /* Disable autoneg on the phy */ 1239 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1240 1241 /* Forcing Full or Half Duplex? */ 1242 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1243 ctrl &= ~E1000_CTRL_FD; 1244 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1245 DEBUGOUT("Half Duplex\n"); 1246 } else { 1247 ctrl |= E1000_CTRL_FD; 1248 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1249 DEBUGOUT("Full Duplex\n"); 1250 } 1251 1252 /* Forcing 10mb or 100mb? */ 1253 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1254 ctrl |= E1000_CTRL_SPD_100; 1255 *phy_ctrl |= MII_CR_SPEED_100; 1256 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1257 DEBUGOUT("Forcing 100mb\n"); 1258 } else { 1259 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1260 /* LINTED */ 1261 *phy_ctrl |= MII_CR_SPEED_10; 1262 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1263 DEBUGOUT("Forcing 10mb\n"); 1264 } 1265 1266 e1000_config_collision_dist_generic(hw); 1267 1268 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1269 } 1270 1271 /* 1272 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1273 * @hw: pointer to the HW structure 1274 * @active: boolean used to enable/disable lplu 1275 * 1276 * Success returns 0, Failure returns 1 1277 * 1278 * The low power link up (lplu) state is set to the power management level D3 1279 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1280 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1281 * is used during Dx states where the power conservation is most important. 1282 * During driver activity, SmartSpeed should be enabled so performance is 1283 * maintained. 1284 */ 1285 s32 1286 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1287 { 1288 struct e1000_phy_info *phy = &hw->phy; 1289 s32 ret_val; 1290 u16 data; 1291 1292 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1293 1294 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1295 if (ret_val) 1296 goto out; 1297 1298 if (!active) { 1299 data &= ~IGP02E1000_PM_D3_LPLU; 1300 ret_val = e1000_write_phy_reg(hw, 1301 IGP02E1000_PHY_POWER_MGMT, 1302 data); 1303 if (ret_val) 1304 goto out; 1305 /* 1306 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1307 * during Dx states where the power conservation is most 1308 * important. During driver activity we should enable 1309 * SmartSpeed, so performance is maintained. 1310 */ 1311 if (phy->smart_speed == e1000_smart_speed_on) { 1312 ret_val = e1000_read_phy_reg(hw, 1313 IGP01E1000_PHY_PORT_CONFIG, 1314 &data); 1315 if (ret_val) 1316 goto out; 1317 1318 data |= IGP01E1000_PSCFR_SMART_SPEED; 1319 ret_val = e1000_write_phy_reg(hw, 1320 IGP01E1000_PHY_PORT_CONFIG, 1321 data); 1322 if (ret_val) 1323 goto out; 1324 } else if (phy->smart_speed == e1000_smart_speed_off) { 1325 ret_val = e1000_read_phy_reg(hw, 1326 IGP01E1000_PHY_PORT_CONFIG, 1327 &data); 1328 if (ret_val) 1329 goto out; 1330 1331 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1332 ret_val = e1000_write_phy_reg(hw, 1333 IGP01E1000_PHY_PORT_CONFIG, 1334 data); 1335 if (ret_val) 1336 goto out; 1337 } 1338 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1339 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1340 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1341 data |= IGP02E1000_PM_D3_LPLU; 1342 ret_val = e1000_write_phy_reg(hw, 1343 IGP02E1000_PHY_POWER_MGMT, 1344 data); 1345 if (ret_val) 1346 goto out; 1347 1348 /* When LPLU is enabled, we should disable SmartSpeed */ 1349 ret_val = e1000_read_phy_reg(hw, 1350 IGP01E1000_PHY_PORT_CONFIG, 1351 &data); 1352 if (ret_val) 1353 goto out; 1354 1355 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1356 ret_val = e1000_write_phy_reg(hw, 1357 IGP01E1000_PHY_PORT_CONFIG, 1358 data); 1359 } 1360 1361 out: 1362 return (ret_val); 1363 } 1364 1365 /* 1366 * e1000_check_downshift_generic - Checks whether a downshift in speed occured 1367 * @hw: pointer to the HW structure 1368 * 1369 * Success returns 0, Failure returns 1 1370 * 1371 * A downshift is detected by querying the PHY link health. 1372 */ 1373 s32 1374 e1000_check_downshift_generic(struct e1000_hw *hw) 1375 { 1376 struct e1000_phy_info *phy = &hw->phy; 1377 s32 ret_val; 1378 u16 phy_data, offset, mask; 1379 1380 DEBUGFUNC("e1000_check_downshift_generic"); 1381 1382 switch (phy->type) { 1383 case e1000_phy_m88: 1384 case e1000_phy_gg82563: 1385 case e1000_phy_bm: 1386 offset = M88E1000_PHY_SPEC_STATUS; 1387 mask = M88E1000_PSSR_DOWNSHIFT; 1388 break; 1389 case e1000_phy_igp_2: 1390 case e1000_phy_igp: 1391 case e1000_phy_igp_3: 1392 offset = IGP01E1000_PHY_LINK_HEALTH; 1393 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1394 break; 1395 default: 1396 /* speed downshift not supported */ 1397 phy->speed_downgraded = FALSE; 1398 ret_val = E1000_SUCCESS; 1399 goto out; 1400 } 1401 1402 ret_val = e1000_read_phy_reg(hw, offset, &phy_data); 1403 1404 if (!ret_val) 1405 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1406 1407 out: 1408 return (ret_val); 1409 } 1410 1411 /* 1412 * e1000_check_polarity_m88 - Checks the polarity. 1413 * @hw: pointer to the HW structure 1414 * 1415 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1416 * 1417 * Polarity is determined based on the PHY specific status register. 1418 */ 1419 s32 1420 e1000_check_polarity_m88(struct e1000_hw *hw) 1421 { 1422 struct e1000_phy_info *phy = &hw->phy; 1423 s32 ret_val; 1424 u16 data; 1425 1426 DEBUGFUNC("e1000_check_polarity_m88"); 1427 1428 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1429 1430 if (!ret_val) 1431 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1432 ? e1000_rev_polarity_reversed 1433 : e1000_rev_polarity_normal; 1434 1435 return (ret_val); 1436 } 1437 1438 /* 1439 * e1000_check_polarity_igp - Checks the polarity. 1440 * @hw: pointer to the HW structure 1441 * 1442 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1443 * 1444 * Polarity is determined based on the PHY port status register, and the 1445 * current speed (since there is no polarity at 100Mbps). 1446 */ 1447 s32 1448 e1000_check_polarity_igp(struct e1000_hw *hw) 1449 { 1450 struct e1000_phy_info *phy = &hw->phy; 1451 s32 ret_val; 1452 u16 data, offset, mask; 1453 1454 DEBUGFUNC("e1000_check_polarity_igp"); 1455 1456 /* 1457 * Polarity is determined based on the speed of 1458 * our connection. 1459 */ 1460 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1461 if (ret_val) 1462 goto out; 1463 1464 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1465 IGP01E1000_PSSR_SPEED_1000MBPS) { 1466 offset = IGP01E1000_PHY_PCS_INIT_REG; 1467 mask = IGP01E1000_PHY_POLARITY_MASK; 1468 } else { 1469 /* 1470 * This really only applies to 10Mbps since 1471 * there is no polarity for 100Mbps (always 0). 1472 */ 1473 offset = IGP01E1000_PHY_PORT_STATUS; 1474 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1475 } 1476 1477 ret_val = e1000_read_phy_reg(hw, offset, &data); 1478 1479 if (!ret_val) 1480 phy->cable_polarity = (data & mask) 1481 ? e1000_rev_polarity_reversed 1482 : e1000_rev_polarity_normal; 1483 1484 out: 1485 return (ret_val); 1486 } 1487 1488 /* 1489 * e1000_wait_autoneg_generic - Wait for auto-neg compeletion 1490 * @hw: pointer to the HW structure 1491 * 1492 * Waits for auto-negotiation to complete or for the auto-negotiation time 1493 * limit to expire, which ever happens first. 1494 */ 1495 s32 1496 e1000_wait_autoneg_generic(struct e1000_hw *hw) 1497 { 1498 s32 ret_val = E1000_SUCCESS; 1499 u16 i, phy_status; 1500 1501 DEBUGFUNC("e1000_wait_autoneg_generic"); 1502 1503 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1504 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1505 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1506 if (ret_val) 1507 break; 1508 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1509 if (ret_val) 1510 break; 1511 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1512 break; 1513 msec_delay(100); 1514 } 1515 1516 /* 1517 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1518 * has completed. 1519 */ 1520 return (ret_val); 1521 } 1522 1523 /* 1524 * e1000_phy_has_link_generic - Polls PHY for link 1525 * @hw: pointer to the HW structure 1526 * @iterations: number of times to poll for link 1527 * @usec_interval: delay between polling attempts 1528 * @success: pointer to whether polling was successful or not 1529 * 1530 * Polls the PHY status register for link, 'iterations' number of times. 1531 */ 1532 s32 1533 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1534 u32 usec_interval, bool *success) 1535 { 1536 s32 ret_val = E1000_SUCCESS; 1537 u16 i, phy_status; 1538 1539 DEBUGFUNC("e1000_phy_has_link_generic"); 1540 1541 for (i = 0; i < iterations; i++) { 1542 /* 1543 * Some PHYs require the PHY_STATUS register to be read 1544 * twice due to the link bit being sticky. No harm doing 1545 * it across the board. 1546 */ 1547 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1548 if (ret_val) 1549 break; 1550 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1551 if (ret_val) 1552 break; 1553 if (phy_status & MII_SR_LINK_STATUS) 1554 break; 1555 if (usec_interval >= 1000) 1556 msec_delay_irq(usec_interval/1000); 1557 else 1558 usec_delay(usec_interval); 1559 } 1560 1561 *success = (i < iterations) ? TRUE : FALSE; 1562 1563 return (ret_val); 1564 } 1565 1566 /* 1567 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1568 * @hw: pointer to the HW structure 1569 * 1570 * Reads the PHY specific status register to retrieve the cable length 1571 * information. The cable length is determined by averaging the minimum and 1572 * maximum values to get the "average" cable length. The m88 PHY has four 1573 * possible cable length values, which are: 1574 * Register Value Cable Length 1575 * 0 < 50 meters 1576 * 1 50 - 80 meters 1577 * 2 80 - 110 meters 1578 * 3 110 - 140 meters 1579 * 4 > 140 meters 1580 */ 1581 s32 1582 e1000_get_cable_length_m88(struct e1000_hw *hw) 1583 { 1584 struct e1000_phy_info *phy = &hw->phy; 1585 s32 ret_val; 1586 u16 phy_data, index; 1587 1588 DEBUGFUNC("e1000_get_cable_length_m88"); 1589 1590 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1591 if (ret_val) 1592 goto out; 1593 1594 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1595 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1596 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1597 phy->max_cable_length = e1000_m88_cable_length_table[index+1]; 1598 1599 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1600 1601 out: 1602 return (ret_val); 1603 } 1604 1605 /* 1606 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1607 * @hw: pointer to the HW structure 1608 * 1609 * The automatic gain control (agc) normalizes the amplitude of the 1610 * received signal, adjusting for the attenuation produced by the 1611 * cable. By reading the AGC registers, which reperesent the 1612 * cobination of course and fine gain value, the value can be put 1613 * into a lookup table to obtain the approximate cable length 1614 * for each channel. 1615 */ 1616 s32 1617 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 1618 { 1619 struct e1000_phy_info *phy = &hw->phy; 1620 s32 ret_val = E1000_SUCCESS; 1621 u16 phy_data, i, agc_value = 0; 1622 u16 cur_agc_index, max_agc_index = 0; 1623 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1624 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 1625 {IGP02E1000_PHY_AGC_A, 1626 IGP02E1000_PHY_AGC_B, 1627 IGP02E1000_PHY_AGC_C, 1628 IGP02E1000_PHY_AGC_D}; 1629 1630 DEBUGFUNC("e1000_get_cable_length_igp_2"); 1631 1632 /* Read the AGC registers for all channels */ 1633 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1634 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 1635 if (ret_val) 1636 goto out; 1637 1638 /* 1639 * Getting bits 15:9, which represent the combination of 1640 * course and fine gain values. The result is a number 1641 * that can be put into the lookup table to obtain the 1642 * approximate cable length. 1643 */ 1644 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1645 IGP02E1000_AGC_LENGTH_MASK; 1646 1647 /* Array index bound check. */ 1648 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1649 (cur_agc_index == 0)) { 1650 ret_val = -E1000_ERR_PHY; 1651 goto out; 1652 } 1653 1654 /* Remove min & max AGC values from calculation. */ 1655 if (e1000_igp_2_cable_length_table[min_agc_index] > 1656 e1000_igp_2_cable_length_table[cur_agc_index]) 1657 min_agc_index = cur_agc_index; 1658 if (e1000_igp_2_cable_length_table[max_agc_index] < 1659 e1000_igp_2_cable_length_table[cur_agc_index]) 1660 max_agc_index = cur_agc_index; 1661 1662 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1663 } 1664 1665 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1666 e1000_igp_2_cable_length_table[max_agc_index]); 1667 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1668 1669 /* Calculate cable length with the error range of +/- 10 meters. */ 1670 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1671 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1672 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1673 1674 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1675 1676 out: 1677 return (ret_val); 1678 } 1679 1680 /* 1681 * e1000_get_phy_info_m88 - Retrieve PHY information 1682 * @hw: pointer to the HW structure 1683 * 1684 * Valid for only copper links. Read the PHY status register (sticky read) 1685 * to verify that link is up. Read the PHY special control register to 1686 * determine the polarity and 10base-T extended distance. Read the PHY 1687 * special status register to determine MDI/MDIx and current speed. If 1688 * speed is 1000, then determine cable length, local and remote receiver. 1689 */ 1690 s32 1691 e1000_get_phy_info_m88(struct e1000_hw *hw) 1692 { 1693 struct e1000_phy_info *phy = &hw->phy; 1694 s32 ret_val; 1695 u16 phy_data; 1696 bool link; 1697 1698 DEBUGFUNC("e1000_get_phy_info_m88"); 1699 1700 if (hw->phy.media_type != e1000_media_type_copper) { 1701 DEBUGOUT("Phy info is only valid for copper media\n"); 1702 ret_val = -E1000_ERR_CONFIG; 1703 goto out; 1704 } 1705 1706 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1707 if (ret_val) 1708 goto out; 1709 1710 if (!link) { 1711 DEBUGOUT("Phy info is only valid if link is up\n"); 1712 ret_val = -E1000_ERR_CONFIG; 1713 goto out; 1714 } 1715 1716 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1717 if (ret_val) 1718 goto out; 1719 1720 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1721 ? TRUE 1722 : FALSE; 1723 1724 ret_val = e1000_check_polarity_m88(hw); 1725 if (ret_val) 1726 goto out; 1727 1728 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1729 if (ret_val) 1730 goto out; 1731 1732 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 1733 1734 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1735 ret_val = e1000_get_cable_length(hw); 1736 if (ret_val) 1737 goto out; 1738 1739 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 1740 if (ret_val) 1741 goto out; 1742 1743 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1744 ? e1000_1000t_rx_status_ok 1745 : e1000_1000t_rx_status_not_ok; 1746 1747 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1748 ? e1000_1000t_rx_status_ok 1749 : e1000_1000t_rx_status_not_ok; 1750 } else { 1751 /* Set values to "undefined" */ 1752 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1753 phy->local_rx = e1000_1000t_rx_status_undefined; 1754 phy->remote_rx = e1000_1000t_rx_status_undefined; 1755 } 1756 1757 out: 1758 return (ret_val); 1759 } 1760 1761 /* 1762 * e1000_get_phy_info_igp - Retrieve igp PHY information 1763 * @hw: pointer to the HW structure 1764 * 1765 * Read PHY status to determine if link is up. If link is up, then 1766 * set/determine 10base-T extended distance and polarity correction. Read 1767 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1768 * determine on the cable length, local and remote receiver. 1769 */ 1770 s32 1771 e1000_get_phy_info_igp(struct e1000_hw *hw) 1772 { 1773 struct e1000_phy_info *phy = &hw->phy; 1774 s32 ret_val; 1775 u16 data; 1776 bool link; 1777 1778 DEBUGFUNC("e1000_get_phy_info_igp"); 1779 1780 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1781 if (ret_val) 1782 goto out; 1783 1784 if (!link) { 1785 DEBUGOUT("Phy info is only valid if link is up\n"); 1786 ret_val = -E1000_ERR_CONFIG; 1787 goto out; 1788 } 1789 1790 phy->polarity_correction = TRUE; 1791 1792 ret_val = e1000_check_polarity_igp(hw); 1793 if (ret_val) 1794 goto out; 1795 1796 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1797 if (ret_val) 1798 goto out; 1799 1800 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 1801 1802 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1803 IGP01E1000_PSSR_SPEED_1000MBPS) { 1804 ret_val = e1000_get_cable_length(hw); 1805 if (ret_val) 1806 goto out; 1807 1808 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &data); 1809 if (ret_val) 1810 goto out; 1811 1812 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 1813 ? e1000_1000t_rx_status_ok 1814 : e1000_1000t_rx_status_not_ok; 1815 1816 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 1817 ? e1000_1000t_rx_status_ok 1818 : e1000_1000t_rx_status_not_ok; 1819 } else { 1820 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1821 phy->local_rx = e1000_1000t_rx_status_undefined; 1822 phy->remote_rx = e1000_1000t_rx_status_undefined; 1823 } 1824 1825 out: 1826 return (ret_val); 1827 } 1828 1829 /* 1830 * e1000_phy_sw_reset_generic - PHY software reset 1831 * @hw: pointer to the HW structure 1832 * 1833 * Does a software reset of the PHY by reading the PHY control register and 1834 * setting/write the control register reset bit to the PHY. 1835 */ 1836 s32 1837 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 1838 { 1839 s32 ret_val; 1840 u16 phy_ctrl; 1841 1842 DEBUGFUNC("e1000_phy_sw_reset_generic"); 1843 1844 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 1845 if (ret_val) 1846 goto out; 1847 1848 phy_ctrl |= MII_CR_RESET; 1849 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 1850 if (ret_val) 1851 goto out; 1852 1853 usec_delay(1); 1854 1855 out: 1856 return (ret_val); 1857 } 1858 1859 /* 1860 * e1000_phy_hw_reset_generic - PHY hardware reset 1861 * @hw: pointer to the HW structure 1862 * 1863 * Verify the reset block is not blocking us from resetting. Acquire 1864 * semaphore (if necessary) and read/set/write the device control reset 1865 * bit in the PHY. Wait the appropriate delay time for the device to 1866 * reset and relase the semaphore (if necessary). 1867 */ 1868 s32 1869 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 1870 { 1871 struct e1000_phy_info *phy = &hw->phy; 1872 s32 ret_val; 1873 u32 ctrl; 1874 1875 DEBUGFUNC("e1000_phy_hw_reset_generic"); 1876 1877 ret_val = e1000_check_reset_block(hw); 1878 if (ret_val) { 1879 ret_val = E1000_SUCCESS; 1880 goto out; 1881 } 1882 1883 ret_val = e1000_acquire_phy(hw); 1884 if (ret_val) 1885 goto out; 1886 1887 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1888 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 1889 E1000_WRITE_FLUSH(hw); 1890 1891 usec_delay(phy->reset_delay_us); 1892 1893 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1894 E1000_WRITE_FLUSH(hw); 1895 1896 usec_delay(150); 1897 1898 e1000_release_phy(hw); 1899 1900 ret_val = e1000_get_phy_cfg_done(hw); 1901 1902 out: 1903 return (ret_val); 1904 } 1905 1906 /* 1907 * e1000_get_cfg_done_generic - Generic configuration done 1908 * @hw: pointer to the HW structure 1909 * 1910 * Generic function to wait 10 milli-seconds for configuration to complete 1911 * and return success. 1912 */ 1913 s32 1914 e1000_get_cfg_done_generic(struct e1000_hw *hw) 1915 { 1916 DEBUGFUNC("e1000_get_cfg_done_generic"); 1917 UNREFERENCED_PARAMETER(hw); 1918 1919 msec_delay_irq(10); 1920 1921 return (E1000_SUCCESS); 1922 } 1923 1924 /* Internal function pointers */ 1925 1926 /* 1927 * e1000_get_phy_cfg_done - Generic PHY configuration done 1928 * @hw: pointer to the HW structure 1929 * 1930 * Return success if silicon family did not implement a family specific 1931 * get_cfg_done function. 1932 */ 1933 static s32 1934 e1000_get_phy_cfg_done(struct e1000_hw *hw) 1935 { 1936 if (hw->func.get_cfg_done) 1937 return (hw->func.get_cfg_done(hw)); 1938 1939 return (E1000_SUCCESS); 1940 } 1941 1942 /* 1943 * e1000_release_phy - Generic release PHY 1944 * @hw: pointer to the HW structure 1945 * 1946 * Return if silicon family does not require a semaphore when accessing the 1947 * PHY. 1948 */ 1949 static void 1950 e1000_release_phy(struct e1000_hw *hw) 1951 { 1952 if (hw->func.release_phy) 1953 hw->func.release_phy(hw); 1954 } 1955 1956 /* 1957 * e1000_acquire_phy - Generic acquire PHY 1958 * @hw: pointer to the HW structure 1959 * 1960 * Return success if silicon family does not require a semaphore when 1961 * accessing the PHY. 1962 */ 1963 static s32 1964 e1000_acquire_phy(struct e1000_hw *hw) 1965 { 1966 if (hw->func.acquire_phy) 1967 return (hw->func.acquire_phy(hw)); 1968 1969 return (E1000_SUCCESS); 1970 } 1971 1972 /* 1973 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex 1974 * @hw: pointer to the HW structure 1975 * 1976 * When the silicon family has not implemented a forced speed/duplex 1977 * function for the PHY, simply return (E1000_SUCCESS). 1978 */ 1979 s32 1980 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1981 { 1982 if (hw->func.force_speed_duplex) 1983 return (hw->func.force_speed_duplex(hw)); 1984 1985 return (E1000_SUCCESS); 1986 } 1987 1988 /* 1989 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 1990 * @hw: pointer to the HW structure 1991 * 1992 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 1993 */ 1994 s32 1995 e1000_phy_init_script_igp3(struct e1000_hw *hw) 1996 { 1997 DEBUGOUT("Running IGP 3 PHY init script\n"); 1998 1999 /* PHY init IGP 3 */ 2000 /* Enable rise/fall, 10-mode work in class-A */ 2001 (void) e1000_write_phy_reg(hw, 0x2F5B, 0x9018); 2002 /* Remove all caps from Replica path filter */ 2003 (void) e1000_write_phy_reg(hw, 0x2F52, 0x0000); 2004 /* Bias trimming for ADC, AFE and Driver (Default) */ 2005 (void) e1000_write_phy_reg(hw, 0x2FB1, 0x8B24); 2006 /* Increase Hybrid poly bias */ 2007 (void) e1000_write_phy_reg(hw, 0x2FB2, 0xF8F0); 2008 /* Add 4% to Tx amplitude in Giga mode */ 2009 (void) e1000_write_phy_reg(hw, 0x2010, 0x10B0); 2010 /* Disable trimming (TTT) */ 2011 (void) e1000_write_phy_reg(hw, 0x2011, 0x0000); 2012 /* Poly DC correction to 94.6% + 2% for all channels */ 2013 (void) e1000_write_phy_reg(hw, 0x20DD, 0x249A); 2014 /* ABS DC correction to 95.9% */ 2015 (void) e1000_write_phy_reg(hw, 0x20DE, 0x00D3); 2016 /* BG temp curve trim */ 2017 (void) e1000_write_phy_reg(hw, 0x28B4, 0x04CE); 2018 /* Increasing ADC OPAMP stage 1 currents to max */ 2019 (void) e1000_write_phy_reg(hw, 0x2F70, 0x29E4); 2020 /* Force 1000 ( required for enabling PHY regs configuration) */ 2021 (void) e1000_write_phy_reg(hw, 0x0000, 0x0140); 2022 /* Set upd_freq to 6 */ 2023 (void) e1000_write_phy_reg(hw, 0x1F30, 0x1606); 2024 /* Disable NPDFE */ 2025 (void) e1000_write_phy_reg(hw, 0x1F31, 0xB814); 2026 /* Disable adaptive fixed FFE (Default) */ 2027 (void) e1000_write_phy_reg(hw, 0x1F35, 0x002A); 2028 /* Enable FFE hysteresis */ 2029 (void) e1000_write_phy_reg(hw, 0x1F3E, 0x0067); 2030 /* Fixed FFE for short cable lengths */ 2031 (void) e1000_write_phy_reg(hw, 0x1F54, 0x0065); 2032 /* Fixed FFE for medium cable lengths */ 2033 (void) e1000_write_phy_reg(hw, 0x1F55, 0x002A); 2034 /* Fixed FFE for long cable lengths */ 2035 (void) e1000_write_phy_reg(hw, 0x1F56, 0x002A); 2036 /* Enable Adaptive Clip Threshold */ 2037 (void) e1000_write_phy_reg(hw, 0x1F72, 0x3FB0); 2038 /* AHT reset limit to 1 */ 2039 (void) e1000_write_phy_reg(hw, 0x1F76, 0xC0FF); 2040 /* Set AHT master delay to 127 msec */ 2041 (void) e1000_write_phy_reg(hw, 0x1F77, 0x1DEC); 2042 /* Set scan bits for AHT */ 2043 (void) e1000_write_phy_reg(hw, 0x1F78, 0xF9EF); 2044 /* Set AHT Preset bits */ 2045 (void) e1000_write_phy_reg(hw, 0x1F79, 0x0210); 2046 /* Change integ_factor of channel A to 3 */ 2047 (void) e1000_write_phy_reg(hw, 0x1895, 0x0003); 2048 /* Change prop_factor of channels BCD to 8 */ 2049 (void) e1000_write_phy_reg(hw, 0x1796, 0x0008); 2050 /* Change cg_icount + enable integbp for channels BCD */ 2051 (void) e1000_write_phy_reg(hw, 0x1798, 0xD008); 2052 /* 2053 * Change cg_icount + enable integbp + change prop_factor_master 2054 * to 8 for channel A 2055 */ 2056 (void) e1000_write_phy_reg(hw, 0x1898, 0xD918); 2057 /* Disable AHT in Slave mode on channel A */ 2058 (void) e1000_write_phy_reg(hw, 0x187A, 0x0800); 2059 /* 2060 * Enable LPLU and disable AN to 1000 in non-D0a states, 2061 * Enable SPD+B2B 2062 */ 2063 (void) e1000_write_phy_reg(hw, 0x0019, 0x008D); 2064 /* Enable restart AN on an1000_dis change */ 2065 (void) e1000_write_phy_reg(hw, 0x001B, 0x2080); 2066 /* Enable wh_fifo read clock in 10/100 modes */ 2067 (void) e1000_write_phy_reg(hw, 0x0014, 0x0045); 2068 /* Restart AN, Speed selection is 1000 */ 2069 (void) e1000_write_phy_reg(hw, 0x0000, 0x1340); 2070 2071 return (E1000_SUCCESS); 2072 } 2073 2074 /* 2075 * e1000_get_phy_type_from_id - Get PHY type from id 2076 * @phy_id: phy_id read from the phy 2077 * 2078 * Returns the phy type from the id. 2079 */ 2080 e1000_phy_type 2081 e1000_get_phy_type_from_id(u32 phy_id) 2082 { 2083 e1000_phy_type phy_type = e1000_phy_unknown; 2084 2085 switch (phy_id) { 2086 case M88E1000_I_PHY_ID: 2087 case M88E1000_E_PHY_ID: 2088 case M88E1111_I_PHY_ID: 2089 case M88E1011_I_PHY_ID: 2090 phy_type = e1000_phy_m88; 2091 break; 2092 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2093 phy_type = e1000_phy_igp_2; 2094 break; 2095 case GG82563_E_PHY_ID: 2096 phy_type = e1000_phy_gg82563; 2097 break; 2098 case IGP03E1000_E_PHY_ID: 2099 phy_type = e1000_phy_igp_3; 2100 break; 2101 case IFE_E_PHY_ID: 2102 case IFE_PLUS_E_PHY_ID: 2103 case IFE_C_E_PHY_ID: 2104 phy_type = e1000_phy_ife; 2105 break; 2106 case BME1000_E_PHY_ID: 2107 case BME1000_E_PHY_ID_R2: 2108 phy_type = e1000_phy_bm; 2109 break; 2110 default: 2111 phy_type = e1000_phy_unknown; 2112 break; 2113 } 2114 return (phy_type); 2115 } 2116 2117 /* 2118 * e1000_determine_phy_address - Determines PHY address. 2119 * @hw: pointer to the HW structure 2120 * 2121 * This uses a trial and error method to loop through possible PHY 2122 * addresses. It tests each by reading the PHY ID registers and 2123 * checking for a match. 2124 */ 2125 s32 2126 e1000_determine_phy_address(struct e1000_hw *hw) 2127 { 2128 s32 ret_val = -E1000_ERR_PHY_TYPE; 2129 u32 phy_addr = 0; 2130 u32 i = 0; 2131 e1000_phy_type phy_type = e1000_phy_unknown; 2132 2133 do { 2134 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2135 hw->phy.addr = phy_addr; 2136 (void) e1000_get_phy_id(hw); 2137 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2138 2139 /* 2140 * If phy_type is valid, break - we found our 2141 * PHY address 2142 */ 2143 if (phy_type != e1000_phy_unknown) { 2144 ret_val = E1000_SUCCESS; 2145 break; 2146 } 2147 } 2148 i++; 2149 } while ((ret_val != E1000_SUCCESS) && (i < 100)); 2150 2151 return (ret_val); 2152 } 2153 2154 /* 2155 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2156 * @page: page to access 2157 * 2158 * Returns the phy address for the page requested. 2159 */ 2160 static u32 2161 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2162 { 2163 u32 phy_addr = 2; 2164 2165 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2166 phy_addr = 1; 2167 2168 return (phy_addr); 2169 } 2170 2171 /* 2172 * e1000_write_phy_reg_bm - Write BM PHY register 2173 * @hw: pointer to the HW structure 2174 * @offset: register offset to write to 2175 * @data: data to write at register offset 2176 * 2177 * Acquires semaphore, if necessary, then writes the data to PHY register 2178 * at the offset. Release any acquired semaphores before exiting. 2179 */ 2180 s32 2181 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2182 { 2183 s32 ret_val; 2184 u32 page_select = 0; 2185 u32 page = offset >> IGP_PAGE_SHIFT; 2186 u32 page_shift = 0; 2187 2188 DEBUGFUNC("e1000_write_phy_reg_bm"); 2189 2190 /* Page 800 works differently than the rest so it has its own func */ 2191 if (page == BM_WUC_PAGE) { 2192 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2193 offset, &data, FALSE); 2194 goto out; 2195 } 2196 2197 ret_val = e1000_acquire_phy(hw); 2198 if (ret_val) 2199 goto out; 2200 2201 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2202 2203 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2204 /* 2205 * Page select is register 31 for phy address 1 and 22 for 2206 * phy address 2 and 3. Page select is shifted only for 2207 * phy address 1. 2208 */ 2209 if (hw->phy.addr == 1) { 2210 page_shift = IGP_PAGE_SHIFT; 2211 page_select = IGP01E1000_PHY_PAGE_SELECT; 2212 } else { 2213 page_shift = 0; 2214 page_select = BM_PHY_PAGE_SELECT; 2215 } 2216 2217 /* Page is shifted left, PHY expects (page x 32) */ 2218 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2219 (page << page_shift)); 2220 if (ret_val) { 2221 e1000_release_phy(hw); 2222 goto out; 2223 } 2224 } 2225 2226 ret_val = e1000_write_phy_reg_mdic(hw, 2227 MAX_PHY_REG_ADDRESS & offset, 2228 data); 2229 2230 e1000_release_phy(hw); 2231 2232 out: 2233 return (ret_val); 2234 } 2235 2236 /* 2237 * e1000_read_phy_reg_bm - Read BM PHY register 2238 * @hw: pointer to the HW structure 2239 * @offset: register offset to be read 2240 * @data: pointer to the read data 2241 * 2242 * Acquires semaphore, if necessary, then reads the PHY register at offset 2243 * and storing the retrieved information in data. Release any acquired 2244 * semaphores before exiting. 2245 */ 2246 s32 2247 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2248 { 2249 s32 ret_val; 2250 u32 page_select = 0; 2251 u32 page = offset >> IGP_PAGE_SHIFT; 2252 u32 page_shift = 0; 2253 2254 DEBUGFUNC("e1000_write_phy_reg_bm"); 2255 2256 /* Page 800 works differently than the rest so it has its own func */ 2257 if (page == BM_WUC_PAGE) { 2258 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2259 offset, data, TRUE); 2260 goto out; 2261 } 2262 2263 ret_val = e1000_acquire_phy(hw); 2264 if (ret_val) 2265 goto out; 2266 2267 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2268 2269 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2270 /* 2271 * Page select is register 31 for phy address 1 and 22 for 2272 * phy address 2 and 3. Page select is shifted only for 2273 * phy address 1. 2274 */ 2275 if (hw->phy.addr == 1) { 2276 page_shift = IGP_PAGE_SHIFT; 2277 page_select = IGP01E1000_PHY_PAGE_SELECT; 2278 } else { 2279 page_shift = 0; 2280 page_select = BM_PHY_PAGE_SELECT; 2281 } 2282 2283 /* Page is shifted left, PHY expects (page x 32) */ 2284 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2285 (page << page_shift)); 2286 if (ret_val) { 2287 e1000_release_phy(hw); 2288 goto out; 2289 } 2290 } 2291 2292 ret_val = e1000_read_phy_reg_mdic(hw, 2293 MAX_PHY_REG_ADDRESS & offset, 2294 data); 2295 e1000_release_phy(hw); 2296 2297 out: 2298 return (ret_val); 2299 } 2300 2301 /* 2302 * e1000_read_phy_reg_bm2 - Read BM PHY register 2303 * @hw: pointer to the HW structure 2304 * @offset: register offset to be read 2305 * @data: pointer to the read data 2306 * 2307 * Acquires semaphore, if necessary, then reads the PHY register at offset 2308 * and storing the retrieved information in data. Release any acquired 2309 * semaphores before exiting. 2310 */ 2311 s32 2312 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2313 { 2314 s32 ret_val; 2315 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2316 2317 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2318 2319 /* Page 800 works differently than the rest so it has its own func */ 2320 if (page == BM_WUC_PAGE) { 2321 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2322 offset, data, TRUE); 2323 goto out; 2324 } 2325 2326 ret_val = e1000_acquire_phy(hw); 2327 if (ret_val) 2328 goto out; 2329 2330 hw->phy.addr = 1; 2331 2332 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2333 2334 /* Page is shifted left, PHY expects (page x 32) */ 2335 ret_val = e1000_write_phy_reg_mdic(hw, 2336 BM_PHY_PAGE_SELECT, 2337 page); 2338 2339 if (ret_val) { 2340 e1000_release_phy(hw); 2341 goto out; 2342 } 2343 } 2344 2345 ret_val = e1000_read_phy_reg_mdic(hw, 2346 MAX_PHY_REG_ADDRESS & offset, 2347 data); 2348 e1000_release_phy(hw); 2349 2350 out: 2351 return (ret_val); 2352 } 2353 2354 /* 2355 * e1000_write_phy_reg_bm2 - Write BM PHY register 2356 * @hw: pointer to the HW structure 2357 * @offset: register offset to write to 2358 * @data: data to write at register offset 2359 * 2360 * Acquires semaphore, if necessary, then writes the data to PHY register 2361 * at the offset. Release any acquired semaphores before exiting. 2362 */ 2363 s32 2364 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2365 { 2366 s32 ret_val; 2367 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2368 2369 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2370 2371 /* Page 800 works differently than the rest so it has its own func */ 2372 if (page == BM_WUC_PAGE) { 2373 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2374 offset, &data, FALSE); 2375 goto out; 2376 } 2377 2378 ret_val = e1000_acquire_phy(hw); 2379 if (ret_val) 2380 goto out; 2381 2382 hw->phy.addr = 1; 2383 2384 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2385 /* Page is shifted left, PHY expects (page x 32) */ 2386 ret_val = e1000_write_phy_reg_mdic(hw, 2387 BM_PHY_PAGE_SELECT, 2388 page); 2389 2390 if (ret_val) { 2391 e1000_release_phy(hw); 2392 goto out; 2393 } 2394 } 2395 2396 ret_val = e1000_write_phy_reg_mdic(hw, 2397 MAX_PHY_REG_ADDRESS & offset, 2398 data); 2399 2400 e1000_release_phy(hw); 2401 2402 out: 2403 return (ret_val); 2404 } 2405 2406 /* 2407 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register 2408 * @hw: pointer to the HW structure 2409 * @offset: register offset to be read or written 2410 * @data: pointer to the data to read or write 2411 * @read: determines if operation is read or write 2412 * 2413 * Acquires semaphore, if necessary, then reads the PHY register at offset 2414 * and storing the retrieved information in data. Release any acquired 2415 * semaphores before exiting. Note that procedure to read the wakeup 2416 * registers are different. It works as such: 2417 * 1) Set page 769, register 17, bit 2 = 1 2418 * 2) Set page to 800 for host (801 if we were manageability) 2419 * 3) Write the address using the address opcode (0x11) 2420 * 4) Read or write the data using the data opcode (0x12) 2421 * 5) Restore 769_17.2 to its original value 2422 */ 2423 s32 2424 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, 2425 u32 offset, u16 *data, bool read) 2426 { 2427 s32 ret_val; 2428 u16 reg = ((u16)offset) & PHY_REG_MASK; 2429 u16 phy_reg = 0; 2430 u8 phy_acquired = 1; 2431 2432 DEBUGFUNC("e1000_read_phy_wakeup_reg_bm"); 2433 2434 ret_val = e1000_acquire_phy(hw); 2435 if (ret_val) { 2436 DEBUGOUT("Couldnt acquire PHY\n"); 2437 phy_acquired = 0; 2438 goto out; 2439 } 2440 2441 /* All operations in this function are phy address 1 */ 2442 hw->phy.addr = 1; 2443 2444 /* Set page 769 */ 2445 (void) e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2446 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2447 2448 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2449 if (ret_val) { 2450 DEBUGOUT("Couldnt read PHY page 769\n"); 2451 goto out; 2452 } 2453 2454 /* First clear bit 4 to avoid a power state change */ 2455 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2456 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2457 if (ret_val) { 2458 DEBUGOUT("Couldnt clear PHY page 769 bit 4\n"); 2459 goto out; 2460 } 2461 2462 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2463 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2464 phy_reg | BM_WUC_ENABLE_BIT); 2465 if (ret_val) { 2466 DEBUGOUT("Couldnt write PHY page 769 bit 2\n"); 2467 goto out; 2468 } 2469 2470 /* Select page 800 */ 2471 ret_val = e1000_write_phy_reg_mdic(hw, 2472 IGP01E1000_PHY_PAGE_SELECT, 2473 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2474 2475 /* Write the page 800 offset value using opcode 0x11 */ 2476 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2477 if (ret_val) { 2478 DEBUGOUT("Couldnt write address opcode to page 800\n"); 2479 goto out; 2480 } 2481 2482 if (read) { 2483 /* Read the page 800 value using opcode 0x12 */ 2484 ret_val = e1000_read_phy_reg_mdic(hw, 2485 BM_WUC_DATA_OPCODE, 2486 data); 2487 } else { 2488 /* Read the page 800 value using opcode 0x12 */ 2489 ret_val = e1000_write_phy_reg_mdic(hw, 2490 BM_WUC_DATA_OPCODE, 2491 *data); 2492 } 2493 2494 if (ret_val) { 2495 DEBUGOUT("Couldnt read data value from page 800\n"); 2496 goto out; 2497 } 2498 2499 /* 2500 * Restore 769_17.2 to its original value 2501 * Set page 769 2502 */ 2503 (void) e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2504 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2505 2506 /* Clear 769_17.2 */ 2507 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2508 if (ret_val) { 2509 DEBUGOUT("Couldnt clear PHY page 769 bit 2\n"); 2510 goto out; 2511 } 2512 2513 out: 2514 if (phy_acquired == 1) 2515 e1000_release_phy(hw); 2516 return (ret_val); 2517 } 2518 2519 /* 2520 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2521 * @hw: pointer to the HW structure 2522 * 2523 * In the case of a PHY power down to save power, or to turn off link during a 2524 * driver unload, or wake on lan is not enabled, restore the link to previous 2525 * settings. 2526 */ 2527 void 2528 e1000_power_up_phy_copper(struct e1000_hw *hw) 2529 { 2530 u16 mii_reg = 0; 2531 2532 /* The PHY will retain its settings across a power down/up cycle */ 2533 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &mii_reg); 2534 mii_reg &= ~MII_CR_POWER_DOWN; 2535 (void) e1000_write_phy_reg(hw, PHY_CONTROL, mii_reg); 2536 } 2537 2538 /* 2539 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2540 * @hw: pointer to the HW structure 2541 * 2542 * In the case of a PHY power down to save power, or to turn off link during a 2543 * driver unload, or wake on lan is not enabled, restore the link to previous 2544 * settings. 2545 */ 2546 void 2547 e1000_power_down_phy_copper(struct e1000_hw *hw) 2548 { 2549 u16 mii_reg = 0; 2550 2551 /* The PHY will retain its settings across a power down/up cycle */ 2552 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &mii_reg); 2553 mii_reg |= MII_CR_POWER_DOWN; 2554 (void) e1000_write_phy_reg(hw, PHY_CONTROL, mii_reg); 2555 msec_delay(1); 2556 } 2557