1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.155 scm_100809_154340 */ 30 31 #include "igb_api.h" 32 33 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw); 34 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 35 36 /* Cable length tables */ 37 static const u16 e1000_m88_cable_length_table[] = 38 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 39 40 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 41 (sizeof (e1000_m88_cable_length_table) / \ 42 sizeof (e1000_m88_cable_length_table[0])) 43 44 static const u16 e1000_igp_2_cable_length_table[] = 45 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 46 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 47 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 48 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 49 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 50 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 51 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 52 104, 109, 114, 118, 121, 124}; 53 54 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 55 (sizeof (e1000_igp_2_cable_length_table) / \ 56 sizeof (e1000_igp_2_cable_length_table[0])) 57 58 /* 59 * e1000_init_phy_ops_generic - Initialize PHY function pointers 60 * @hw: pointer to the HW structure 61 * 62 * Setups up the function pointers to no-op functions 63 */ 64 void 65 e1000_init_phy_ops_generic(struct e1000_hw *hw) 66 { 67 struct e1000_phy_info *phy = &hw->phy; 68 DEBUGFUNC("e1000_init_phy_ops_generic"); 69 70 /* Initialize function pointers */ 71 phy->ops.init_params = e1000_null_ops_generic; 72 phy->ops.acquire = e1000_null_ops_generic; 73 phy->ops.check_polarity = e1000_null_ops_generic; 74 phy->ops.check_reset_block = e1000_null_ops_generic; 75 phy->ops.commit = e1000_null_ops_generic; 76 phy->ops.force_speed_duplex = e1000_null_ops_generic; 77 phy->ops.get_cfg_done = e1000_null_ops_generic; 78 phy->ops.get_cable_length = e1000_null_ops_generic; 79 phy->ops.get_info = e1000_null_ops_generic; 80 phy->ops.read_reg = e1000_null_read_reg; 81 phy->ops.read_reg_locked = e1000_null_read_reg; 82 phy->ops.release = e1000_null_phy_generic; 83 phy->ops.reset = e1000_null_ops_generic; 84 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 85 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 86 phy->ops.write_reg = e1000_null_write_reg; 87 phy->ops.write_reg_locked = e1000_null_write_reg; 88 phy->ops.power_up = e1000_null_phy_generic; 89 phy->ops.power_down = e1000_null_phy_generic; 90 } 91 92 /* 93 * e1000_null_read_reg - No-op function, return 0 94 * @hw: pointer to the HW structure 95 */ 96 s32 97 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 98 { 99 DEBUGFUNC("e1000_null_read_reg"); 100 UNREFERENCED_3PARAMETER(hw, offset, data); 101 return (E1000_SUCCESS); 102 } 103 104 /* 105 * e1000_null_phy_generic - No-op function, return void 106 * @hw: pointer to the HW structure 107 */ 108 void 109 e1000_null_phy_generic(struct e1000_hw *hw) 110 { 111 DEBUGFUNC("e1000_null_phy_generic"); 112 UNREFERENCED_1PARAMETER(hw); 113 } 114 115 /* 116 * e1000_null_lplu_state - No-op function, return 0 117 * @hw: pointer to the HW structure 118 */ 119 s32 120 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 121 { 122 DEBUGFUNC("e1000_null_lplu_state"); 123 UNREFERENCED_2PARAMETER(hw, active); 124 return (E1000_SUCCESS); 125 } 126 127 /* 128 * e1000_null_write_reg - No-op function, return 0 129 * @hw: pointer to the HW structure 130 */ 131 s32 132 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 133 { 134 DEBUGFUNC("e1000_null_write_reg"); 135 UNREFERENCED_3PARAMETER(hw, offset, data); 136 return (E1000_SUCCESS); 137 } 138 139 /* 140 * e1000_check_reset_block_generic - Check if PHY reset is blocked 141 * @hw: pointer to the HW structure 142 * 143 * Read the PHY management control register and check whether a PHY reset 144 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 145 * return E1000_BLK_PHY_RESET (12). 146 */ 147 s32 148 e1000_check_reset_block_generic(struct e1000_hw *hw) 149 { 150 u32 manc; 151 152 DEBUGFUNC("e1000_check_reset_block"); 153 154 manc = E1000_READ_REG(hw, E1000_MANC); 155 156 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 157 E1000_BLK_PHY_RESET : E1000_SUCCESS; 158 } 159 160 /* 161 * e1000_get_phy_id - Retrieve the PHY ID and revision 162 * @hw: pointer to the HW structure 163 * 164 * Reads the PHY registers and stores the PHY ID and possibly the PHY 165 * revision in the hardware structure. 166 */ 167 s32 168 e1000_get_phy_id(struct e1000_hw *hw) 169 { 170 struct e1000_phy_info *phy = &hw->phy; 171 s32 ret_val = E1000_SUCCESS; 172 u16 phy_id; 173 174 DEBUGFUNC("e1000_get_phy_id"); 175 176 if (!(phy->ops.read_reg)) 177 goto out; 178 179 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 180 if (ret_val) 181 goto out; 182 183 phy->id = (u32)(phy_id << 16); 184 usec_delay(20); 185 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 186 if (ret_val) 187 goto out; 188 189 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 190 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 191 192 out: 193 return (ret_val); 194 } 195 196 /* 197 * e1000_phy_reset_dsp_generic - Reset PHY DSP 198 * @hw: pointer to the HW structure 199 * 200 * Reset the digital signal processor. 201 */ 202 s32 203 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 204 { 205 s32 ret_val = E1000_SUCCESS; 206 207 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 208 209 if (!(hw->phy.ops.write_reg)) 210 goto out; 211 212 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 213 if (ret_val) 214 goto out; 215 216 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 217 218 out: 219 return (ret_val); 220 } 221 222 /* 223 * e1000_read_phy_reg_mdic - Read MDI control register 224 * @hw: pointer to the HW structure 225 * @offset: register offset to be read 226 * @data: pointer to the read data 227 * 228 * Reads the MDI control register in the PHY at offset and stores the 229 * information read to data. 230 */ 231 s32 232 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 233 { 234 struct e1000_phy_info *phy = &hw->phy; 235 u32 i, mdic = 0; 236 s32 ret_val = E1000_SUCCESS; 237 238 DEBUGFUNC("e1000_read_phy_reg_mdic"); 239 240 /* 241 * Set up Op-code, Phy Address, and register offset in the MDI 242 * Control register. The MAC will take care of interfacing with the 243 * PHY to retrieve the desired data. 244 */ 245 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 246 (phy->addr << E1000_MDIC_PHY_SHIFT) | 247 (E1000_MDIC_OP_READ)); 248 249 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 250 251 /* 252 * Poll the ready bit to see if the MDI read completed 253 * Increasing the time out as testing showed failures with 254 * the lower time out 255 */ 256 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 257 usec_delay(50); 258 mdic = E1000_READ_REG(hw, E1000_MDIC); 259 if (mdic & E1000_MDIC_READY) 260 break; 261 } 262 if (!(mdic & E1000_MDIC_READY)) { 263 DEBUGOUT("MDI Read did not complete\n"); 264 ret_val = -E1000_ERR_PHY; 265 goto out; 266 } 267 if (mdic & E1000_MDIC_ERROR) { 268 DEBUGOUT("MDI Error\n"); 269 ret_val = -E1000_ERR_PHY; 270 goto out; 271 } 272 *data = (u16) mdic; 273 274 out: 275 return (ret_val); 276 } 277 278 /* 279 * e1000_write_phy_reg_mdic - Write MDI control register 280 * @hw: pointer to the HW structure 281 * @offset: register offset to write to 282 * @data: data to write to register at offset 283 * 284 * Writes data to MDI control register in the PHY at offset. 285 */ 286 s32 287 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 288 { 289 struct e1000_phy_info *phy = &hw->phy; 290 u32 i, mdic = 0; 291 s32 ret_val = E1000_SUCCESS; 292 293 DEBUGFUNC("e1000_write_phy_reg_mdic"); 294 295 /* 296 * Set up Op-code, Phy Address, and register offset in the MDI 297 * Control register. The MAC will take care of interfacing with the 298 * PHY to retrieve the desired data. 299 */ 300 mdic = (((u32)data) | 301 (offset << E1000_MDIC_REG_SHIFT) | 302 (phy->addr << E1000_MDIC_PHY_SHIFT) | 303 (E1000_MDIC_OP_WRITE)); 304 305 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 306 307 /* 308 * Poll the ready bit to see if the MDI read completed 309 * Increasing the time out as testing showed failures with 310 * the lower time out 311 */ 312 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 313 usec_delay(50); 314 mdic = E1000_READ_REG(hw, E1000_MDIC); 315 if (mdic & E1000_MDIC_READY) 316 break; 317 } 318 if (!(mdic & E1000_MDIC_READY)) { 319 DEBUGOUT("MDI Write did not complete\n"); 320 ret_val = -E1000_ERR_PHY; 321 goto out; 322 } 323 if (mdic & E1000_MDIC_ERROR) { 324 DEBUGOUT("MDI Error\n"); 325 ret_val = -E1000_ERR_PHY; 326 goto out; 327 } 328 329 out: 330 return (ret_val); 331 } 332 333 /* 334 * e1000_read_phy_reg_i2c - Read PHY register using i2c 335 * @hw: pointer to the HW structure 336 * @offset: register offset to be read 337 * @data: pointer to the read data 338 * 339 * Reads the PHY register at offset using the i2c interface and stores the 340 * retrieved information in data. 341 */ 342 s32 343 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 344 { 345 struct e1000_phy_info *phy = &hw->phy; 346 u32 i, i2ccmd = 0; 347 348 DEBUGFUNC("e1000_read_phy_reg_i2c"); 349 350 /* 351 * Set up Op-code, Phy Address, and register address in the I2CCMD 352 * register. The MAC will take care of interfacing with the 353 * PHY to retrieve the desired data. 354 */ 355 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 356 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 357 (E1000_I2CCMD_OPCODE_READ)); 358 359 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 360 361 /* Poll the ready bit to see if the I2C read completed */ 362 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 363 usec_delay(50); 364 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 365 if (i2ccmd & E1000_I2CCMD_READY) 366 break; 367 } 368 if (!(i2ccmd & E1000_I2CCMD_READY)) { 369 DEBUGOUT("I2CCMD Read did not complete\n"); 370 return (-E1000_ERR_PHY); 371 } 372 if (i2ccmd & E1000_I2CCMD_ERROR) { 373 DEBUGOUT("I2CCMD Error bit set\n"); 374 return (-E1000_ERR_PHY); 375 } 376 377 /* Need to byte-swap the 16-bit value. */ 378 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 379 380 return (E1000_SUCCESS); 381 } 382 383 /* 384 * e1000_write_phy_reg_i2c - Write PHY register using i2c 385 * @hw: pointer to the HW structure 386 * @offset: register offset to write to 387 * @data: data to write at register offset 388 * 389 * Writes the data to PHY register at the offset using the i2c interface. 390 */ 391 s32 392 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 393 { 394 struct e1000_phy_info *phy = &hw->phy; 395 u32 i, i2ccmd = 0; 396 u16 phy_data_swapped; 397 398 DEBUGFUNC("e1000_write_phy_reg_i2c"); 399 400 /* Swap the data bytes for the I2C interface */ 401 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 402 403 /* 404 * Set up Op-code, Phy Address, and register address in the I2CCMD 405 * register. The MAC will take care of interfacing with the 406 * PHY to retrieve the desired data. 407 */ 408 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 409 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 410 E1000_I2CCMD_OPCODE_WRITE | 411 phy_data_swapped); 412 413 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 414 415 /* Poll the ready bit to see if the I2C read completed */ 416 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 417 usec_delay(50); 418 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 419 if (i2ccmd & E1000_I2CCMD_READY) 420 break; 421 } 422 if (!(i2ccmd & E1000_I2CCMD_READY)) { 423 DEBUGOUT("I2CCMD Write did not complete\n"); 424 return (-E1000_ERR_PHY); 425 } 426 if (i2ccmd & E1000_I2CCMD_ERROR) { 427 DEBUGOUT("I2CCMD Error bit set\n"); 428 return (-E1000_ERR_PHY); 429 } 430 431 return (E1000_SUCCESS); 432 } 433 434 /* 435 * e1000_read_phy_reg_m88 - Read m88 PHY register 436 * @hw: pointer to the HW structure 437 * @offset: register offset to be read 438 * @data: pointer to the read data 439 * 440 * Acquires semaphore, if necessary, then reads the PHY register at offset 441 * and storing the retrieved information in data. Release any acquired 442 * semaphores before exiting. 443 */ 444 s32 445 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 446 { 447 s32 ret_val = E1000_SUCCESS; 448 449 DEBUGFUNC("e1000_read_phy_reg_m88"); 450 451 if (!(hw->phy.ops.acquire)) 452 goto out; 453 454 ret_val = hw->phy.ops.acquire(hw); 455 if (ret_val) 456 goto out; 457 458 ret_val = e1000_read_phy_reg_mdic(hw, 459 MAX_PHY_REG_ADDRESS & offset, data); 460 461 hw->phy.ops.release(hw); 462 463 out: 464 return (ret_val); 465 } 466 467 /* 468 * e1000_write_phy_reg_m88 - Write m88 PHY register 469 * @hw: pointer to the HW structure 470 * @offset: register offset to write to 471 * @data: data to write at register offset 472 * 473 * Acquires semaphore, if necessary, then writes the data to PHY register 474 * at the offset. Release any acquired semaphores before exiting. 475 */ 476 s32 477 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 478 { 479 s32 ret_val = E1000_SUCCESS; 480 481 DEBUGFUNC("e1000_write_phy_reg_m88"); 482 483 if (!(hw->phy.ops.acquire)) 484 goto out; 485 486 ret_val = hw->phy.ops.acquire(hw); 487 if (ret_val) 488 goto out; 489 490 ret_val = e1000_write_phy_reg_mdic(hw, 491 MAX_PHY_REG_ADDRESS & offset, data); 492 493 hw->phy.ops.release(hw); 494 495 out: 496 return (ret_val); 497 } 498 499 /* 500 * __e1000_read_phy_reg_igp - Read igp PHY register 501 * @hw: pointer to the HW structure 502 * @offset: register offset to be read 503 * @data: pointer to the read data 504 * @locked: semaphore has already been acquired or not 505 * 506 * Acquires semaphore, if necessary, then reads the PHY register at offset 507 * and stores the retrieved information in data. Release any acquired 508 * semaphores before exiting. 509 */ 510 static s32 511 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 512 bool locked) 513 { 514 s32 ret_val = E1000_SUCCESS; 515 516 DEBUGFUNC("__e1000_read_phy_reg_igp"); 517 518 if (!locked) { 519 if (!(hw->phy.ops.acquire)) 520 goto out; 521 522 ret_val = hw->phy.ops.acquire(hw); 523 if (ret_val) 524 goto out; 525 } 526 527 if (offset > MAX_PHY_MULTI_PAGE_REG) { 528 ret_val = e1000_write_phy_reg_mdic(hw, 529 IGP01E1000_PHY_PAGE_SELECT, (u16)offset); 530 if (ret_val) 531 goto release; 532 } 533 534 ret_val = e1000_read_phy_reg_mdic(hw, 535 MAX_PHY_REG_ADDRESS & offset, data); 536 537 release: 538 if (!locked) 539 hw->phy.ops.release(hw); 540 541 out: 542 return (ret_val); 543 } 544 545 /* 546 * e1000_read_phy_reg_igp - Read igp PHY register 547 * @hw: pointer to the HW structure 548 * @offset: register offset to be read 549 * @data: pointer to the read data 550 * 551 * Acquires semaphore then reads the PHY register at offset and stores the 552 * retrieved information in data. 553 * Release the acquired semaphore before exiting. 554 */ 555 s32 556 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 557 { 558 return (__e1000_read_phy_reg_igp(hw, offset, data, false)); 559 } 560 561 /* 562 * e1000_read_phy_reg_igp_locked - Read igp PHY register 563 * @hw: pointer to the HW structure 564 * @offset: register offset to be read 565 * @data: pointer to the read data 566 * 567 * Reads the PHY register at offset and stores the retrieved information 568 * in data. Assumes semaphore already acquired. 569 */ 570 s32 571 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 572 { 573 return (__e1000_read_phy_reg_igp(hw, offset, data, true)); 574 } 575 576 /* 577 * __e1000_write_phy_reg_igp - Write igp PHY register 578 * @hw: pointer to the HW structure 579 * @offset: register offset to write to 580 * @data: data to write at register offset 581 * @locked: semaphore has already been acquired or not 582 * 583 * Acquires semaphore, if necessary, then writes the data to PHY register 584 * at the offset. Release any acquired semaphores before exiting. 585 */ 586 static s32 587 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 588 bool locked) 589 { 590 s32 ret_val = E1000_SUCCESS; 591 592 DEBUGFUNC("__e1000_write_phy_reg_igp"); 593 594 if (!locked) { 595 if (!(hw->phy.ops.acquire)) 596 goto out; 597 598 ret_val = hw->phy.ops.acquire(hw); 599 if (ret_val) 600 goto out; 601 } 602 603 if (offset > MAX_PHY_MULTI_PAGE_REG) { 604 ret_val = e1000_write_phy_reg_mdic(hw, 605 IGP01E1000_PHY_PAGE_SELECT, (u16)offset); 606 if (ret_val) 607 goto release; 608 } 609 610 ret_val = e1000_write_phy_reg_mdic(hw, 611 MAX_PHY_REG_ADDRESS & offset, data); 612 613 release: 614 if (!locked) 615 hw->phy.ops.release(hw); 616 617 out: 618 return (ret_val); 619 } 620 621 /* 622 * e1000_write_phy_reg_igp - Write igp PHY register 623 * @hw: pointer to the HW structure 624 * @offset: register offset to write to 625 * @data: data to write at register offset 626 * 627 * Acquires semaphore then writes the data to PHY register 628 * at the offset. Release any acquired semaphores before exiting. 629 */ 630 s32 631 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 632 { 633 return (__e1000_write_phy_reg_igp(hw, offset, data, false)); 634 } 635 636 /* 637 * e1000_write_phy_reg_igp_locked - Write igp PHY register 638 * @hw: pointer to the HW structure 639 * @offset: register offset to write to 640 * @data: data to write at register offset 641 * 642 * Writes the data to PHY register at the offset. 643 * Assumes semaphore already acquired. 644 */ 645 s32 646 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 647 { 648 return (__e1000_write_phy_reg_igp(hw, offset, data, true)); 649 } 650 651 /* 652 * __e1000_read_kmrn_reg - Read kumeran register 653 * @hw: pointer to the HW structure 654 * @offset: register offset to be read 655 * @data: pointer to the read data 656 * @locked: semaphore has already been acquired or not 657 * 658 * Acquires semaphore, if necessary. Then reads the PHY register at offset 659 * using the kumeran interface. The information retrieved is stored in data. 660 * Release any acquired semaphores before exiting. 661 */ 662 static s32 663 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, bool locked) 664 { 665 u32 kmrnctrlsta; 666 s32 ret_val = E1000_SUCCESS; 667 668 DEBUGFUNC("__e1000_read_kmrn_reg_generic"); 669 670 if (!locked) { 671 if (!(hw->phy.ops.acquire)) 672 goto out; 673 674 ret_val = hw->phy.ops.acquire(hw); 675 if (ret_val) 676 goto out; 677 } 678 679 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 680 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 681 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 682 683 usec_delay(2); 684 685 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 686 *data = (u16)kmrnctrlsta; 687 688 if (!locked) 689 hw->phy.ops.release(hw); 690 691 out: 692 return (ret_val); 693 } 694 695 /* 696 * e1000_read_kmrn_reg_generic - Read kumeran register 697 * @hw: pointer to the HW structure 698 * @offset: register offset to be read 699 * @data: pointer to the read data 700 * 701 * Acquires semaphore then reads the PHY register at offset using the 702 * kumeran interface. The information retrieved is stored in data. 703 * Release the acquired semaphore before exiting. 704 */ 705 s32 706 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 707 { 708 return (__e1000_read_kmrn_reg(hw, offset, data, false)); 709 } 710 711 /* 712 * e1000_read_kmrn_reg_locked - Read kumeran register 713 * @hw: pointer to the HW structure 714 * @offset: register offset to be read 715 * @data: pointer to the read data 716 * 717 * Reads the PHY register at offset using the kumeran interface. The 718 * information retrieved is stored in data. 719 * Assumes semaphore already acquired. 720 */ 721 s32 722 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 723 { 724 return (__e1000_read_kmrn_reg(hw, offset, data, true)); 725 } 726 727 /* 728 * __e1000_write_kmrn_reg - Write kumeran register 729 * @hw: pointer to the HW structure 730 * @offset: register offset to write to 731 * @data: data to write at register offset 732 * @locked: semaphore has already been acquired or not 733 * 734 * Acquires semaphore, if necessary. Then write the data to PHY register 735 * at the offset using the kumeran interface. Release any acquired semaphores 736 * before exiting. 737 */ 738 static s32 739 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, bool locked) 740 { 741 u32 kmrnctrlsta; 742 s32 ret_val = E1000_SUCCESS; 743 744 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 745 746 if (!locked) { 747 if (!(hw->phy.ops.acquire)) 748 goto out; 749 750 ret_val = hw->phy.ops.acquire(hw); 751 if (ret_val) 752 goto out; 753 } 754 755 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 756 E1000_KMRNCTRLSTA_OFFSET) | data; 757 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 758 759 usec_delay(2); 760 761 if (!locked) 762 hw->phy.ops.release(hw); 763 764 out: 765 return (ret_val); 766 } 767 768 /* 769 * e1000_write_kmrn_reg_generic - Write kumeran register 770 * @hw: pointer to the HW structure 771 * @offset: register offset to write to 772 * @data: data to write at register offset 773 * 774 * Acquires semaphore then writes the data to the PHY register at the offset 775 * using the kumeran interface. Release the acquired semaphore before exiting. 776 */ 777 s32 778 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 779 { 780 return (__e1000_write_kmrn_reg(hw, offset, data, false)); 781 } 782 783 /* 784 * e1000_write_kmrn_reg_locked - Write kumeran register 785 * @hw: pointer to the HW structure 786 * @offset: register offset to write to 787 * @data: data to write at register offset 788 * 789 * Write the data to PHY register at the offset using the kumeran interface. 790 * Assumes semaphore already acquired. 791 */ 792 s32 793 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 794 { 795 return (__e1000_write_kmrn_reg(hw, offset, data, true)); 796 } 797 798 /* 799 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 800 * @hw: pointer to the HW structure 801 * 802 * Sets up Carrier-sense on Transmit and downshift values. 803 */ 804 s32 805 e1000_copper_link_setup_82577(struct e1000_hw *hw) 806 { 807 struct e1000_phy_info *phy = &hw->phy; 808 s32 ret_val; 809 u16 phy_data; 810 811 DEBUGFUNC("e1000_copper_link_setup_82577"); 812 813 if (phy->reset_disable) { 814 ret_val = E1000_SUCCESS; 815 goto out; 816 } 817 818 if (phy->type == e1000_phy_82580) { 819 ret_val = hw->phy.ops.reset(hw); 820 if (ret_val) { 821 DEBUGOUT("Error resetting the PHY.\n"); 822 goto out; 823 } 824 } 825 826 /* Enable CRS on TX. This must be set for half-duplex operation. */ 827 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); 828 if (ret_val) 829 goto out; 830 831 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 832 833 /* Enable downshift */ 834 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 835 836 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); 837 if (ret_val) 838 goto out; 839 840 /* Set number of link attempts before downshift */ 841 ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data); 842 if (ret_val) 843 goto out; 844 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK; 845 ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data); 846 847 out: 848 return (ret_val); 849 } 850 851 /* 852 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 853 * @hw: pointer to the HW structure 854 * 855 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 856 * and downshift values are set also. 857 */ 858 s32 859 e1000_copper_link_setup_m88(struct e1000_hw *hw) 860 { 861 struct e1000_phy_info *phy = &hw->phy; 862 s32 ret_val; 863 u16 phy_data; 864 865 DEBUGFUNC("e1000_copper_link_setup_m88"); 866 867 if (phy->reset_disable) { 868 ret_val = E1000_SUCCESS; 869 goto out; 870 } 871 872 /* Enable CRS on TX. This must be set for half-duplex operation. */ 873 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 874 if (ret_val) 875 goto out; 876 877 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 878 879 /* 880 * Options: 881 * MDI/MDI-X = 0 (default) 882 * 0 - Auto for all speeds 883 * 1 - MDI mode 884 * 2 - MDI-X mode 885 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 886 */ 887 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 888 889 switch (phy->mdix) { 890 case 1: 891 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 892 break; 893 case 2: 894 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 895 break; 896 case 3: 897 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 898 break; 899 case 0: 900 default: 901 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 902 break; 903 } 904 905 /* 906 * Options: 907 * disable_polarity_correction = 0 (default) 908 * Automatic Correction for Reversed Cable Polarity 909 * 0 - Disabled 910 * 1 - Enabled 911 */ 912 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 913 if (phy->disable_polarity_correction == 1) 914 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 915 916 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 917 if (ret_val) 918 goto out; 919 920 if (phy->revision < E1000_REVISION_4) { 921 /* 922 * Force TX_CLK in the Extended PHY Specific Control Register 923 * to 25MHz clock. 924 */ 925 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 926 &phy_data); 927 if (ret_val) 928 goto out; 929 930 phy_data |= M88E1000_EPSCR_TX_CLK_25; 931 932 if ((phy->revision == E1000_REVISION_2) && 933 (phy->id == M88E1111_I_PHY_ID)) { 934 /* 82573L PHY - set the downshift counter to 5x. */ 935 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 936 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 937 } else { 938 /* Configure Master and Slave downshift values */ 939 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 940 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 941 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 942 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 943 } 944 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 945 phy_data); 946 if (ret_val) 947 goto out; 948 } 949 950 /* Commit the changes. */ 951 ret_val = phy->ops.commit(hw); 952 if (ret_val) { 953 DEBUGOUT("Error committing the PHY changes\n"); 954 goto out; 955 } 956 957 out: 958 return (ret_val); 959 } 960 961 /* 962 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 963 * @hw: pointer to the HW structure 964 * 965 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 966 * igp PHY's. 967 */ 968 s32 969 e1000_copper_link_setup_igp(struct e1000_hw *hw) 970 { 971 struct e1000_phy_info *phy = &hw->phy; 972 s32 ret_val; 973 u16 data; 974 975 DEBUGFUNC("e1000_copper_link_setup_igp"); 976 977 if (phy->reset_disable) { 978 ret_val = E1000_SUCCESS; 979 goto out; 980 } 981 982 ret_val = hw->phy.ops.reset(hw); 983 if (ret_val) { 984 DEBUGOUT("Error resetting the PHY.\n"); 985 goto out; 986 } 987 988 /* 989 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 990 * timeout issues when LFS is enabled. 991 */ 992 msec_delay(100); 993 994 /* 995 * The NVM settings will configure LPLU in D3 for 996 * non-IGP1 PHYs. 997 */ 998 if (phy->type == e1000_phy_igp) { 999 /* disable lplu d3 during driver init */ 1000 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); 1001 if (ret_val) { 1002 DEBUGOUT("Error Disabling LPLU D3\n"); 1003 goto out; 1004 } 1005 } 1006 1007 /* disable lplu d0 during driver init */ 1008 if (hw->phy.ops.set_d0_lplu_state) { 1009 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 1010 if (ret_val) { 1011 DEBUGOUT("Error Disabling LPLU D0\n"); 1012 goto out; 1013 } 1014 } 1015 /* Configure mdi-mdix settings */ 1016 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1017 if (ret_val) 1018 goto out; 1019 1020 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1021 1022 switch (phy->mdix) { 1023 case 1: 1024 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1025 break; 1026 case 2: 1027 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1028 break; 1029 case 0: 1030 default: 1031 data |= IGP01E1000_PSCR_AUTO_MDIX; 1032 break; 1033 } 1034 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1035 if (ret_val) 1036 goto out; 1037 1038 /* set auto-master slave resolution settings */ 1039 if (hw->mac.autoneg) { 1040 /* 1041 * when autonegotiation advertisement is only 1000Mbps then we 1042 * should disable SmartSpeed and enable Auto MasterSlave 1043 * resolution as hardware default. 1044 */ 1045 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1046 /* Disable SmartSpeed */ 1047 ret_val = phy->ops.read_reg(hw, 1048 IGP01E1000_PHY_PORT_CONFIG, &data); 1049 if (ret_val) 1050 goto out; 1051 1052 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1053 ret_val = phy->ops.write_reg(hw, 1054 IGP01E1000_PHY_PORT_CONFIG, data); 1055 if (ret_val) 1056 goto out; 1057 1058 /* Set auto Master/Slave resolution process */ 1059 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1060 if (ret_val) 1061 goto out; 1062 1063 data &= ~CR_1000T_MS_ENABLE; 1064 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1065 if (ret_val) 1066 goto out; 1067 } 1068 1069 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1070 if (ret_val) 1071 goto out; 1072 1073 /* load defaults for future use */ 1074 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 1075 ((data & CR_1000T_MS_VALUE) ? 1076 e1000_ms_force_master : 1077 e1000_ms_force_slave) : 1078 e1000_ms_auto; 1079 1080 switch (phy->ms_type) { 1081 case e1000_ms_force_master: 1082 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1083 break; 1084 case e1000_ms_force_slave: 1085 data |= CR_1000T_MS_ENABLE; 1086 data &= ~(CR_1000T_MS_VALUE); 1087 break; 1088 case e1000_ms_auto: 1089 data &= ~CR_1000T_MS_ENABLE; 1090 default: 1091 break; 1092 } 1093 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1094 if (ret_val) 1095 goto out; 1096 } 1097 1098 out: 1099 return (ret_val); 1100 } 1101 1102 /* 1103 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1104 * @hw: pointer to the HW structure 1105 * 1106 * Performs initial bounds checking on autoneg advertisement parameter, then 1107 * configure to advertise the full capability. Setup the PHY to autoneg 1108 * and restart the negotiation process between the link partner. If 1109 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1110 */ 1111 static s32 1112 e1000_copper_link_autoneg(struct e1000_hw *hw) 1113 { 1114 struct e1000_phy_info *phy = &hw->phy; 1115 s32 ret_val; 1116 u16 phy_ctrl; 1117 1118 DEBUGFUNC("e1000_copper_link_autoneg"); 1119 1120 /* 1121 * Perform some bounds checking on the autoneg advertisement 1122 * parameter. 1123 */ 1124 phy->autoneg_advertised &= phy->autoneg_mask; 1125 1126 /* 1127 * If autoneg_advertised is zero, we assume it was not defaulted 1128 * by the calling code so we set to advertise full capability. 1129 */ 1130 if (phy->autoneg_advertised == 0) 1131 phy->autoneg_advertised = phy->autoneg_mask; 1132 1133 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1134 ret_val = e1000_phy_setup_autoneg(hw); 1135 if (ret_val) { 1136 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1137 goto out; 1138 } 1139 DEBUGOUT("Restarting Auto-Neg\n"); 1140 1141 /* 1142 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1143 * the Auto Neg Restart bit in the PHY control register. 1144 */ 1145 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1146 if (ret_val) 1147 goto out; 1148 1149 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1150 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1151 if (ret_val) 1152 goto out; 1153 1154 /* 1155 * Does the user want to wait for Auto-Neg to complete here, or 1156 * check at a later time (for example, callback routine). 1157 */ 1158 if (phy->autoneg_wait_to_complete) { 1159 ret_val = hw->mac.ops.wait_autoneg(hw); 1160 if (ret_val) { 1161 DEBUGOUT("Error while waiting for " 1162 "autoneg to complete\n"); 1163 goto out; 1164 } 1165 } 1166 1167 hw->mac.get_link_status = true; 1168 1169 out: 1170 return (ret_val); 1171 } 1172 1173 /* 1174 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1175 * @hw: pointer to the HW structure 1176 * 1177 * Reads the MII auto-neg advertisement register and/or the 1000T control 1178 * register and if the PHY is already setup for auto-negotiation, then 1179 * return successful. Otherwise, setup advertisement and flow control to 1180 * the appropriate values for the wanted auto-negotiation. 1181 */ 1182 s32 1183 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1184 { 1185 struct e1000_phy_info *phy = &hw->phy; 1186 s32 ret_val; 1187 u16 mii_autoneg_adv_reg; 1188 u16 mii_1000t_ctrl_reg = 0; 1189 1190 DEBUGFUNC("e1000_phy_setup_autoneg"); 1191 1192 phy->autoneg_advertised &= phy->autoneg_mask; 1193 1194 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1195 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1196 if (ret_val) 1197 goto out; 1198 1199 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1200 /* Read the MII 1000Base-T Control Register (Address 9). */ 1201 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1202 &mii_1000t_ctrl_reg); 1203 if (ret_val) 1204 goto out; 1205 } 1206 1207 /* 1208 * Need to parse both autoneg_advertised and fc and set up 1209 * the appropriate PHY registers. First we will parse for 1210 * autoneg_advertised software override. Since we can advertise 1211 * a plethora of combinations, we need to check each bit 1212 * individually. 1213 */ 1214 1215 /* 1216 * First we clear all the 10/100 mb speed bits in the Auto-Neg 1217 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1218 * the 1000Base-T Control Register (Address 9). 1219 */ 1220 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1221 NWAY_AR_100TX_HD_CAPS | 1222 NWAY_AR_10T_FD_CAPS | 1223 NWAY_AR_10T_HD_CAPS); 1224 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1225 1226 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1227 1228 /* Do we want to advertise 10 Mb Half Duplex? */ 1229 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1230 DEBUGOUT("Advertise 10mb Half duplex\n"); 1231 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1232 } 1233 1234 /* Do we want to advertise 10 Mb Full Duplex? */ 1235 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1236 DEBUGOUT("Advertise 10mb Full duplex\n"); 1237 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1238 } 1239 1240 /* Do we want to advertise 100 Mb Half Duplex? */ 1241 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1242 DEBUGOUT("Advertise 100mb Half duplex\n"); 1243 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1244 } 1245 1246 /* Do we want to advertise 100 Mb Full Duplex? */ 1247 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1248 DEBUGOUT("Advertise 100mb Full duplex\n"); 1249 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1250 } 1251 1252 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1253 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1254 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1255 1256 /* Do we want to advertise 1000 Mb Full Duplex? */ 1257 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1258 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1259 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1260 } 1261 1262 /* 1263 * Check for a software override of the flow control settings, and 1264 * setup the PHY advertisement registers accordingly. If 1265 * auto-negotiation is enabled, then software will have to set the 1266 * "PAUSE" bits to the correct value in the Auto-Negotiation 1267 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1268 * negotiation. 1269 * 1270 * The possible values of the "fc" parameter are: 1271 * 0: Flow control is completely disabled 1272 * 1: Rx flow control is enabled (we can receive pause frames 1273 * but not send pause frames). 1274 * 2: Tx flow control is enabled (we can send pause frames 1275 * but we do not support receiving pause frames). 1276 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1277 * other: No software override. The flow control configuration 1278 * in the EEPROM is used. 1279 */ 1280 switch (hw->fc.current_mode) { 1281 case e1000_fc_none: 1282 /* 1283 * Flow control (Rx & Tx) is completely disabled by a 1284 * software over-ride. 1285 */ 1286 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1287 break; 1288 case e1000_fc_rx_pause: 1289 /* 1290 * Rx Flow control is enabled, and Tx Flow control is 1291 * disabled, by a software over-ride. 1292 * 1293 * Since there really isn't a way to advertise that we are 1294 * capable of Rx Pause ONLY, we will advertise that we 1295 * support both symmetric and asymmetric Rx PAUSE. Later 1296 * (in e1000_config_fc_after_link_up) we will disable the 1297 * hw's ability to send PAUSE frames. 1298 */ 1299 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1300 break; 1301 case e1000_fc_tx_pause: 1302 /* 1303 * Tx Flow control is enabled, and Rx Flow control is 1304 * disabled, by a software over-ride. 1305 */ 1306 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1307 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1308 break; 1309 case e1000_fc_full: 1310 /* 1311 * Flow control (both Rx and Tx) is enabled by a software 1312 * over-ride. 1313 */ 1314 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1315 break; 1316 default: 1317 DEBUGOUT("Flow control param set incorrectly\n"); 1318 ret_val = -E1000_ERR_CONFIG; 1319 goto out; 1320 } 1321 1322 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1323 if (ret_val) 1324 goto out; 1325 1326 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1327 1328 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1329 ret_val = phy->ops.write_reg(hw, 1330 PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1331 if (ret_val) 1332 goto out; 1333 } 1334 1335 out: 1336 return (ret_val); 1337 } 1338 1339 /* 1340 * e1000_setup_copper_link_generic - Configure copper link settings 1341 * @hw: pointer to the HW structure 1342 * 1343 * Calls the appropriate function to configure the link for auto-neg or forced 1344 * speed and duplex. Then we check for link, once link is established calls 1345 * to configure collision distance and flow control are called. If link is 1346 * not established, we return -E1000_ERR_PHY (-2). 1347 */ 1348 s32 1349 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1350 { 1351 s32 ret_val; 1352 bool link; 1353 1354 DEBUGFUNC("e1000_setup_copper_link_generic"); 1355 1356 if (hw->mac.autoneg) { 1357 /* 1358 * Setup autoneg and flow control advertisement and perform 1359 * autonegotiation. 1360 */ 1361 ret_val = e1000_copper_link_autoneg(hw); 1362 if (ret_val) 1363 goto out; 1364 } else { 1365 /* 1366 * PHY will be set to 10H, 10F, 100H or 100F 1367 * depending on user settings. 1368 */ 1369 DEBUGOUT("Forcing Speed and Duplex\n"); 1370 ret_val = hw->phy.ops.force_speed_duplex(hw); 1371 if (ret_val) { 1372 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1373 goto out; 1374 } 1375 } 1376 1377 /* 1378 * Check link status. Wait up to 100 microseconds for link to become 1379 * valid. 1380 */ 1381 ret_val = e1000_phy_has_link_generic(hw, 1382 COPPER_LINK_UP_LIMIT, 1383 10, 1384 &link); 1385 if (ret_val) 1386 goto out; 1387 1388 if (link) { 1389 DEBUGOUT("Valid link established!!!\n"); 1390 e1000_config_collision_dist_generic(hw); 1391 ret_val = e1000_config_fc_after_link_up_generic(hw); 1392 } else { 1393 DEBUGOUT("Unable to establish link!!!\n"); 1394 } 1395 1396 out: 1397 return (ret_val); 1398 } 1399 1400 /* 1401 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1402 * @hw: pointer to the HW structure 1403 * 1404 * Calls the PHY setup function to force speed and duplex. Clears the 1405 * auto-crossover to force MDI manually. Waits for link and returns 1406 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1407 */ 1408 s32 1409 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1410 { 1411 struct e1000_phy_info *phy = &hw->phy; 1412 s32 ret_val; 1413 u16 phy_data; 1414 bool link; 1415 1416 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1417 1418 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1419 if (ret_val) 1420 goto out; 1421 1422 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1423 1424 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1425 if (ret_val) 1426 goto out; 1427 1428 /* 1429 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1430 * forced whenever speed and duplex are forced. 1431 */ 1432 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1433 if (ret_val) 1434 goto out; 1435 1436 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1437 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1438 1439 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1440 if (ret_val) 1441 goto out; 1442 1443 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1444 1445 usec_delay(1); 1446 1447 if (phy->autoneg_wait_to_complete) { 1448 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1449 1450 ret_val = e1000_phy_has_link_generic(hw, 1451 PHY_FORCE_LIMIT, 1452 100000, 1453 &link); 1454 if (ret_val) 1455 goto out; 1456 1457 if (!link) 1458 DEBUGOUT("Link taking longer than expected.\n"); 1459 1460 /* Try once more */ 1461 ret_val = e1000_phy_has_link_generic(hw, 1462 PHY_FORCE_LIMIT, 1463 100000, 1464 &link); 1465 if (ret_val) 1466 goto out; 1467 } 1468 1469 out: 1470 return (ret_val); 1471 } 1472 1473 /* 1474 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1475 * @hw: pointer to the HW structure 1476 * 1477 * Calls the PHY setup function to force speed and duplex. Clears the 1478 * auto-crossover to force MDI manually. Resets the PHY to commit the 1479 * changes. If time expires while waiting for link up, we reset the DSP. 1480 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1481 * successful completion, else return corresponding error code. 1482 */ 1483 s32 1484 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1485 { 1486 struct e1000_phy_info *phy = &hw->phy; 1487 s32 ret_val; 1488 u16 phy_data; 1489 bool link; 1490 1491 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1492 1493 /* 1494 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1495 * forced whenever speed and duplex are forced. 1496 */ 1497 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1498 if (ret_val) 1499 goto out; 1500 1501 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1502 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1503 if (ret_val) 1504 goto out; 1505 1506 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1507 1508 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1509 if (ret_val) 1510 goto out; 1511 1512 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1513 1514 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1515 if (ret_val) 1516 goto out; 1517 1518 /* Reset the phy to commit changes. */ 1519 ret_val = hw->phy.ops.commit(hw); 1520 if (ret_val) 1521 goto out; 1522 1523 if (phy->autoneg_wait_to_complete) { 1524 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1525 1526 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1527 100000, &link); 1528 if (ret_val) 1529 goto out; 1530 1531 if (!link) { 1532 /* 1533 * We didn't get link. 1534 * Reset the DSP and cross our fingers. 1535 */ 1536 ret_val = phy->ops.write_reg(hw, 1537 M88E1000_PHY_PAGE_SELECT, 1538 0x001d); 1539 if (ret_val) 1540 goto out; 1541 ret_val = e1000_phy_reset_dsp_generic(hw); 1542 if (ret_val) 1543 goto out; 1544 } 1545 1546 /* Try once more */ 1547 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1548 100000, &link); 1549 if (ret_val) 1550 goto out; 1551 } 1552 1553 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1554 if (ret_val) 1555 goto out; 1556 1557 /* 1558 * Resetting the phy means we need to re-force TX_CLK in the 1559 * Extended PHY Specific Control Register to 25MHz clock from 1560 * the reset value of 2.5MHz. 1561 */ 1562 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1563 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1564 if (ret_val) 1565 goto out; 1566 1567 /* 1568 * In addition, we must re-enable CRS on Tx for both half and full 1569 * duplex. 1570 */ 1571 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1572 if (ret_val) 1573 goto out; 1574 1575 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1576 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1577 1578 out: 1579 return (ret_val); 1580 } 1581 1582 /* 1583 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1584 * @hw: pointer to the HW structure 1585 * 1586 * Forces the speed and duplex settings of the PHY. 1587 * This is a function pointer entry point only called by 1588 * PHY setup routines. 1589 */ 1590 s32 1591 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1592 { 1593 struct e1000_phy_info *phy = &hw->phy; 1594 s32 ret_val; 1595 u16 data; 1596 bool link; 1597 1598 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1599 1600 if (phy->type != e1000_phy_ife) { 1601 ret_val = e1000_phy_force_speed_duplex_igp(hw); 1602 goto out; 1603 } 1604 1605 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1606 if (ret_val) 1607 goto out; 1608 1609 e1000_phy_force_speed_duplex_setup(hw, &data); 1610 1611 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1612 if (ret_val) 1613 goto out; 1614 1615 /* Disable MDI-X support for 10/100 */ 1616 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1617 if (ret_val) 1618 goto out; 1619 1620 data &= ~IFE_PMC_AUTO_MDIX; 1621 data &= ~IFE_PMC_FORCE_MDIX; 1622 1623 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1624 if (ret_val) 1625 goto out; 1626 1627 DEBUGOUT1("IFE PMC: %X\n", data); 1628 1629 usec_delay(1); 1630 1631 if (phy->autoneg_wait_to_complete) { 1632 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1633 1634 ret_val = e1000_phy_has_link_generic(hw, 1635 PHY_FORCE_LIMIT, 100000, &link); 1636 if (ret_val) 1637 goto out; 1638 1639 if (!link) 1640 DEBUGOUT("Link taking longer than expected.\n"); 1641 1642 /* Try once more */ 1643 ret_val = e1000_phy_has_link_generic(hw, 1644 PHY_FORCE_LIMIT, 100000, &link); 1645 if (ret_val) 1646 goto out; 1647 } 1648 1649 out: 1650 return (ret_val); 1651 } 1652 /* 1653 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1654 * @hw: pointer to the HW structure 1655 * @phy_ctrl: pointer to current value of PHY_CONTROL 1656 * 1657 * Forces speed and duplex on the PHY by doing the following: disable flow 1658 * control, force speed/duplex on the MAC, disable auto speed detection, 1659 * disable auto-negotiation, configure duplex, configure speed, configure 1660 * the collision distance, write configuration to CTRL register. The 1661 * caller must write to the PHY_CONTROL register for these settings to 1662 * take affect. 1663 */ 1664 void 1665 e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1666 { 1667 struct e1000_mac_info *mac = &hw->mac; 1668 u32 ctrl; 1669 1670 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1671 1672 /* Turn off flow control when forcing speed/duplex */ 1673 hw->fc.current_mode = e1000_fc_none; 1674 1675 /* Force speed/duplex on the mac */ 1676 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1677 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1678 ctrl &= ~E1000_CTRL_SPD_SEL; 1679 1680 /* Disable Auto Speed Detection */ 1681 ctrl &= ~E1000_CTRL_ASDE; 1682 1683 /* Disable autoneg on the phy */ 1684 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1685 1686 /* Forcing Full or Half Duplex? */ 1687 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1688 ctrl &= ~E1000_CTRL_FD; 1689 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1690 DEBUGOUT("Half Duplex\n"); 1691 } else { 1692 ctrl |= E1000_CTRL_FD; 1693 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1694 DEBUGOUT("Full Duplex\n"); 1695 } 1696 1697 /* Forcing 10mb or 100mb? */ 1698 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1699 ctrl |= E1000_CTRL_SPD_100; 1700 *phy_ctrl |= MII_CR_SPEED_100; 1701 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1702 DEBUGOUT("Forcing 100mb\n"); 1703 } else { 1704 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1705 /* LINTED */ 1706 *phy_ctrl |= MII_CR_SPEED_10; 1707 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1708 DEBUGOUT("Forcing 10mb\n"); 1709 } 1710 1711 e1000_config_collision_dist_generic(hw); 1712 1713 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1714 } 1715 1716 /* 1717 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1718 * @hw: pointer to the HW structure 1719 * @active: boolean used to enable/disable lplu 1720 * 1721 * Success returns 0, Failure returns 1 1722 * 1723 * The low power link up (lplu) state is set to the power management level D3 1724 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1725 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1726 * is used during Dx states where the power conservation is most important. 1727 * During driver activity, SmartSpeed should be enabled so performance is 1728 * maintained. 1729 */ 1730 s32 1731 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1732 { 1733 struct e1000_phy_info *phy = &hw->phy; 1734 s32 ret_val = E1000_SUCCESS; 1735 u16 data; 1736 1737 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1738 1739 if (!(hw->phy.ops.read_reg)) 1740 goto out; 1741 1742 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1743 if (ret_val) 1744 goto out; 1745 1746 if (!active) { 1747 data &= ~IGP02E1000_PM_D3_LPLU; 1748 ret_val = phy->ops.write_reg(hw, 1749 IGP02E1000_PHY_POWER_MGMT, 1750 data); 1751 if (ret_val) 1752 goto out; 1753 /* 1754 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1755 * during Dx states where the power conservation is most 1756 * important. During driver activity we should enable 1757 * SmartSpeed, so performance is maintained. 1758 */ 1759 if (phy->smart_speed == e1000_smart_speed_on) { 1760 ret_val = phy->ops.read_reg(hw, 1761 IGP01E1000_PHY_PORT_CONFIG, 1762 &data); 1763 if (ret_val) 1764 goto out; 1765 1766 data |= IGP01E1000_PSCFR_SMART_SPEED; 1767 ret_val = phy->ops.write_reg(hw, 1768 IGP01E1000_PHY_PORT_CONFIG, 1769 data); 1770 if (ret_val) 1771 goto out; 1772 } else if (phy->smart_speed == e1000_smart_speed_off) { 1773 ret_val = phy->ops.read_reg(hw, 1774 IGP01E1000_PHY_PORT_CONFIG, 1775 &data); 1776 if (ret_val) 1777 goto out; 1778 1779 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1780 ret_val = phy->ops.write_reg(hw, 1781 IGP01E1000_PHY_PORT_CONFIG, 1782 data); 1783 if (ret_val) 1784 goto out; 1785 } 1786 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1787 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1788 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1789 data |= IGP02E1000_PM_D3_LPLU; 1790 ret_val = phy->ops.write_reg(hw, 1791 IGP02E1000_PHY_POWER_MGMT, 1792 data); 1793 if (ret_val) 1794 goto out; 1795 1796 /* When LPLU is enabled, we should disable SmartSpeed */ 1797 ret_val = phy->ops.read_reg(hw, 1798 IGP01E1000_PHY_PORT_CONFIG, 1799 &data); 1800 if (ret_val) 1801 goto out; 1802 1803 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1804 ret_val = phy->ops.write_reg(hw, 1805 IGP01E1000_PHY_PORT_CONFIG, 1806 data); 1807 } 1808 1809 out: 1810 return (ret_val); 1811 } 1812 1813 /* 1814 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1815 * @hw: pointer to the HW structure 1816 * 1817 * Success returns 0, Failure returns 1 1818 * 1819 * A downshift is detected by querying the PHY link health. 1820 */ 1821 s32 1822 e1000_check_downshift_generic(struct e1000_hw *hw) 1823 { 1824 struct e1000_phy_info *phy = &hw->phy; 1825 s32 ret_val; 1826 u16 phy_data, offset, mask; 1827 1828 DEBUGFUNC("e1000_check_downshift_generic"); 1829 1830 switch (phy->type) { 1831 case e1000_phy_m88: 1832 case e1000_phy_gg82563: 1833 offset = M88E1000_PHY_SPEC_STATUS; 1834 mask = M88E1000_PSSR_DOWNSHIFT; 1835 break; 1836 case e1000_phy_igp_2: 1837 case e1000_phy_igp: 1838 case e1000_phy_igp_3: 1839 offset = IGP01E1000_PHY_LINK_HEALTH; 1840 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1841 break; 1842 default: 1843 /* speed downshift not supported */ 1844 phy->speed_downgraded = false; 1845 ret_val = E1000_SUCCESS; 1846 goto out; 1847 } 1848 1849 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1850 1851 if (!ret_val) 1852 phy->speed_downgraded = (phy_data & mask) ? true : false; 1853 1854 out: 1855 return (ret_val); 1856 } 1857 1858 /* 1859 * e1000_check_polarity_m88 - Checks the polarity. 1860 * @hw: pointer to the HW structure 1861 * 1862 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1863 * 1864 * Polarity is determined based on the PHY specific status register. 1865 */ 1866 s32 1867 e1000_check_polarity_m88(struct e1000_hw *hw) 1868 { 1869 struct e1000_phy_info *phy = &hw->phy; 1870 s32 ret_val; 1871 u16 data; 1872 1873 DEBUGFUNC("e1000_check_polarity_m88"); 1874 1875 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1876 1877 if (!ret_val) 1878 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1879 ? e1000_rev_polarity_reversed 1880 : e1000_rev_polarity_normal; 1881 1882 return (ret_val); 1883 } 1884 1885 /* 1886 * e1000_check_polarity_igp - Checks the polarity. 1887 * @hw: pointer to the HW structure 1888 * 1889 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1890 * 1891 * Polarity is determined based on the PHY port status register, and the 1892 * current speed (since there is no polarity at 100Mbps). 1893 */ 1894 s32 1895 e1000_check_polarity_igp(struct e1000_hw *hw) 1896 { 1897 struct e1000_phy_info *phy = &hw->phy; 1898 s32 ret_val; 1899 u16 data, offset, mask; 1900 1901 DEBUGFUNC("e1000_check_polarity_igp"); 1902 1903 /* 1904 * Polarity is determined based on the speed of 1905 * our connection. 1906 */ 1907 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1908 if (ret_val) 1909 goto out; 1910 1911 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1912 IGP01E1000_PSSR_SPEED_1000MBPS) { 1913 offset = IGP01E1000_PHY_PCS_INIT_REG; 1914 mask = IGP01E1000_PHY_POLARITY_MASK; 1915 } else { 1916 /* 1917 * This really only applies to 10Mbps since 1918 * there is no polarity for 100Mbps (always 0). 1919 */ 1920 offset = IGP01E1000_PHY_PORT_STATUS; 1921 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1922 } 1923 1924 ret_val = phy->ops.read_reg(hw, offset, &data); 1925 1926 if (!ret_val) 1927 phy->cable_polarity = (data & mask) 1928 ? e1000_rev_polarity_reversed 1929 : e1000_rev_polarity_normal; 1930 1931 out: 1932 return (ret_val); 1933 } 1934 1935 /* 1936 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1937 * @hw: pointer to the HW structure 1938 * 1939 * Polarity is determined on the polarity reversal feature being enabled. 1940 */ 1941 s32 1942 e1000_check_polarity_ife(struct e1000_hw *hw) 1943 { 1944 struct e1000_phy_info *phy = &hw->phy; 1945 s32 ret_val; 1946 u16 phy_data, offset, mask; 1947 1948 DEBUGFUNC("e1000_check_polarity_ife"); 1949 1950 /* 1951 * Polarity is determined based on the reversal feature being enabled. 1952 */ 1953 if (phy->polarity_correction) { 1954 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1955 mask = IFE_PESC_POLARITY_REVERSED; 1956 } else { 1957 offset = IFE_PHY_SPECIAL_CONTROL; 1958 mask = IFE_PSC_FORCE_POLARITY; 1959 } 1960 1961 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1962 1963 if (!ret_val) 1964 phy->cable_polarity = (phy_data & mask) 1965 ? e1000_rev_polarity_reversed 1966 : e1000_rev_polarity_normal; 1967 1968 return (ret_val); 1969 } 1970 /* 1971 * e1000_wait_autoneg_generic - Wait for auto-neg completion 1972 * @hw: pointer to the HW structure 1973 * 1974 * Waits for auto-negotiation to complete or for the auto-negotiation time 1975 * limit to expire, which ever happens first. 1976 */ 1977 s32 1978 e1000_wait_autoneg_generic(struct e1000_hw *hw) 1979 { 1980 s32 ret_val = E1000_SUCCESS; 1981 u16 i, phy_status; 1982 1983 DEBUGFUNC("e1000_wait_autoneg_generic"); 1984 1985 if (!(hw->phy.ops.read_reg)) 1986 return (E1000_SUCCESS); 1987 1988 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1989 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1990 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1991 if (ret_val) 1992 break; 1993 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1994 if (ret_val) 1995 break; 1996 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1997 break; 1998 msec_delay(100); 1999 } 2000 2001 /* 2002 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2003 * has completed. 2004 */ 2005 return (ret_val); 2006 } 2007 2008 /* 2009 * e1000_phy_has_link_generic - Polls PHY for link 2010 * @hw: pointer to the HW structure 2011 * @iterations: number of times to poll for link 2012 * @usec_interval: delay between polling attempts 2013 * @success: pointer to whether polling was successful or not 2014 * 2015 * Polls the PHY status register for link, 'iterations' number of times. 2016 */ 2017 s32 2018 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2019 u32 usec_interval, bool *success) 2020 { 2021 s32 ret_val = E1000_SUCCESS; 2022 u16 i, phy_status; 2023 2024 DEBUGFUNC("e1000_phy_has_link_generic"); 2025 2026 if (!(hw->phy.ops.read_reg)) 2027 return (E1000_SUCCESS); 2028 2029 for (i = 0; i < iterations; i++) { 2030 /* 2031 * Some PHYs require the PHY_STATUS register to be read 2032 * twice due to the link bit being sticky. No harm doing 2033 * it across the board. 2034 */ 2035 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2036 if (ret_val) { 2037 /* 2038 * If the first read fails, another entity may have 2039 * ownership of the resources, wait and try again to 2040 * see if they have relinquished the resources yet. 2041 */ 2042 usec_delay(usec_interval); 2043 } 2044 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2045 if (ret_val) 2046 break; 2047 if (phy_status & MII_SR_LINK_STATUS) 2048 break; 2049 if (usec_interval >= 1000) 2050 msec_delay_irq(usec_interval/1000); 2051 else 2052 usec_delay(usec_interval); 2053 } 2054 2055 *success = (i < iterations) ? true : false; 2056 2057 return (ret_val); 2058 } 2059 2060 /* 2061 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2062 * @hw: pointer to the HW structure 2063 * 2064 * Reads the PHY specific status register to retrieve the cable length 2065 * information. The cable length is determined by averaging the minimum and 2066 * maximum values to get the "average" cable length. The m88 PHY has four 2067 * possible cable length values, which are: 2068 * Register Value Cable Length 2069 * 0 < 50 meters 2070 * 1 50 - 80 meters 2071 * 2 80 - 110 meters 2072 * 3 110 - 140 meters 2073 * 4 > 140 meters 2074 */ 2075 s32 2076 e1000_get_cable_length_m88(struct e1000_hw *hw) 2077 { 2078 struct e1000_phy_info *phy = &hw->phy; 2079 s32 ret_val; 2080 u16 phy_data, index; 2081 2082 DEBUGFUNC("e1000_get_cable_length_m88"); 2083 2084 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2085 if (ret_val) 2086 goto out; 2087 2088 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2089 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2090 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 2091 ret_val = -E1000_ERR_PHY; 2092 goto out; 2093 } 2094 2095 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2096 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2097 2098 phy->cable_length = (phy->min_cable_length + 2099 phy->max_cable_length) / 2; 2100 2101 out: 2102 return (ret_val); 2103 } 2104 2105 /* 2106 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2107 * @hw: pointer to the HW structure 2108 * 2109 * The automatic gain control (agc) normalizes the amplitude of the 2110 * received signal, adjusting for the attenuation produced by the 2111 * cable. By reading the AGC registers, which represent the 2112 * combination of coarse and fine gain value, the value can be put 2113 * into a lookup table to obtain the approximate cable length 2114 * for each channel. 2115 */ 2116 s32 2117 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2118 { 2119 struct e1000_phy_info *phy = &hw->phy; 2120 s32 ret_val = E1000_SUCCESS; 2121 u16 phy_data, i, agc_value = 0; 2122 u16 cur_agc_index, max_agc_index = 0; 2123 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2124 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 2125 {IGP02E1000_PHY_AGC_A, 2126 IGP02E1000_PHY_AGC_B, 2127 IGP02E1000_PHY_AGC_C, 2128 IGP02E1000_PHY_AGC_D}; 2129 2130 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2131 2132 /* Read the AGC registers for all channels */ 2133 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2134 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2135 if (ret_val) 2136 goto out; 2137 2138 /* 2139 * Getting bits 15:9, which represent the combination of 2140 * coarse and fine gain values. The result is a number 2141 * that can be put into the lookup table to obtain the 2142 * approximate cable length. 2143 */ 2144 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2145 IGP02E1000_AGC_LENGTH_MASK; 2146 2147 /* Array index bound check. */ 2148 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2149 (cur_agc_index == 0)) { 2150 ret_val = -E1000_ERR_PHY; 2151 goto out; 2152 } 2153 2154 /* Remove min & max AGC values from calculation. */ 2155 if (e1000_igp_2_cable_length_table[min_agc_index] > 2156 e1000_igp_2_cable_length_table[cur_agc_index]) 2157 min_agc_index = cur_agc_index; 2158 if (e1000_igp_2_cable_length_table[max_agc_index] < 2159 e1000_igp_2_cable_length_table[cur_agc_index]) 2160 max_agc_index = cur_agc_index; 2161 2162 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2163 } 2164 2165 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2166 e1000_igp_2_cable_length_table[max_agc_index]); 2167 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2168 2169 /* Calculate cable length with the error range of +/- 10 meters. */ 2170 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2171 (agc_value - IGP02E1000_AGC_RANGE) : 0; 2172 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2173 2174 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2175 2176 out: 2177 return (ret_val); 2178 } 2179 2180 /* 2181 * e1000_get_phy_info_m88 - Retrieve PHY information 2182 * @hw: pointer to the HW structure 2183 * 2184 * Valid for only copper links. Read the PHY status register (sticky read) 2185 * to verify that link is up. Read the PHY special control register to 2186 * determine the polarity and 10base-T extended distance. Read the PHY 2187 * special status register to determine MDI/MDIx and current speed. If 2188 * speed is 1000, then determine cable length, local and remote receiver. 2189 */ 2190 s32 2191 e1000_get_phy_info_m88(struct e1000_hw *hw) 2192 { 2193 struct e1000_phy_info *phy = &hw->phy; 2194 s32 ret_val; 2195 u16 phy_data; 2196 bool link; 2197 2198 DEBUGFUNC("e1000_get_phy_info_m88"); 2199 2200 if (phy->media_type != e1000_media_type_copper) { 2201 DEBUGOUT("Phy info is only valid for copper media\n"); 2202 ret_val = -E1000_ERR_CONFIG; 2203 goto out; 2204 } 2205 2206 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2207 if (ret_val) 2208 goto out; 2209 2210 if (!link) { 2211 DEBUGOUT("Phy info is only valid if link is up\n"); 2212 ret_val = -E1000_ERR_CONFIG; 2213 goto out; 2214 } 2215 2216 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2217 if (ret_val) 2218 goto out; 2219 2220 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 2221 ? true : false; 2222 2223 ret_val = e1000_check_polarity_m88(hw); 2224 if (ret_val) 2225 goto out; 2226 2227 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2228 if (ret_val) 2229 goto out; 2230 2231 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 2232 2233 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2234 ret_val = hw->phy.ops.get_cable_length(hw); 2235 if (ret_val) 2236 goto out; 2237 2238 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2239 if (ret_val) 2240 goto out; 2241 2242 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2243 ? e1000_1000t_rx_status_ok 2244 : e1000_1000t_rx_status_not_ok; 2245 2246 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2247 ? e1000_1000t_rx_status_ok 2248 : e1000_1000t_rx_status_not_ok; 2249 } else { 2250 /* Set values to "undefined" */ 2251 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2252 phy->local_rx = e1000_1000t_rx_status_undefined; 2253 phy->remote_rx = e1000_1000t_rx_status_undefined; 2254 } 2255 2256 out: 2257 return (ret_val); 2258 } 2259 2260 /* 2261 * e1000_get_phy_info_igp - Retrieve igp PHY information 2262 * @hw: pointer to the HW structure 2263 * 2264 * Read PHY status to determine if link is up. If link is up, then 2265 * set/determine 10base-T extended distance and polarity correction. Read 2266 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2267 * determine on the cable length, local and remote receiver. 2268 */ 2269 s32 2270 e1000_get_phy_info_igp(struct e1000_hw *hw) 2271 { 2272 struct e1000_phy_info *phy = &hw->phy; 2273 s32 ret_val; 2274 u16 data; 2275 bool link; 2276 2277 DEBUGFUNC("e1000_get_phy_info_igp"); 2278 2279 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2280 if (ret_val) 2281 goto out; 2282 2283 if (!link) { 2284 DEBUGOUT("Phy info is only valid if link is up\n"); 2285 ret_val = -E1000_ERR_CONFIG; 2286 goto out; 2287 } 2288 2289 phy->polarity_correction = true; 2290 2291 ret_val = e1000_check_polarity_igp(hw); 2292 if (ret_val) 2293 goto out; 2294 2295 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2296 if (ret_val) 2297 goto out; 2298 2299 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 2300 2301 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2302 IGP01E1000_PSSR_SPEED_1000MBPS) { 2303 ret_val = phy->ops.get_cable_length(hw); 2304 if (ret_val) 2305 goto out; 2306 2307 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2308 if (ret_val) 2309 goto out; 2310 2311 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2312 ? e1000_1000t_rx_status_ok 2313 : e1000_1000t_rx_status_not_ok; 2314 2315 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2316 ? e1000_1000t_rx_status_ok 2317 : e1000_1000t_rx_status_not_ok; 2318 } else { 2319 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2320 phy->local_rx = e1000_1000t_rx_status_undefined; 2321 phy->remote_rx = e1000_1000t_rx_status_undefined; 2322 } 2323 2324 out: 2325 return (ret_val); 2326 } 2327 2328 /* 2329 * e1000_phy_sw_reset_generic - PHY software reset 2330 * @hw: pointer to the HW structure 2331 * 2332 * Does a software reset of the PHY by reading the PHY control register and 2333 * setting/write the control register reset bit to the PHY. 2334 */ 2335 s32 2336 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2337 { 2338 s32 ret_val = E1000_SUCCESS; 2339 u16 phy_ctrl; 2340 2341 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2342 2343 if (!(hw->phy.ops.read_reg)) 2344 goto out; 2345 2346 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2347 if (ret_val) 2348 goto out; 2349 2350 phy_ctrl |= MII_CR_RESET; 2351 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2352 if (ret_val) 2353 goto out; 2354 2355 usec_delay(1); 2356 2357 out: 2358 return (ret_val); 2359 } 2360 2361 /* 2362 * e1000_phy_hw_reset_generic - PHY hardware reset 2363 * @hw: pointer to the HW structure 2364 * 2365 * Verify the reset block is not blocking us from resetting. Acquire 2366 * semaphore (if necessary) and read/set/write the device control reset 2367 * bit in the PHY. Wait the appropriate delay time for the device to 2368 * reset and release the semaphore (if necessary). 2369 */ 2370 s32 2371 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2372 { 2373 struct e1000_phy_info *phy = &hw->phy; 2374 s32 ret_val = E1000_SUCCESS; 2375 u32 ctrl; 2376 2377 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2378 2379 ret_val = phy->ops.check_reset_block(hw); 2380 if (ret_val) { 2381 ret_val = E1000_SUCCESS; 2382 goto out; 2383 } 2384 2385 ret_val = phy->ops.acquire(hw); 2386 if (ret_val) 2387 goto out; 2388 2389 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2390 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2391 E1000_WRITE_FLUSH(hw); 2392 2393 usec_delay(phy->reset_delay_us); 2394 2395 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2396 E1000_WRITE_FLUSH(hw); 2397 2398 usec_delay(150); 2399 2400 phy->ops.release(hw); 2401 2402 ret_val = phy->ops.get_cfg_done(hw); 2403 2404 out: 2405 return (ret_val); 2406 } 2407 2408 /* 2409 * e1000_get_cfg_done_generic - Generic configuration done 2410 * @hw: pointer to the HW structure 2411 * 2412 * Generic function to wait 10 milli-seconds for configuration to complete 2413 * and return success. 2414 */ 2415 s32 2416 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2417 { 2418 DEBUGFUNC("e1000_get_cfg_done_generic"); 2419 UNREFERENCED_1PARAMETER(hw); 2420 2421 msec_delay_irq(10); 2422 2423 return (E1000_SUCCESS); 2424 } 2425 2426 /* 2427 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2428 * @hw: pointer to the HW structure 2429 * 2430 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2431 */ 2432 s32 2433 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2434 { 2435 DEBUGOUT("Running IGP 3 PHY init script\n"); 2436 2437 /* PHY init IGP 3 */ 2438 /* Enable rise/fall, 10-mode work in class-A */ 2439 (void) hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2440 /* Remove all caps from Replica path filter */ 2441 (void) hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2442 /* Bias trimming for ADC, AFE and Driver (Default) */ 2443 (void) hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2444 /* Increase Hybrid poly bias */ 2445 (void) hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2446 /* Add 4% to Tx amplitude in Gig mode */ 2447 (void) hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2448 /* Disable trimming (TTT) */ 2449 (void) hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2450 /* Poly DC correction to 94.6% + 2% for all channels */ 2451 (void) hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2452 /* ABS DC correction to 95.9% */ 2453 (void) hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2454 /* BG temp curve trim */ 2455 (void) hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2456 /* Increasing ADC OPAMP stage 1 currents to max */ 2457 (void) hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2458 /* Force 1000 ( required for enabling PHY regs configuration) */ 2459 (void) hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2460 /* Set upd_freq to 6 */ 2461 (void) hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2462 /* Disable NPDFE */ 2463 (void) hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2464 /* Disable adaptive fixed FFE (Default) */ 2465 (void) hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2466 /* Enable FFE hysteresis */ 2467 (void) hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2468 /* Fixed FFE for short cable lengths */ 2469 (void) hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2470 /* Fixed FFE for medium cable lengths */ 2471 (void) hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2472 /* Fixed FFE for long cable lengths */ 2473 (void) hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2474 /* Enable Adaptive Clip Threshold */ 2475 (void) hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2476 /* AHT reset limit to 1 */ 2477 (void) hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2478 /* Set AHT master delay to 127 msec */ 2479 (void) hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2480 /* Set scan bits for AHT */ 2481 (void) hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2482 /* Set AHT Preset bits */ 2483 (void) hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2484 /* Change integ_factor of channel A to 3 */ 2485 (void) hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2486 /* Change prop_factor of channels BCD to 8 */ 2487 (void) hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2488 /* Change cg_icount + enable integbp for channels BCD */ 2489 (void) hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2490 /* 2491 * Change cg_icount + enable integbp + change prop_factor_master 2492 * to 8 for channel A 2493 */ 2494 (void) hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2495 /* Disable AHT in Slave mode on channel A */ 2496 (void) hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2497 /* 2498 * Enable LPLU and disable AN to 1000 in non-D0a states, 2499 * Enable SPD+B2B 2500 */ 2501 (void) hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2502 /* Enable restart AN on an1000_dis change */ 2503 (void) hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2504 /* Enable wh_fifo read clock in 10/100 modes */ 2505 (void) hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2506 /* Restart AN, Speed selection is 1000 */ 2507 (void) hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2508 2509 return (E1000_SUCCESS); 2510 } 2511 2512 /* 2513 * e1000_get_phy_type_from_id - Get PHY type from id 2514 * @phy_id: phy_id read from the phy 2515 * 2516 * Returns the phy type from the id. 2517 */ 2518 enum e1000_phy_type 2519 e1000_get_phy_type_from_id(u32 phy_id) 2520 { 2521 enum e1000_phy_type phy_type = e1000_phy_unknown; 2522 2523 switch (phy_id) { 2524 case M88E1000_I_PHY_ID: 2525 case M88E1000_E_PHY_ID: 2526 case M88E1111_I_PHY_ID: 2527 case M88E1011_I_PHY_ID: 2528 phy_type = e1000_phy_m88; 2529 break; 2530 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2531 phy_type = e1000_phy_igp_2; 2532 break; 2533 case GG82563_E_PHY_ID: 2534 phy_type = e1000_phy_gg82563; 2535 break; 2536 case IGP03E1000_E_PHY_ID: 2537 phy_type = e1000_phy_igp_3; 2538 break; 2539 case IFE_E_PHY_ID: 2540 case IFE_PLUS_E_PHY_ID: 2541 case IFE_C_E_PHY_ID: 2542 phy_type = e1000_phy_ife; 2543 break; 2544 case I82580_I_PHY_ID: 2545 phy_type = e1000_phy_82580; 2546 break; 2547 default: 2548 phy_type = e1000_phy_unknown; 2549 break; 2550 } 2551 return (phy_type); 2552 } 2553 2554 /* 2555 * e1000_determine_phy_address - Determines PHY address. 2556 * @hw: pointer to the HW structure 2557 * 2558 * This uses a trial and error method to loop through possible PHY 2559 * addresses. It tests each by reading the PHY ID registers and 2560 * checking for a match. 2561 */ 2562 s32 2563 e1000_determine_phy_address(struct e1000_hw *hw) 2564 { 2565 s32 ret_val = -E1000_ERR_PHY_TYPE; 2566 u32 phy_addr = 0; 2567 u32 i; 2568 enum e1000_phy_type phy_type = e1000_phy_unknown; 2569 2570 hw->phy.id = phy_type; 2571 2572 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2573 hw->phy.addr = phy_addr; 2574 i = 0; 2575 2576 do { 2577 (void) e1000_get_phy_id(hw); 2578 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2579 2580 /* 2581 * If phy_type is valid, break - we found our 2582 * PHY address 2583 */ 2584 if (phy_type != e1000_phy_unknown) { 2585 ret_val = E1000_SUCCESS; 2586 goto out; 2587 } 2588 msec_delay(1); 2589 i++; 2590 } while (i < 10); 2591 } 2592 2593 out: 2594 return (ret_val); 2595 } 2596 /* 2597 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2598 * @hw: pointer to the HW structure 2599 * 2600 * In the case of a PHY power down to save power, or to turn off link during a 2601 * driver unload, or wake on lan is not enabled, restore the link to previous 2602 * settings. 2603 */ 2604 void 2605 e1000_power_up_phy_copper(struct e1000_hw *hw) 2606 { 2607 u16 mii_reg = 0; 2608 2609 /* The PHY will retain its settings across a power down/up cycle */ 2610 (void) hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2611 mii_reg &= ~MII_CR_POWER_DOWN; 2612 (void) hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2613 } 2614 2615 /* 2616 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2617 * @hw: pointer to the HW structure 2618 * 2619 * In the case of a PHY power down to save power, or to turn off link during a 2620 * driver unload, or wake on lan is not enabled, restore the link to previous 2621 * settings. 2622 */ 2623 void 2624 e1000_power_down_phy_copper(struct e1000_hw *hw) 2625 { 2626 u16 mii_reg = 0; 2627 2628 /* The PHY will retain its settings across a power down/up cycle */ 2629 (void) hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2630 mii_reg |= MII_CR_POWER_DOWN; 2631 (void) hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2632 msec_delay(1); 2633 } 2634 2635 /* 2636 * e1000_check_polarity_82577 - Checks the polarity. 2637 * @hw: pointer to the HW structure 2638 * 2639 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2640 * 2641 * Polarity is determined based on the PHY specific status register. 2642 */ 2643 s32 2644 e1000_check_polarity_82577(struct e1000_hw *hw) 2645 { 2646 struct e1000_phy_info *phy = &hw->phy; 2647 s32 ret_val; 2648 u16 data; 2649 2650 DEBUGFUNC("e1000_check_polarity_82577"); 2651 2652 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 2653 2654 if (!ret_val) 2655 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 2656 ? e1000_rev_polarity_reversed 2657 : e1000_rev_polarity_normal; 2658 2659 return (ret_val); 2660 } 2661 2662 /* 2663 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 2664 * @hw: pointer to the HW structure 2665 * 2666 * Calls the PHY setup function to force speed and duplex. Clears the 2667 * auto-crossover to force MDI manually. Waits for link and returns 2668 * successful if link up is successful, else -E1000_ERR_PHY (-2). 2669 */ 2670 s32 2671 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 2672 { 2673 struct e1000_phy_info *phy = &hw->phy; 2674 s32 ret_val; 2675 u16 phy_data; 2676 bool link; 2677 2678 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 2679 2680 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 2681 if (ret_val) 2682 goto out; 2683 2684 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 2685 2686 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 2687 if (ret_val) 2688 goto out; 2689 2690 /* 2691 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI 2692 * forced whenever speed and duplex are forced. 2693 */ 2694 ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 2695 if (ret_val) 2696 goto out; 2697 2698 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX; 2699 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX; 2700 2701 ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 2702 if (ret_val) 2703 goto out; 2704 2705 DEBUGOUT1("I82577_PHY_CTRL_2: %X\n", phy_data); 2706 2707 usec_delay(1); 2708 2709 if (phy->autoneg_wait_to_complete) { 2710 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 2711 2712 ret_val = e1000_phy_has_link_generic(hw, 2713 PHY_FORCE_LIMIT, 2714 100000, 2715 &link); 2716 if (ret_val) 2717 goto out; 2718 2719 if (!link) 2720 DEBUGOUT("Link taking longer than expected.\n"); 2721 2722 /* Try once more */ 2723 ret_val = e1000_phy_has_link_generic(hw, 2724 PHY_FORCE_LIMIT, 2725 100000, 2726 &link); 2727 if (ret_val) 2728 goto out; 2729 } 2730 2731 out: 2732 return (ret_val); 2733 } 2734 2735 /* 2736 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 2737 * @hw: pointer to the HW structure 2738 * 2739 * Read PHY status to determine if link is up. If link is up, then 2740 * set/determine 10base-T extended distance and polarity correction. Read 2741 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2742 * determine on the cable length, local and remote receiver. 2743 */ 2744 s32 2745 e1000_get_phy_info_82577(struct e1000_hw *hw) 2746 { 2747 struct e1000_phy_info *phy = &hw->phy; 2748 s32 ret_val; 2749 u16 data; 2750 bool link; 2751 2752 DEBUGFUNC("e1000_get_phy_info_82577"); 2753 2754 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2755 if (ret_val) 2756 goto out; 2757 2758 if (!link) { 2759 DEBUGOUT("Phy info is only valid if link is up\n"); 2760 ret_val = -E1000_ERR_CONFIG; 2761 goto out; 2762 } 2763 2764 phy->polarity_correction = true; 2765 2766 ret_val = e1000_check_polarity_82577(hw); 2767 if (ret_val) 2768 goto out; 2769 2770 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 2771 if (ret_val) 2772 goto out; 2773 2774 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; 2775 2776 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 2777 I82577_PHY_STATUS2_SPEED_1000MBPS) { 2778 ret_val = hw->phy.ops.get_cable_length(hw); 2779 if (ret_val) 2780 goto out; 2781 2782 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2783 if (ret_val) 2784 goto out; 2785 2786 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2787 ? e1000_1000t_rx_status_ok 2788 : e1000_1000t_rx_status_not_ok; 2789 2790 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2791 ? e1000_1000t_rx_status_ok 2792 : e1000_1000t_rx_status_not_ok; 2793 } else { 2794 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2795 phy->local_rx = e1000_1000t_rx_status_undefined; 2796 phy->remote_rx = e1000_1000t_rx_status_undefined; 2797 } 2798 2799 out: 2800 return (ret_val); 2801 } 2802 2803 /* 2804 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 2805 * @hw: pointer to the HW structure 2806 * 2807 * Reads the diagnostic status register and verifies result is valid before 2808 * placing it in the phy_cable_length field. 2809 */ 2810 s32 2811 e1000_get_cable_length_82577(struct e1000_hw *hw) 2812 { 2813 struct e1000_phy_info *phy = &hw->phy; 2814 s32 ret_val; 2815 u16 phy_data, length; 2816 2817 DEBUGFUNC("e1000_get_cable_length_82577"); 2818 2819 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 2820 if (ret_val) 2821 goto out; 2822 2823 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 2824 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 2825 2826 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2827 ret_val = -E1000_ERR_PHY; 2828 2829 phy->cable_length = length; 2830 2831 out: 2832 2833 return (ret_val); 2834 } 2835