1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.140 v2-9-8_2009-6-12 */ 30 31 #include "igb_api.h" 32 33 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 34 35 /* Cable length tables */ 36 static const u16 e1000_m88_cable_length_table[] = 37 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 38 39 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 40 (sizeof (e1000_m88_cable_length_table) / \ 41 sizeof (e1000_m88_cable_length_table[0])) 42 43 static const u16 e1000_igp_2_cable_length_table[] = 44 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 45 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 46 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 47 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 48 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 49 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 50 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 51 104, 109, 114, 118, 121, 124}; 52 53 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 54 (sizeof (e1000_igp_2_cable_length_table) / \ 55 sizeof (e1000_igp_2_cable_length_table[0])) 56 57 /* 58 * e1000_init_phy_ops_generic - Initialize PHY function pointers 59 * @hw: pointer to the HW structure 60 * 61 * Setups up the function pointers to no-op functions 62 */ 63 void 64 e1000_init_phy_ops_generic(struct e1000_hw *hw) 65 { 66 struct e1000_phy_info *phy = &hw->phy; 67 DEBUGFUNC("e1000_init_phy_ops_generic"); 68 69 /* Initialize function pointers */ 70 phy->ops.init_params = e1000_null_ops_generic; 71 phy->ops.acquire = e1000_null_ops_generic; 72 phy->ops.check_polarity = e1000_null_ops_generic; 73 phy->ops.check_reset_block = e1000_null_ops_generic; 74 phy->ops.commit = e1000_null_ops_generic; 75 phy->ops.force_speed_duplex = e1000_null_ops_generic; 76 phy->ops.get_cfg_done = e1000_null_ops_generic; 77 phy->ops.get_cable_length = e1000_null_ops_generic; 78 phy->ops.get_info = e1000_null_ops_generic; 79 phy->ops.read_reg = e1000_null_read_reg; 80 phy->ops.release = e1000_null_phy_generic; 81 phy->ops.reset = e1000_null_ops_generic; 82 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 83 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 84 phy->ops.write_reg = e1000_null_write_reg; 85 phy->ops.power_up = e1000_null_phy_generic; 86 phy->ops.power_down = e1000_null_phy_generic; 87 } 88 89 /* 90 * e1000_null_read_reg - No-op function, return 0 91 * @hw: pointer to the HW structure 92 */ 93 s32 94 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 95 { 96 DEBUGFUNC("e1000_null_read_reg"); 97 UNREFERENCED_3PARAMETER(hw, offset, data); 98 return (E1000_SUCCESS); 99 } 100 101 /* 102 * e1000_null_phy_generic - No-op function, return void 103 * @hw: pointer to the HW structure 104 */ 105 void 106 e1000_null_phy_generic(struct e1000_hw *hw) 107 { 108 DEBUGFUNC("e1000_null_phy_generic"); 109 UNREFERENCED_1PARAMETER(hw); 110 } 111 112 /* 113 * e1000_null_lplu_state - No-op function, return 0 114 * @hw: pointer to the HW structure 115 */ 116 s32 117 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 118 { 119 DEBUGFUNC("e1000_null_lplu_state"); 120 UNREFERENCED_2PARAMETER(hw, active); 121 return (E1000_SUCCESS); 122 } 123 124 /* 125 * e1000_null_write_reg - No-op function, return 0 126 * @hw: pointer to the HW structure 127 */ 128 s32 129 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 130 { 131 DEBUGFUNC("e1000_null_write_reg"); 132 UNREFERENCED_3PARAMETER(hw, offset, data); 133 return (E1000_SUCCESS); 134 } 135 136 /* 137 * e1000_check_reset_block_generic - Check if PHY reset is blocked 138 * @hw: pointer to the HW structure 139 * 140 * Read the PHY management control register and check whether a PHY reset 141 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 142 * return E1000_BLK_PHY_RESET (12). 143 */ 144 s32 145 e1000_check_reset_block_generic(struct e1000_hw *hw) 146 { 147 u32 manc; 148 149 DEBUGFUNC("e1000_check_reset_block"); 150 151 manc = E1000_READ_REG(hw, E1000_MANC); 152 153 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 154 E1000_BLK_PHY_RESET : E1000_SUCCESS; 155 } 156 157 /* 158 * e1000_get_phy_id - Retrieve the PHY ID and revision 159 * @hw: pointer to the HW structure 160 * 161 * Reads the PHY registers and stores the PHY ID and possibly the PHY 162 * revision in the hardware structure. 163 */ 164 s32 165 e1000_get_phy_id(struct e1000_hw *hw) 166 { 167 struct e1000_phy_info *phy = &hw->phy; 168 s32 ret_val = E1000_SUCCESS; 169 u16 phy_id; 170 171 DEBUGFUNC("e1000_get_phy_id"); 172 173 if (!(phy->ops.read_reg)) 174 goto out; 175 176 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 177 if (ret_val) 178 goto out; 179 180 phy->id = (u32)(phy_id << 16); 181 usec_delay(20); 182 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 183 if (ret_val) 184 goto out; 185 186 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 187 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 188 189 out: 190 return (ret_val); 191 } 192 193 /* 194 * e1000_phy_reset_dsp_generic - Reset PHY DSP 195 * @hw: pointer to the HW structure 196 * 197 * Reset the digital signal processor. 198 */ 199 s32 200 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 201 { 202 s32 ret_val = E1000_SUCCESS; 203 204 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 205 206 if (!(hw->phy.ops.write_reg)) 207 goto out; 208 209 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 210 if (ret_val) 211 goto out; 212 213 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 214 215 out: 216 return (ret_val); 217 } 218 219 /* 220 * e1000_read_phy_reg_mdic - Read MDI control register 221 * @hw: pointer to the HW structure 222 * @offset: register offset to be read 223 * @data: pointer to the read data 224 * 225 * Reads the MDI control register in the PHY at offset and stores the 226 * information read to data. 227 */ 228 s32 229 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 230 { 231 struct e1000_phy_info *phy = &hw->phy; 232 u32 i, mdic = 0; 233 s32 ret_val = E1000_SUCCESS; 234 235 DEBUGFUNC("e1000_read_phy_reg_mdic"); 236 237 /* 238 * Set up Op-code, Phy Address, and register offset in the MDI 239 * Control register. The MAC will take care of interfacing with the 240 * PHY to retrieve the desired data. 241 */ 242 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 243 (phy->addr << E1000_MDIC_PHY_SHIFT) | 244 (E1000_MDIC_OP_READ)); 245 246 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 247 248 /* 249 * Poll the ready bit to see if the MDI read completed 250 * Increasing the time out as testing showed failures with 251 * the lower time out 252 */ 253 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 254 usec_delay(50); 255 mdic = E1000_READ_REG(hw, E1000_MDIC); 256 if (mdic & E1000_MDIC_READY) 257 break; 258 } 259 if (!(mdic & E1000_MDIC_READY)) { 260 DEBUGOUT("MDI Read did not complete\n"); 261 ret_val = -E1000_ERR_PHY; 262 goto out; 263 } 264 if (mdic & E1000_MDIC_ERROR) { 265 DEBUGOUT("MDI Error\n"); 266 ret_val = -E1000_ERR_PHY; 267 goto out; 268 } 269 *data = (u16) mdic; 270 271 out: 272 return (ret_val); 273 } 274 275 /* 276 * e1000_write_phy_reg_mdic - Write MDI control register 277 * @hw: pointer to the HW structure 278 * @offset: register offset to write to 279 * @data: data to write to register at offset 280 * 281 * Writes data to MDI control register in the PHY at offset. 282 */ 283 s32 284 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 285 { 286 struct e1000_phy_info *phy = &hw->phy; 287 u32 i, mdic = 0; 288 s32 ret_val = E1000_SUCCESS; 289 290 DEBUGFUNC("e1000_write_phy_reg_mdic"); 291 292 /* 293 * Set up Op-code, Phy Address, and register offset in the MDI 294 * Control register. The MAC will take care of interfacing with the 295 * PHY to retrieve the desired data. 296 */ 297 mdic = (((u32)data) | 298 (offset << E1000_MDIC_REG_SHIFT) | 299 (phy->addr << E1000_MDIC_PHY_SHIFT) | 300 (E1000_MDIC_OP_WRITE)); 301 302 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 303 304 /* 305 * Poll the ready bit to see if the MDI read completed 306 * Increasing the time out as testing showed failures with 307 * the lower time out 308 */ 309 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 310 usec_delay(50); 311 mdic = E1000_READ_REG(hw, E1000_MDIC); 312 if (mdic & E1000_MDIC_READY) 313 break; 314 } 315 if (!(mdic & E1000_MDIC_READY)) { 316 DEBUGOUT("MDI Write did not complete\n"); 317 ret_val = -E1000_ERR_PHY; 318 goto out; 319 } 320 if (mdic & E1000_MDIC_ERROR) { 321 DEBUGOUT("MDI Error\n"); 322 ret_val = -E1000_ERR_PHY; 323 goto out; 324 } 325 326 out: 327 return (ret_val); 328 } 329 330 /* 331 * e1000_read_phy_reg_m88 - Read m88 PHY register 332 * @hw: pointer to the HW structure 333 * @offset: register offset to be read 334 * @data: pointer to the read data 335 * 336 * Acquires semaphore, if necessary, then reads the PHY register at offset 337 * and storing the retrieved information in data. Release any acquired 338 * semaphores before exiting. 339 */ 340 s32 341 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 342 { 343 s32 ret_val = E1000_SUCCESS; 344 345 DEBUGFUNC("e1000_read_phy_reg_m88"); 346 347 if (!(hw->phy.ops.acquire)) 348 goto out; 349 350 ret_val = hw->phy.ops.acquire(hw); 351 if (ret_val) 352 goto out; 353 354 ret_val = e1000_read_phy_reg_mdic(hw, 355 MAX_PHY_REG_ADDRESS & offset, data); 356 357 hw->phy.ops.release(hw); 358 359 out: 360 return (ret_val); 361 } 362 363 /* 364 * e1000_write_phy_reg_m88 - Write m88 PHY register 365 * @hw: pointer to the HW structure 366 * @offset: register offset to write to 367 * @data: data to write at register offset 368 * 369 * Acquires semaphore, if necessary, then writes the data to PHY register 370 * at the offset. Release any acquired semaphores before exiting. 371 */ 372 s32 373 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 374 { 375 s32 ret_val = E1000_SUCCESS; 376 377 DEBUGFUNC("e1000_write_phy_reg_m88"); 378 379 if (!(hw->phy.ops.acquire)) 380 goto out; 381 382 ret_val = hw->phy.ops.acquire(hw); 383 if (ret_val) 384 goto out; 385 386 ret_val = e1000_write_phy_reg_mdic(hw, 387 MAX_PHY_REG_ADDRESS & offset, data); 388 389 hw->phy.ops.release(hw); 390 391 out: 392 return (ret_val); 393 } 394 395 /* 396 * e1000_read_phy_reg_igp - Read igp PHY register 397 * @hw: pointer to the HW structure 398 * @offset: register offset to be read 399 * @data: pointer to the read data 400 * 401 * Acquires semaphore, if necessary, then reads the PHY register at offset 402 * and storing the retrieved information in data. Release any acquired 403 * semaphores before exiting. 404 */ 405 s32 406 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 407 { 408 s32 ret_val = E1000_SUCCESS; 409 410 DEBUGFUNC("e1000_read_phy_reg_igp"); 411 412 if (!(hw->phy.ops.acquire)) 413 goto out; 414 415 ret_val = hw->phy.ops.acquire(hw); 416 if (ret_val) 417 goto out; 418 419 if (offset > MAX_PHY_MULTI_PAGE_REG) { 420 ret_val = e1000_write_phy_reg_mdic(hw, 421 IGP01E1000_PHY_PAGE_SELECT, (u16)offset); 422 if (ret_val) { 423 hw->phy.ops.release(hw); 424 goto out; 425 } 426 } 427 428 ret_val = e1000_read_phy_reg_mdic(hw, 429 MAX_PHY_REG_ADDRESS & offset, data); 430 431 hw->phy.ops.release(hw); 432 433 out: 434 return (ret_val); 435 } 436 437 /* 438 * e1000_write_phy_reg_igp - Write igp PHY register 439 * @hw: pointer to the HW structure 440 * @offset: register offset to write to 441 * @data: data to write at register offset 442 * 443 * Acquires semaphore, if necessary, then writes the data to PHY register 444 * at the offset. Release any acquired semaphores before exiting. 445 */ 446 s32 447 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 448 { 449 s32 ret_val = E1000_SUCCESS; 450 451 DEBUGFUNC("e1000_write_phy_reg_igp"); 452 453 if (!(hw->phy.ops.acquire)) 454 goto out; 455 456 ret_val = hw->phy.ops.acquire(hw); 457 if (ret_val) 458 goto out; 459 460 if (offset > MAX_PHY_MULTI_PAGE_REG) { 461 ret_val = e1000_write_phy_reg_mdic(hw, 462 IGP01E1000_PHY_PAGE_SELECT, (u16)offset); 463 if (ret_val) { 464 hw->phy.ops.release(hw); 465 goto out; 466 } 467 } 468 469 ret_val = e1000_write_phy_reg_mdic(hw, 470 MAX_PHY_REG_ADDRESS & offset, data); 471 472 hw->phy.ops.release(hw); 473 474 out: 475 return (ret_val); 476 } 477 478 /* 479 * e1000_read_kmrn_reg_generic - Read kumeran register 480 * @hw: pointer to the HW structure 481 * @offset: register offset to be read 482 * @data: pointer to the read data 483 * 484 * Acquires semaphore, if necessary. Then reads the PHY register at offset 485 * using the kumeran interface. The information retrieved is stored in data. 486 * Release any acquired semaphores before exiting. 487 */ 488 s32 489 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 490 { 491 u32 kmrnctrlsta; 492 s32 ret_val = E1000_SUCCESS; 493 494 DEBUGFUNC("e1000_read_kmrn_reg_generic"); 495 496 if (!(hw->phy.ops.acquire)) 497 goto out; 498 499 ret_val = hw->phy.ops.acquire(hw); 500 if (ret_val) 501 goto out; 502 503 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 504 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 505 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 506 507 usec_delay(2); 508 509 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 510 *data = (u16)kmrnctrlsta; 511 512 hw->phy.ops.release(hw); 513 514 out: 515 return (ret_val); 516 } 517 518 /* 519 * e1000_write_kmrn_reg_generic - Write kumeran register 520 * @hw: pointer to the HW structure 521 * @offset: register offset to write to 522 * @data: data to write at register offset 523 * 524 * Acquires semaphore, if necessary. Then write the data to PHY register 525 * at the offset using the kumeran interface. Release any acquired semaphores 526 * before exiting. 527 */ 528 s32 529 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 530 { 531 u32 kmrnctrlsta; 532 s32 ret_val = E1000_SUCCESS; 533 534 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 535 536 if (!(hw->phy.ops.acquire)) 537 goto out; 538 539 ret_val = hw->phy.ops.acquire(hw); 540 if (ret_val) 541 goto out; 542 543 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 544 E1000_KMRNCTRLSTA_OFFSET) | data; 545 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 546 547 usec_delay(2); 548 hw->phy.ops.release(hw); 549 550 out: 551 return (ret_val); 552 } 553 554 /* 555 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 556 * @hw: pointer to the HW structure 557 * 558 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 559 * and downshift values are set also. 560 */ 561 s32 562 e1000_copper_link_setup_m88(struct e1000_hw *hw) 563 { 564 struct e1000_phy_info *phy = &hw->phy; 565 s32 ret_val; 566 u16 phy_data; 567 568 DEBUGFUNC("e1000_copper_link_setup_m88"); 569 570 if (phy->reset_disable) { 571 ret_val = E1000_SUCCESS; 572 goto out; 573 } 574 575 /* Enable CRS on TX. This must be set for half-duplex operation. */ 576 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 577 if (ret_val) 578 goto out; 579 580 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 581 582 /* 583 * Options: 584 * MDI/MDI-X = 0 (default) 585 * 0 - Auto for all speeds 586 * 1 - MDI mode 587 * 2 - MDI-X mode 588 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 589 */ 590 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 591 592 switch (phy->mdix) { 593 case 1: 594 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 595 break; 596 case 2: 597 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 598 break; 599 case 3: 600 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 601 break; 602 case 0: 603 default: 604 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 605 break; 606 } 607 608 /* 609 * Options: 610 * disable_polarity_correction = 0 (default) 611 * Automatic Correction for Reversed Cable Polarity 612 * 0 - Disabled 613 * 1 - Enabled 614 */ 615 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 616 if (phy->disable_polarity_correction == 1) 617 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 618 619 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 620 if (ret_val) 621 goto out; 622 623 if (phy->revision < E1000_REVISION_4) { 624 /* 625 * Force TX_CLK in the Extended PHY Specific Control Register 626 * to 25MHz clock. 627 */ 628 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 629 &phy_data); 630 if (ret_val) 631 goto out; 632 633 phy_data |= M88E1000_EPSCR_TX_CLK_25; 634 635 if ((phy->revision == E1000_REVISION_2) && 636 (phy->id == M88E1111_I_PHY_ID)) { 637 /* 82573L PHY - set the downshift counter to 5x. */ 638 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 639 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 640 } else { 641 /* Configure Master and Slave downshift values */ 642 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 643 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 644 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 645 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 646 } 647 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 648 phy_data); 649 if (ret_val) 650 goto out; 651 } 652 653 /* Commit the changes. */ 654 ret_val = phy->ops.commit(hw); 655 if (ret_val) { 656 DEBUGOUT("Error committing the PHY changes\n"); 657 goto out; 658 } 659 660 out: 661 return (ret_val); 662 } 663 664 /* 665 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 666 * @hw: pointer to the HW structure 667 * 668 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 669 * igp PHY's. 670 */ 671 s32 672 e1000_copper_link_setup_igp(struct e1000_hw *hw) 673 { 674 struct e1000_phy_info *phy = &hw->phy; 675 s32 ret_val; 676 u16 data; 677 678 DEBUGFUNC("e1000_copper_link_setup_igp"); 679 680 if (phy->reset_disable) { 681 ret_val = E1000_SUCCESS; 682 goto out; 683 } 684 685 ret_val = hw->phy.ops.reset(hw); 686 if (ret_val) { 687 DEBUGOUT("Error resetting the PHY.\n"); 688 goto out; 689 } 690 691 /* 692 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 693 * timeout issues when LFS is enabled. 694 */ 695 msec_delay(100); 696 697 /* 698 * The NVM settings will configure LPLU in D3 for 699 * non-IGP1 PHYs. 700 */ 701 if (phy->type == e1000_phy_igp) { 702 /* disable lplu d3 during driver init */ 703 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); 704 if (ret_val) { 705 DEBUGOUT("Error Disabling LPLU D3\n"); 706 goto out; 707 } 708 } 709 710 /* disable lplu d0 during driver init */ 711 if (hw->phy.ops.set_d0_lplu_state) { 712 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 713 if (ret_val) { 714 DEBUGOUT("Error Disabling LPLU D0\n"); 715 goto out; 716 } 717 } 718 /* Configure mdi-mdix settings */ 719 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 720 if (ret_val) 721 goto out; 722 723 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 724 725 switch (phy->mdix) { 726 case 1: 727 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 728 break; 729 case 2: 730 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 731 break; 732 case 0: 733 default: 734 data |= IGP01E1000_PSCR_AUTO_MDIX; 735 break; 736 } 737 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 738 if (ret_val) 739 goto out; 740 741 /* set auto-master slave resolution settings */ 742 if (hw->mac.autoneg) { 743 /* 744 * when autonegotiation advertisement is only 1000Mbps then we 745 * should disable SmartSpeed and enable Auto MasterSlave 746 * resolution as hardware default. 747 */ 748 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 749 /* Disable SmartSpeed */ 750 ret_val = phy->ops.read_reg(hw, 751 IGP01E1000_PHY_PORT_CONFIG, &data); 752 if (ret_val) 753 goto out; 754 755 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 756 ret_val = phy->ops.write_reg(hw, 757 IGP01E1000_PHY_PORT_CONFIG, data); 758 if (ret_val) 759 goto out; 760 761 /* Set auto Master/Slave resolution process */ 762 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 763 if (ret_val) 764 goto out; 765 766 data &= ~CR_1000T_MS_ENABLE; 767 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 768 if (ret_val) 769 goto out; 770 } 771 772 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 773 if (ret_val) 774 goto out; 775 776 /* load defaults for future use */ 777 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 778 ((data & CR_1000T_MS_VALUE) ? 779 e1000_ms_force_master : 780 e1000_ms_force_slave) : 781 e1000_ms_auto; 782 783 switch (phy->ms_type) { 784 case e1000_ms_force_master: 785 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 786 break; 787 case e1000_ms_force_slave: 788 data |= CR_1000T_MS_ENABLE; 789 data &= ~(CR_1000T_MS_VALUE); 790 break; 791 case e1000_ms_auto: 792 data &= ~CR_1000T_MS_ENABLE; 793 default: 794 break; 795 } 796 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 797 if (ret_val) 798 goto out; 799 } 800 801 out: 802 return (ret_val); 803 } 804 805 /* 806 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 807 * @hw: pointer to the HW structure 808 * 809 * Performs initial bounds checking on autoneg advertisement parameter, then 810 * configure to advertise the full capability. Setup the PHY to autoneg 811 * and restart the negotiation process between the link partner. If 812 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 813 */ 814 s32 815 e1000_copper_link_autoneg(struct e1000_hw *hw) 816 { 817 struct e1000_phy_info *phy = &hw->phy; 818 s32 ret_val; 819 u16 phy_ctrl; 820 821 DEBUGFUNC("e1000_copper_link_autoneg"); 822 823 /* 824 * Perform some bounds checking on the autoneg advertisement 825 * parameter. 826 */ 827 phy->autoneg_advertised &= phy->autoneg_mask; 828 829 /* 830 * If autoneg_advertised is zero, we assume it was not defaulted 831 * by the calling code so we set to advertise full capability. 832 */ 833 if (phy->autoneg_advertised == 0) 834 phy->autoneg_advertised = phy->autoneg_mask; 835 836 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 837 ret_val = e1000_phy_setup_autoneg(hw); 838 if (ret_val) { 839 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 840 goto out; 841 } 842 DEBUGOUT("Restarting Auto-Neg\n"); 843 844 /* 845 * Restart auto-negotiation by setting the Auto Neg Enable bit and 846 * the Auto Neg Restart bit in the PHY control register. 847 */ 848 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 849 if (ret_val) 850 goto out; 851 852 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 853 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 854 if (ret_val) 855 goto out; 856 857 /* 858 * Does the user want to wait for Auto-Neg to complete here, or 859 * check at a later time (for example, callback routine). 860 */ 861 if (phy->autoneg_wait_to_complete) { 862 ret_val = hw->mac.ops.wait_autoneg(hw); 863 if (ret_val) { 864 DEBUGOUT("Error while waiting for " 865 "autoneg to complete\n"); 866 goto out; 867 } 868 } 869 870 hw->mac.get_link_status = true; 871 872 out: 873 return (ret_val); 874 } 875 876 /* 877 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 878 * @hw: pointer to the HW structure 879 * 880 * Reads the MII auto-neg advertisement register and/or the 1000T control 881 * register and if the PHY is already setup for auto-negotiation, then 882 * return successful. Otherwise, setup advertisement and flow control to 883 * the appropriate values for the wanted auto-negotiation. 884 */ 885 s32 886 e1000_phy_setup_autoneg(struct e1000_hw *hw) 887 { 888 struct e1000_phy_info *phy = &hw->phy; 889 s32 ret_val; 890 u16 mii_autoneg_adv_reg; 891 u16 mii_1000t_ctrl_reg = 0; 892 893 DEBUGFUNC("e1000_phy_setup_autoneg"); 894 895 phy->autoneg_advertised &= phy->autoneg_mask; 896 897 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 898 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 899 if (ret_val) 900 goto out; 901 902 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 903 /* Read the MII 1000Base-T Control Register (Address 9). */ 904 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 905 &mii_1000t_ctrl_reg); 906 if (ret_val) 907 goto out; 908 } 909 910 /* 911 * Need to parse both autoneg_advertised and fc and set up 912 * the appropriate PHY registers. First we will parse for 913 * autoneg_advertised software override. Since we can advertise 914 * a plethora of combinations, we need to check each bit 915 * individually. 916 */ 917 918 /* 919 * First we clear all the 10/100 mb speed bits in the Auto-Neg 920 * Advertisement Register (Address 4) and the 1000 mb speed bits in 921 * the 1000Base-T Control Register (Address 9). 922 */ 923 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 924 NWAY_AR_100TX_HD_CAPS | 925 NWAY_AR_10T_FD_CAPS | 926 NWAY_AR_10T_HD_CAPS); 927 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 928 929 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 930 931 /* Do we want to advertise 10 Mb Half Duplex? */ 932 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 933 DEBUGOUT("Advertise 10mb Half duplex\n"); 934 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 935 } 936 937 /* Do we want to advertise 10 Mb Full Duplex? */ 938 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 939 DEBUGOUT("Advertise 10mb Full duplex\n"); 940 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 941 } 942 943 /* Do we want to advertise 100 Mb Half Duplex? */ 944 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 945 DEBUGOUT("Advertise 100mb Half duplex\n"); 946 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 947 } 948 949 /* Do we want to advertise 100 Mb Full Duplex? */ 950 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 951 DEBUGOUT("Advertise 100mb Full duplex\n"); 952 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 953 } 954 955 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 956 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 957 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 958 959 /* Do we want to advertise 1000 Mb Full Duplex? */ 960 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 961 DEBUGOUT("Advertise 1000mb Full duplex\n"); 962 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 963 } 964 965 /* 966 * Check for a software override of the flow control settings, and 967 * setup the PHY advertisement registers accordingly. If 968 * auto-negotiation is enabled, then software will have to set the 969 * "PAUSE" bits to the correct value in the Auto-Negotiation 970 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 971 * negotiation. 972 * 973 * The possible values of the "fc" parameter are: 974 * 0: Flow control is completely disabled 975 * 1: Rx flow control is enabled (we can receive pause frames 976 * but not send pause frames). 977 * 2: Tx flow control is enabled (we can send pause frames 978 * but we do not support receiving pause frames). 979 * 3: Both Rx and Tx flow control (symmetric) are enabled. 980 * other: No software override. The flow control configuration 981 * in the EEPROM is used. 982 */ 983 switch (hw->fc.current_mode) { 984 case e1000_fc_none: 985 /* 986 * Flow control (Rx & Tx) is completely disabled by a 987 * software over-ride. 988 */ 989 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 990 break; 991 case e1000_fc_rx_pause: 992 /* 993 * Rx Flow control is enabled, and Tx Flow control is 994 * disabled, by a software over-ride. 995 * 996 * Since there really isn't a way to advertise that we are 997 * capable of Rx Pause ONLY, we will advertise that we 998 * support both symmetric and asymmetric Rx PAUSE. Later 999 * (in e1000_config_fc_after_link_up) we will disable the 1000 * hw's ability to send PAUSE frames. 1001 */ 1002 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1003 break; 1004 case e1000_fc_tx_pause: 1005 /* 1006 * Tx Flow control is enabled, and Rx Flow control is 1007 * disabled, by a software over-ride. 1008 */ 1009 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1010 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1011 break; 1012 case e1000_fc_full: 1013 /* 1014 * Flow control (both Rx and Tx) is enabled by a software 1015 * over-ride. 1016 */ 1017 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1018 break; 1019 default: 1020 DEBUGOUT("Flow control param set incorrectly\n"); 1021 ret_val = -E1000_ERR_CONFIG; 1022 goto out; 1023 } 1024 1025 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1026 if (ret_val) 1027 goto out; 1028 1029 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1030 1031 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1032 ret_val = phy->ops.write_reg(hw, 1033 PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1034 if (ret_val) 1035 goto out; 1036 } 1037 1038 out: 1039 return (ret_val); 1040 } 1041 1042 /* 1043 * e1000_setup_copper_link_generic - Configure copper link settings 1044 * @hw: pointer to the HW structure 1045 * 1046 * Calls the appropriate function to configure the link for auto-neg or forced 1047 * speed and duplex. Then we check for link, once link is established calls 1048 * to configure collision distance and flow control are called. If link is 1049 * not established, we return -E1000_ERR_PHY (-2). 1050 */ 1051 s32 1052 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1053 { 1054 s32 ret_val; 1055 bool link; 1056 1057 DEBUGFUNC("e1000_setup_copper_link_generic"); 1058 1059 if (hw->mac.autoneg) { 1060 /* 1061 * Setup autoneg and flow control advertisement and perform 1062 * autonegotiation. 1063 */ 1064 ret_val = e1000_copper_link_autoneg(hw); 1065 if (ret_val) 1066 goto out; 1067 } else { 1068 /* 1069 * PHY will be set to 10H, 10F, 100H or 100F 1070 * depending on user settings. 1071 */ 1072 DEBUGOUT("Forcing Speed and Duplex\n"); 1073 ret_val = hw->phy.ops.force_speed_duplex(hw); 1074 if (ret_val) { 1075 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1076 goto out; 1077 } 1078 } 1079 1080 /* 1081 * Check link status. Wait up to 100 microseconds for link to become 1082 * valid. 1083 */ 1084 ret_val = e1000_phy_has_link_generic(hw, 1085 COPPER_LINK_UP_LIMIT, 1086 10, 1087 &link); 1088 if (ret_val) 1089 goto out; 1090 1091 if (link) { 1092 DEBUGOUT("Valid link established!!!\n"); 1093 e1000_config_collision_dist_generic(hw); 1094 ret_val = e1000_config_fc_after_link_up_generic(hw); 1095 } else { 1096 DEBUGOUT("Unable to establish link!!!\n"); 1097 } 1098 1099 out: 1100 return (ret_val); 1101 } 1102 1103 /* 1104 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1105 * @hw: pointer to the HW structure 1106 * 1107 * Calls the PHY setup function to force speed and duplex. Clears the 1108 * auto-crossover to force MDI manually. Waits for link and returns 1109 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1110 */ 1111 s32 1112 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1113 { 1114 struct e1000_phy_info *phy = &hw->phy; 1115 s32 ret_val; 1116 u16 phy_data; 1117 bool link; 1118 1119 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1120 1121 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1122 if (ret_val) 1123 goto out; 1124 1125 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1126 1127 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1128 if (ret_val) 1129 goto out; 1130 1131 /* 1132 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1133 * forced whenever speed and duplex are forced. 1134 */ 1135 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1136 if (ret_val) 1137 goto out; 1138 1139 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1140 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1141 1142 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1143 if (ret_val) 1144 goto out; 1145 1146 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1147 1148 usec_delay(1); 1149 1150 if (phy->autoneg_wait_to_complete) { 1151 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1152 1153 ret_val = e1000_phy_has_link_generic(hw, 1154 PHY_FORCE_LIMIT, 1155 100000, 1156 &link); 1157 if (ret_val) 1158 goto out; 1159 1160 if (!link) 1161 DEBUGOUT("Link taking longer than expected.\n"); 1162 1163 /* Try once more */ 1164 ret_val = e1000_phy_has_link_generic(hw, 1165 PHY_FORCE_LIMIT, 1166 100000, 1167 &link); 1168 if (ret_val) 1169 goto out; 1170 } 1171 1172 out: 1173 return (ret_val); 1174 } 1175 1176 /* 1177 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1178 * @hw: pointer to the HW structure 1179 * 1180 * Calls the PHY setup function to force speed and duplex. Clears the 1181 * auto-crossover to force MDI manually. Resets the PHY to commit the 1182 * changes. If time expires while waiting for link up, we reset the DSP. 1183 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1184 * successful completion, else return corresponding error code. 1185 */ 1186 s32 1187 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1188 { 1189 struct e1000_phy_info *phy = &hw->phy; 1190 s32 ret_val; 1191 u16 phy_data; 1192 bool link; 1193 1194 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1195 1196 /* 1197 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1198 * forced whenever speed and duplex are forced. 1199 */ 1200 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1201 if (ret_val) 1202 goto out; 1203 1204 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1205 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1206 if (ret_val) 1207 goto out; 1208 1209 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1210 1211 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1212 if (ret_val) 1213 goto out; 1214 1215 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1216 1217 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1218 if (ret_val) 1219 goto out; 1220 1221 /* Reset the phy to commit changes. */ 1222 ret_val = hw->phy.ops.commit(hw); 1223 if (ret_val) 1224 goto out; 1225 1226 if (phy->autoneg_wait_to_complete) { 1227 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1228 1229 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1230 100000, &link); 1231 if (ret_val) 1232 goto out; 1233 1234 if (!link) { 1235 /* 1236 * We didn't get link. 1237 * Reset the DSP and cross our fingers. 1238 */ 1239 ret_val = phy->ops.write_reg(hw, 1240 M88E1000_PHY_PAGE_SELECT, 1241 0x001d); 1242 if (ret_val) 1243 goto out; 1244 ret_val = e1000_phy_reset_dsp_generic(hw); 1245 if (ret_val) 1246 goto out; 1247 } 1248 1249 /* Try once more */ 1250 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1251 100000, &link); 1252 if (ret_val) 1253 goto out; 1254 } 1255 1256 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1257 if (ret_val) 1258 goto out; 1259 1260 /* 1261 * Resetting the phy means we need to re-force TX_CLK in the 1262 * Extended PHY Specific Control Register to 25MHz clock from 1263 * the reset value of 2.5MHz. 1264 */ 1265 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1266 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1267 if (ret_val) 1268 goto out; 1269 1270 /* 1271 * In addition, we must re-enable CRS on Tx for both half and full 1272 * duplex. 1273 */ 1274 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1275 if (ret_val) 1276 goto out; 1277 1278 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1279 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1280 1281 out: 1282 return (ret_val); 1283 } 1284 1285 /* 1286 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1287 * @hw: pointer to the HW structure 1288 * 1289 * Forces the speed and duplex settings of the PHY. 1290 * This is a function pointer entry point only called by 1291 * PHY setup routines. 1292 */ 1293 s32 1294 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1295 { 1296 struct e1000_phy_info *phy = &hw->phy; 1297 s32 ret_val; 1298 u16 data; 1299 bool link; 1300 1301 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1302 1303 if (phy->type != e1000_phy_ife) { 1304 ret_val = e1000_phy_force_speed_duplex_igp(hw); 1305 goto out; 1306 } 1307 1308 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1309 if (ret_val) 1310 goto out; 1311 1312 e1000_phy_force_speed_duplex_setup(hw, &data); 1313 1314 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1315 if (ret_val) 1316 goto out; 1317 1318 /* Disable MDI-X support for 10/100 */ 1319 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1320 if (ret_val) 1321 goto out; 1322 1323 data &= ~IFE_PMC_AUTO_MDIX; 1324 data &= ~IFE_PMC_FORCE_MDIX; 1325 1326 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1327 if (ret_val) 1328 goto out; 1329 1330 DEBUGOUT1("IFE PMC: %X\n", data); 1331 1332 usec_delay(1); 1333 1334 if (phy->autoneg_wait_to_complete) { 1335 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1336 1337 ret_val = e1000_phy_has_link_generic(hw, 1338 PHY_FORCE_LIMIT, 100000, &link); 1339 if (ret_val) 1340 goto out; 1341 1342 if (!link) 1343 DEBUGOUT("Link taking longer than expected.\n"); 1344 1345 /* Try once more */ 1346 ret_val = e1000_phy_has_link_generic(hw, 1347 PHY_FORCE_LIMIT, 100000, &link); 1348 if (ret_val) 1349 goto out; 1350 } 1351 1352 out: 1353 return (ret_val); 1354 } 1355 /* 1356 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1357 * @hw: pointer to the HW structure 1358 * @phy_ctrl: pointer to current value of PHY_CONTROL 1359 * 1360 * Forces speed and duplex on the PHY by doing the following: disable flow 1361 * control, force speed/duplex on the MAC, disable auto speed detection, 1362 * disable auto-negotiation, configure duplex, configure speed, configure 1363 * the collision distance, write configuration to CTRL register. The 1364 * caller must write to the PHY_CONTROL register for these settings to 1365 * take affect. 1366 */ 1367 void 1368 e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1369 { 1370 struct e1000_mac_info *mac = &hw->mac; 1371 u32 ctrl; 1372 1373 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1374 1375 /* Turn off flow control when forcing speed/duplex */ 1376 hw->fc.current_mode = e1000_fc_none; 1377 1378 /* Force speed/duplex on the mac */ 1379 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1380 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1381 ctrl &= ~E1000_CTRL_SPD_SEL; 1382 1383 /* Disable Auto Speed Detection */ 1384 ctrl &= ~E1000_CTRL_ASDE; 1385 1386 /* Disable autoneg on the phy */ 1387 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1388 1389 /* Forcing Full or Half Duplex? */ 1390 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1391 ctrl &= ~E1000_CTRL_FD; 1392 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1393 DEBUGOUT("Half Duplex\n"); 1394 } else { 1395 ctrl |= E1000_CTRL_FD; 1396 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1397 DEBUGOUT("Full Duplex\n"); 1398 } 1399 1400 /* Forcing 10mb or 100mb? */ 1401 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1402 ctrl |= E1000_CTRL_SPD_100; 1403 *phy_ctrl |= MII_CR_SPEED_100; 1404 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1405 DEBUGOUT("Forcing 100mb\n"); 1406 } else { 1407 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1408 /* LINTED */ 1409 *phy_ctrl |= MII_CR_SPEED_10; 1410 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1411 DEBUGOUT("Forcing 10mb\n"); 1412 } 1413 1414 e1000_config_collision_dist_generic(hw); 1415 1416 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1417 } 1418 1419 /* 1420 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1421 * @hw: pointer to the HW structure 1422 * @active: boolean used to enable/disable lplu 1423 * 1424 * Success returns 0, Failure returns 1 1425 * 1426 * The low power link up (lplu) state is set to the power management level D3 1427 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1428 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1429 * is used during Dx states where the power conservation is most important. 1430 * During driver activity, SmartSpeed should be enabled so performance is 1431 * maintained. 1432 */ 1433 s32 1434 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1435 { 1436 struct e1000_phy_info *phy = &hw->phy; 1437 s32 ret_val = E1000_SUCCESS; 1438 u16 data; 1439 1440 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1441 1442 if (!(hw->phy.ops.read_reg)) 1443 goto out; 1444 1445 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1446 if (ret_val) 1447 goto out; 1448 1449 if (!active) { 1450 data &= ~IGP02E1000_PM_D3_LPLU; 1451 ret_val = phy->ops.write_reg(hw, 1452 IGP02E1000_PHY_POWER_MGMT, 1453 data); 1454 if (ret_val) 1455 goto out; 1456 /* 1457 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1458 * during Dx states where the power conservation is most 1459 * important. During driver activity we should enable 1460 * SmartSpeed, so performance is maintained. 1461 */ 1462 if (phy->smart_speed == e1000_smart_speed_on) { 1463 ret_val = phy->ops.read_reg(hw, 1464 IGP01E1000_PHY_PORT_CONFIG, 1465 &data); 1466 if (ret_val) 1467 goto out; 1468 1469 data |= IGP01E1000_PSCFR_SMART_SPEED; 1470 ret_val = phy->ops.write_reg(hw, 1471 IGP01E1000_PHY_PORT_CONFIG, 1472 data); 1473 if (ret_val) 1474 goto out; 1475 } else if (phy->smart_speed == e1000_smart_speed_off) { 1476 ret_val = phy->ops.read_reg(hw, 1477 IGP01E1000_PHY_PORT_CONFIG, 1478 &data); 1479 if (ret_val) 1480 goto out; 1481 1482 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1483 ret_val = phy->ops.write_reg(hw, 1484 IGP01E1000_PHY_PORT_CONFIG, 1485 data); 1486 if (ret_val) 1487 goto out; 1488 } 1489 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1490 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1491 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1492 data |= IGP02E1000_PM_D3_LPLU; 1493 ret_val = phy->ops.write_reg(hw, 1494 IGP02E1000_PHY_POWER_MGMT, 1495 data); 1496 if (ret_val) 1497 goto out; 1498 1499 /* When LPLU is enabled, we should disable SmartSpeed */ 1500 ret_val = phy->ops.read_reg(hw, 1501 IGP01E1000_PHY_PORT_CONFIG, 1502 &data); 1503 if (ret_val) 1504 goto out; 1505 1506 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1507 ret_val = phy->ops.write_reg(hw, 1508 IGP01E1000_PHY_PORT_CONFIG, 1509 data); 1510 } 1511 1512 out: 1513 return (ret_val); 1514 } 1515 1516 /* 1517 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1518 * @hw: pointer to the HW structure 1519 * 1520 * Success returns 0, Failure returns 1 1521 * 1522 * A downshift is detected by querying the PHY link health. 1523 */ 1524 s32 1525 e1000_check_downshift_generic(struct e1000_hw *hw) 1526 { 1527 struct e1000_phy_info *phy = &hw->phy; 1528 s32 ret_val; 1529 u16 phy_data, offset, mask; 1530 1531 DEBUGFUNC("e1000_check_downshift_generic"); 1532 1533 switch (phy->type) { 1534 case e1000_phy_m88: 1535 case e1000_phy_gg82563: 1536 offset = M88E1000_PHY_SPEC_STATUS; 1537 mask = M88E1000_PSSR_DOWNSHIFT; 1538 break; 1539 case e1000_phy_igp_2: 1540 case e1000_phy_igp: 1541 case e1000_phy_igp_3: 1542 offset = IGP01E1000_PHY_LINK_HEALTH; 1543 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1544 break; 1545 default: 1546 /* speed downshift not supported */ 1547 phy->speed_downgraded = false; 1548 ret_val = E1000_SUCCESS; 1549 goto out; 1550 } 1551 1552 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1553 1554 if (!ret_val) 1555 phy->speed_downgraded = (phy_data & mask) ? true : false; 1556 1557 out: 1558 return (ret_val); 1559 } 1560 1561 /* 1562 * e1000_check_polarity_m88 - Checks the polarity. 1563 * @hw: pointer to the HW structure 1564 * 1565 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1566 * 1567 * Polarity is determined based on the PHY specific status register. 1568 */ 1569 s32 1570 e1000_check_polarity_m88(struct e1000_hw *hw) 1571 { 1572 struct e1000_phy_info *phy = &hw->phy; 1573 s32 ret_val; 1574 u16 data; 1575 1576 DEBUGFUNC("e1000_check_polarity_m88"); 1577 1578 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1579 1580 if (!ret_val) 1581 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1582 ? e1000_rev_polarity_reversed 1583 : e1000_rev_polarity_normal; 1584 1585 return (ret_val); 1586 } 1587 1588 /* 1589 * e1000_check_polarity_igp - Checks the polarity. 1590 * @hw: pointer to the HW structure 1591 * 1592 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1593 * 1594 * Polarity is determined based on the PHY port status register, and the 1595 * current speed (since there is no polarity at 100Mbps). 1596 */ 1597 s32 1598 e1000_check_polarity_igp(struct e1000_hw *hw) 1599 { 1600 struct e1000_phy_info *phy = &hw->phy; 1601 s32 ret_val; 1602 u16 data, offset, mask; 1603 1604 DEBUGFUNC("e1000_check_polarity_igp"); 1605 1606 /* 1607 * Polarity is determined based on the speed of 1608 * our connection. 1609 */ 1610 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1611 if (ret_val) 1612 goto out; 1613 1614 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1615 IGP01E1000_PSSR_SPEED_1000MBPS) { 1616 offset = IGP01E1000_PHY_PCS_INIT_REG; 1617 mask = IGP01E1000_PHY_POLARITY_MASK; 1618 } else { 1619 /* 1620 * This really only applies to 10Mbps since 1621 * there is no polarity for 100Mbps (always 0). 1622 */ 1623 offset = IGP01E1000_PHY_PORT_STATUS; 1624 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1625 } 1626 1627 ret_val = phy->ops.read_reg(hw, offset, &data); 1628 1629 if (!ret_val) 1630 phy->cable_polarity = (data & mask) 1631 ? e1000_rev_polarity_reversed 1632 : e1000_rev_polarity_normal; 1633 1634 out: 1635 return (ret_val); 1636 } 1637 1638 /* 1639 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1640 * @hw: pointer to the HW structure 1641 * 1642 * Polarity is determined on the polarity reversal feature being enabled. 1643 */ 1644 s32 1645 e1000_check_polarity_ife(struct e1000_hw *hw) 1646 { 1647 struct e1000_phy_info *phy = &hw->phy; 1648 s32 ret_val; 1649 u16 phy_data, offset, mask; 1650 1651 DEBUGFUNC("e1000_check_polarity_ife"); 1652 1653 /* 1654 * Polarity is determined based on the reversal feature being enabled. 1655 */ 1656 if (phy->polarity_correction) { 1657 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1658 mask = IFE_PESC_POLARITY_REVERSED; 1659 } else { 1660 offset = IFE_PHY_SPECIAL_CONTROL; 1661 mask = IFE_PSC_FORCE_POLARITY; 1662 } 1663 1664 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1665 1666 if (!ret_val) 1667 phy->cable_polarity = (phy_data & mask) 1668 ? e1000_rev_polarity_reversed 1669 : e1000_rev_polarity_normal; 1670 1671 return (ret_val); 1672 } 1673 /* 1674 * e1000_wait_autoneg_generic - Wait for auto-neg completion 1675 * @hw: pointer to the HW structure 1676 * 1677 * Waits for auto-negotiation to complete or for the auto-negotiation time 1678 * limit to expire, which ever happens first. 1679 */ 1680 s32 1681 e1000_wait_autoneg_generic(struct e1000_hw *hw) 1682 { 1683 s32 ret_val = E1000_SUCCESS; 1684 u16 i, phy_status; 1685 1686 DEBUGFUNC("e1000_wait_autoneg_generic"); 1687 1688 if (!(hw->phy.ops.read_reg)) 1689 return (E1000_SUCCESS); 1690 1691 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1692 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1693 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1694 if (ret_val) 1695 break; 1696 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1697 if (ret_val) 1698 break; 1699 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1700 break; 1701 msec_delay(100); 1702 } 1703 1704 /* 1705 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1706 * has completed. 1707 */ 1708 return (ret_val); 1709 } 1710 1711 /* 1712 * e1000_phy_has_link_generic - Polls PHY for link 1713 * @hw: pointer to the HW structure 1714 * @iterations: number of times to poll for link 1715 * @usec_interval: delay between polling attempts 1716 * @success: pointer to whether polling was successful or not 1717 * 1718 * Polls the PHY status register for link, 'iterations' number of times. 1719 */ 1720 s32 1721 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1722 u32 usec_interval, bool *success) 1723 { 1724 s32 ret_val = E1000_SUCCESS; 1725 u16 i, phy_status; 1726 1727 DEBUGFUNC("e1000_phy_has_link_generic"); 1728 1729 if (!(hw->phy.ops.read_reg)) 1730 return (E1000_SUCCESS); 1731 1732 for (i = 0; i < iterations; i++) { 1733 /* 1734 * Some PHYs require the PHY_STATUS register to be read 1735 * twice due to the link bit being sticky. No harm doing 1736 * it across the board. 1737 */ 1738 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1739 if (ret_val) { 1740 /* 1741 * If the first read fails, another entity may have 1742 * ownership of the resources, wait and try again to 1743 * see if they have relinquished the resources yet. 1744 */ 1745 usec_delay(usec_interval); 1746 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 1747 &phy_status); 1748 } 1749 if (ret_val) 1750 break; 1751 if (phy_status & MII_SR_LINK_STATUS) 1752 break; 1753 if (usec_interval >= 1000) 1754 msec_delay_irq(usec_interval/1000); 1755 else 1756 usec_delay(usec_interval); 1757 } 1758 1759 *success = (i < iterations) ? true : false; 1760 1761 return (ret_val); 1762 } 1763 1764 /* 1765 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1766 * @hw: pointer to the HW structure 1767 * 1768 * Reads the PHY specific status register to retrieve the cable length 1769 * information. The cable length is determined by averaging the minimum and 1770 * maximum values to get the "average" cable length. The m88 PHY has four 1771 * possible cable length values, which are: 1772 * Register Value Cable Length 1773 * 0 < 50 meters 1774 * 1 50 - 80 meters 1775 * 2 80 - 110 meters 1776 * 3 110 - 140 meters 1777 * 4 > 140 meters 1778 */ 1779 s32 1780 e1000_get_cable_length_m88(struct e1000_hw *hw) 1781 { 1782 struct e1000_phy_info *phy = &hw->phy; 1783 s32 ret_val; 1784 u16 phy_data, index; 1785 1786 DEBUGFUNC("e1000_get_cable_length_m88"); 1787 1788 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1789 if (ret_val) 1790 goto out; 1791 1792 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1793 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1794 if (index < (M88E1000_CABLE_LENGTH_TABLE_SIZE + 1)) { 1795 ret_val = E1000_ERR_PHY; 1796 goto out; 1797 } 1798 1799 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1800 phy->max_cable_length = e1000_m88_cable_length_table[index+1]; 1801 1802 phy->cable_length = (phy->min_cable_length + 1803 phy->max_cable_length) / 2; 1804 1805 out: 1806 return (ret_val); 1807 } 1808 1809 /* 1810 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1811 * @hw: pointer to the HW structure 1812 * 1813 * The automatic gain control (agc) normalizes the amplitude of the 1814 * received signal, adjusting for the attenuation produced by the 1815 * cable. By reading the AGC registers, which represent the 1816 * combination of coarse and fine gain value, the value can be put 1817 * into a lookup table to obtain the approximate cable length 1818 * for each channel. 1819 */ 1820 s32 1821 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 1822 { 1823 struct e1000_phy_info *phy = &hw->phy; 1824 s32 ret_val = E1000_SUCCESS; 1825 u16 phy_data, i, agc_value = 0; 1826 u16 cur_agc_index, max_agc_index = 0; 1827 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1828 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 1829 {IGP02E1000_PHY_AGC_A, 1830 IGP02E1000_PHY_AGC_B, 1831 IGP02E1000_PHY_AGC_C, 1832 IGP02E1000_PHY_AGC_D}; 1833 1834 DEBUGFUNC("e1000_get_cable_length_igp_2"); 1835 1836 /* Read the AGC registers for all channels */ 1837 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1838 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1839 if (ret_val) 1840 goto out; 1841 1842 /* 1843 * Getting bits 15:9, which represent the combination of 1844 * coarse and fine gain values. The result is a number 1845 * that can be put into the lookup table to obtain the 1846 * approximate cable length. 1847 */ 1848 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1849 IGP02E1000_AGC_LENGTH_MASK; 1850 1851 /* Array index bound check. */ 1852 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1853 (cur_agc_index == 0)) { 1854 ret_val = -E1000_ERR_PHY; 1855 goto out; 1856 } 1857 1858 /* Remove min & max AGC values from calculation. */ 1859 if (e1000_igp_2_cable_length_table[min_agc_index] > 1860 e1000_igp_2_cable_length_table[cur_agc_index]) 1861 min_agc_index = cur_agc_index; 1862 if (e1000_igp_2_cable_length_table[max_agc_index] < 1863 e1000_igp_2_cable_length_table[cur_agc_index]) 1864 max_agc_index = cur_agc_index; 1865 1866 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1867 } 1868 1869 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1870 e1000_igp_2_cable_length_table[max_agc_index]); 1871 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1872 1873 /* Calculate cable length with the error range of +/- 10 meters. */ 1874 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1875 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1876 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1877 1878 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1879 1880 out: 1881 return (ret_val); 1882 } 1883 1884 /* 1885 * e1000_get_phy_info_m88 - Retrieve PHY information 1886 * @hw: pointer to the HW structure 1887 * 1888 * Valid for only copper links. Read the PHY status register (sticky read) 1889 * to verify that link is up. Read the PHY special control register to 1890 * determine the polarity and 10base-T extended distance. Read the PHY 1891 * special status register to determine MDI/MDIx and current speed. If 1892 * speed is 1000, then determine cable length, local and remote receiver. 1893 */ 1894 s32 1895 e1000_get_phy_info_m88(struct e1000_hw *hw) 1896 { 1897 struct e1000_phy_info *phy = &hw->phy; 1898 s32 ret_val; 1899 u16 phy_data; 1900 bool link; 1901 1902 DEBUGFUNC("e1000_get_phy_info_m88"); 1903 1904 if (hw->phy.media_type != e1000_media_type_copper) { 1905 DEBUGOUT("Phy info is only valid for copper media\n"); 1906 ret_val = -E1000_ERR_CONFIG; 1907 goto out; 1908 } 1909 1910 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1911 if (ret_val) 1912 goto out; 1913 1914 if (!link) { 1915 DEBUGOUT("Phy info is only valid if link is up\n"); 1916 ret_val = -E1000_ERR_CONFIG; 1917 goto out; 1918 } 1919 1920 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1921 if (ret_val) 1922 goto out; 1923 1924 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1925 ? true : false; 1926 1927 ret_val = e1000_check_polarity_m88(hw); 1928 if (ret_val) 1929 goto out; 1930 1931 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1932 if (ret_val) 1933 goto out; 1934 1935 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 1936 1937 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1938 ret_val = hw->phy.ops.get_cable_length(hw); 1939 if (ret_val) 1940 goto out; 1941 1942 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 1943 if (ret_val) 1944 goto out; 1945 1946 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1947 ? e1000_1000t_rx_status_ok 1948 : e1000_1000t_rx_status_not_ok; 1949 1950 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1951 ? e1000_1000t_rx_status_ok 1952 : e1000_1000t_rx_status_not_ok; 1953 } else { 1954 /* Set values to "undefined" */ 1955 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1956 phy->local_rx = e1000_1000t_rx_status_undefined; 1957 phy->remote_rx = e1000_1000t_rx_status_undefined; 1958 } 1959 1960 out: 1961 return (ret_val); 1962 } 1963 1964 /* 1965 * e1000_get_phy_info_igp - Retrieve igp PHY information 1966 * @hw: pointer to the HW structure 1967 * 1968 * Read PHY status to determine if link is up. If link is up, then 1969 * set/determine 10base-T extended distance and polarity correction. Read 1970 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1971 * determine on the cable length, local and remote receiver. 1972 */ 1973 s32 1974 e1000_get_phy_info_igp(struct e1000_hw *hw) 1975 { 1976 struct e1000_phy_info *phy = &hw->phy; 1977 s32 ret_val; 1978 u16 data; 1979 bool link; 1980 1981 DEBUGFUNC("e1000_get_phy_info_igp"); 1982 1983 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1984 if (ret_val) 1985 goto out; 1986 1987 if (!link) { 1988 DEBUGOUT("Phy info is only valid if link is up\n"); 1989 ret_val = -E1000_ERR_CONFIG; 1990 goto out; 1991 } 1992 1993 phy->polarity_correction = true; 1994 1995 ret_val = e1000_check_polarity_igp(hw); 1996 if (ret_val) 1997 goto out; 1998 1999 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2000 if (ret_val) 2001 goto out; 2002 2003 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 2004 2005 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2006 IGP01E1000_PSSR_SPEED_1000MBPS) { 2007 ret_val = hw->phy.ops.get_cable_length(hw); 2008 if (ret_val) 2009 goto out; 2010 2011 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2012 if (ret_val) 2013 goto out; 2014 2015 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2016 ? e1000_1000t_rx_status_ok 2017 : e1000_1000t_rx_status_not_ok; 2018 2019 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2020 ? e1000_1000t_rx_status_ok 2021 : e1000_1000t_rx_status_not_ok; 2022 } else { 2023 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2024 phy->local_rx = e1000_1000t_rx_status_undefined; 2025 phy->remote_rx = e1000_1000t_rx_status_undefined; 2026 } 2027 2028 out: 2029 return (ret_val); 2030 } 2031 2032 /* 2033 * e1000_phy_sw_reset_generic - PHY software reset 2034 * @hw: pointer to the HW structure 2035 * 2036 * Does a software reset of the PHY by reading the PHY control register and 2037 * setting/write the control register reset bit to the PHY. 2038 */ 2039 s32 2040 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2041 { 2042 s32 ret_val = E1000_SUCCESS; 2043 u16 phy_ctrl; 2044 2045 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2046 2047 if (!(hw->phy.ops.read_reg)) 2048 goto out; 2049 2050 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2051 if (ret_val) 2052 goto out; 2053 2054 phy_ctrl |= MII_CR_RESET; 2055 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2056 if (ret_val) 2057 goto out; 2058 2059 usec_delay(1); 2060 2061 out: 2062 return (ret_val); 2063 } 2064 2065 /* 2066 * e1000_phy_hw_reset_generic - PHY hardware reset 2067 * @hw: pointer to the HW structure 2068 * 2069 * Verify the reset block is not blocking us from resetting. Acquire 2070 * semaphore (if necessary) and read/set/write the device control reset 2071 * bit in the PHY. Wait the appropriate delay time for the device to 2072 * reset and release the semaphore (if necessary). 2073 */ 2074 s32 2075 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2076 { 2077 struct e1000_phy_info *phy = &hw->phy; 2078 s32 ret_val = E1000_SUCCESS; 2079 u32 ctrl; 2080 2081 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2082 2083 ret_val = phy->ops.check_reset_block(hw); 2084 if (ret_val) { 2085 ret_val = E1000_SUCCESS; 2086 goto out; 2087 } 2088 2089 ret_val = phy->ops.acquire(hw); 2090 if (ret_val) 2091 goto out; 2092 2093 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2094 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2095 E1000_WRITE_FLUSH(hw); 2096 2097 usec_delay(phy->reset_delay_us); 2098 2099 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2100 E1000_WRITE_FLUSH(hw); 2101 2102 usec_delay(150); 2103 2104 phy->ops.release(hw); 2105 2106 ret_val = phy->ops.get_cfg_done(hw); 2107 2108 out: 2109 return (ret_val); 2110 } 2111 2112 /* 2113 * e1000_get_cfg_done_generic - Generic configuration done 2114 * @hw: pointer to the HW structure 2115 * 2116 * Generic function to wait 10 milli-seconds for configuration to complete 2117 * and return success. 2118 */ 2119 s32 2120 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2121 { 2122 DEBUGFUNC("e1000_get_cfg_done_generic"); 2123 UNREFERENCED_1PARAMETER(hw); 2124 2125 msec_delay_irq(10); 2126 2127 return (E1000_SUCCESS); 2128 } 2129 2130 /* 2131 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2132 * @hw: pointer to the HW structure 2133 * 2134 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2135 */ 2136 s32 2137 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2138 { 2139 DEBUGOUT("Running IGP 3 PHY init script\n"); 2140 2141 /* PHY init IGP 3 */ 2142 /* Enable rise/fall, 10-mode work in class-A */ 2143 (void) hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2144 /* Remove all caps from Replica path filter */ 2145 (void) hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2146 /* Bias trimming for ADC, AFE and Driver (Default) */ 2147 (void) hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2148 /* Increase Hybrid poly bias */ 2149 (void) hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2150 /* Add 4% to Tx amplitude in Gig mode */ 2151 (void) hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2152 /* Disable trimming (TTT) */ 2153 (void) hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2154 /* Poly DC correction to 94.6% + 2% for all channels */ 2155 (void) hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2156 /* ABS DC correction to 95.9% */ 2157 (void) hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2158 /* BG temp curve trim */ 2159 (void) hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2160 /* Increasing ADC OPAMP stage 1 currents to max */ 2161 (void) hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2162 /* Force 1000 ( required for enabling PHY regs configuration) */ 2163 (void) hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2164 /* Set upd_freq to 6 */ 2165 (void) hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2166 /* Disable NPDFE */ 2167 (void) hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2168 /* Disable adaptive fixed FFE (Default) */ 2169 (void) hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2170 /* Enable FFE hysteresis */ 2171 (void) hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2172 /* Fixed FFE for short cable lengths */ 2173 (void) hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2174 /* Fixed FFE for medium cable lengths */ 2175 (void) hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2176 /* Fixed FFE for long cable lengths */ 2177 (void) hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2178 /* Enable Adaptive Clip Threshold */ 2179 (void) hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2180 /* AHT reset limit to 1 */ 2181 (void) hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2182 /* Set AHT master delay to 127 msec */ 2183 (void) hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2184 /* Set scan bits for AHT */ 2185 (void) hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2186 /* Set AHT Preset bits */ 2187 (void) hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2188 /* Change integ_factor of channel A to 3 */ 2189 (void) hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2190 /* Change prop_factor of channels BCD to 8 */ 2191 (void) hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2192 /* Change cg_icount + enable integbp for channels BCD */ 2193 (void) hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2194 /* 2195 * Change cg_icount + enable integbp + change prop_factor_master 2196 * to 8 for channel A 2197 */ 2198 (void) hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2199 /* Disable AHT in Slave mode on channel A */ 2200 (void) hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2201 /* 2202 * Enable LPLU and disable AN to 1000 in non-D0a states, 2203 * Enable SPD+B2B 2204 */ 2205 (void) hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2206 /* Enable restart AN on an1000_dis change */ 2207 (void) hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2208 /* Enable wh_fifo read clock in 10/100 modes */ 2209 (void) hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2210 /* Restart AN, Speed selection is 1000 */ 2211 (void) hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2212 2213 return (E1000_SUCCESS); 2214 } 2215 2216 /* 2217 * e1000_get_phy_type_from_id - Get PHY type from id 2218 * @phy_id: phy_id read from the phy 2219 * 2220 * Returns the phy type from the id. 2221 */ 2222 enum e1000_phy_type 2223 e1000_get_phy_type_from_id(u32 phy_id) 2224 { 2225 enum e1000_phy_type phy_type = e1000_phy_unknown; 2226 2227 switch (phy_id) { 2228 case M88E1000_I_PHY_ID: 2229 case M88E1000_E_PHY_ID: 2230 case M88E1111_I_PHY_ID: 2231 case M88E1011_I_PHY_ID: 2232 phy_type = e1000_phy_m88; 2233 break; 2234 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2235 phy_type = e1000_phy_igp_2; 2236 break; 2237 case GG82563_E_PHY_ID: 2238 phy_type = e1000_phy_gg82563; 2239 break; 2240 case IGP03E1000_E_PHY_ID: 2241 phy_type = e1000_phy_igp_3; 2242 break; 2243 case IFE_E_PHY_ID: 2244 case IFE_PLUS_E_PHY_ID: 2245 case IFE_C_E_PHY_ID: 2246 phy_type = e1000_phy_ife; 2247 break; 2248 default: 2249 phy_type = e1000_phy_unknown; 2250 break; 2251 } 2252 return (phy_type); 2253 } 2254 2255 /* 2256 * e1000_determine_phy_address - Determines PHY address. 2257 * @hw: pointer to the HW structure 2258 * 2259 * This uses a trial and error method to loop through possible PHY 2260 * addresses. It tests each by reading the PHY ID registers and 2261 * checking for a match. 2262 */ 2263 s32 2264 e1000_determine_phy_address(struct e1000_hw *hw) 2265 { 2266 s32 ret_val = -E1000_ERR_PHY_TYPE; 2267 u32 phy_addr = 0; 2268 u32 i; 2269 enum e1000_phy_type phy_type = e1000_phy_unknown; 2270 2271 hw->phy.id = phy_type; 2272 2273 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2274 hw->phy.addr = phy_addr; 2275 i = 0; 2276 2277 do { 2278 e1000_get_phy_id(hw); 2279 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2280 2281 /* 2282 * If phy_type is valid, break - we found our 2283 * PHY address 2284 */ 2285 if (phy_type != e1000_phy_unknown) { 2286 ret_val = E1000_SUCCESS; 2287 goto out; 2288 } 2289 msec_delay(1); 2290 i++; 2291 } while (i < 10); 2292 } 2293 2294 out: 2295 return (ret_val); 2296 } 2297 /* 2298 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2299 * @hw: pointer to the HW structure 2300 * 2301 * In the case of a PHY power down to save power, or to turn off link during a 2302 * driver unload, or wake on lan is not enabled, restore the link to previous 2303 * settings. 2304 */ 2305 void 2306 e1000_power_up_phy_copper(struct e1000_hw *hw) 2307 { 2308 u16 mii_reg = 0; 2309 2310 /* The PHY will retain its settings across a power down/up cycle */ 2311 (void) hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2312 mii_reg &= ~MII_CR_POWER_DOWN; 2313 (void) hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2314 } 2315 2316 /* 2317 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2318 * @hw: pointer to the HW structure 2319 * 2320 * In the case of a PHY power down to save power, or to turn off link during a 2321 * driver unload, or wake on lan is not enabled, restore the link to previous 2322 * settings. 2323 */ 2324 void 2325 e1000_power_down_phy_copper(struct e1000_hw *hw) 2326 { 2327 u16 mii_reg = 0; 2328 2329 /* The PHY will retain its settings across a power down/up cycle */ 2330 (void) hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2331 mii_reg |= MII_CR_POWER_DOWN; 2332 (void) hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2333 msec_delay(1); 2334 } 2335