1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #ifndef _IGB_OSDEP_H 30 #define _IGB_OSDEP_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/conf.h> 38 #include <sys/debug.h> 39 #include <sys/stropts.h> 40 #include <sys/stream.h> 41 #include <sys/strlog.h> 42 #include <sys/kmem.h> 43 #include <sys/stat.h> 44 #include <sys/kstat.h> 45 #include <sys/modctl.h> 46 #include <sys/errno.h> 47 #include <sys/ddi.h> 48 #include <sys/dditypes.h> 49 #include <sys/sunddi.h> 50 #include <sys/pci.h> 51 #include <sys/pci_cap.h> 52 #include <sys/atomic.h> 53 #include <sys/note.h> 54 #include "igb_debug.h" 55 56 #define usec_delay(x) drv_usecwait(x) 57 #define msec_delay(x) drv_usecwait(x * 1000) 58 #define msec_delay_irq msec_delay 59 60 #ifdef IGB_DEBUG 61 #define DEBUGOUT(S) IGB_DEBUGLOG_0(NULL, S) 62 #define DEBUGOUT1(S, A) IGB_DEBUGLOG_1(NULL, S, A) 63 #define DEBUGOUT2(S, A, B) IGB_DEBUGLOG_2(NULL, S, A, B) 64 #define DEBUGOUT3(S, A, B, C) IGB_DEBUGLOG_3(NULL, S, A, B, C) 65 #else 66 #define DEBUGOUT(S) 67 #define DEBUGOUT1(S, A) 68 #define DEBUGOUT2(S, A, B) 69 #define DEBUGOUT3(S, A, B, C) 70 #endif 71 72 #define DEBUGFUNC(f) 73 74 #define OS_DEP(hw) ((struct igb_osdep *)((hw)->back)) 75 76 #define false B_FALSE 77 #define true B_TRUE 78 79 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 80 #define PCI_COMMAND_REGISTER 0x04 81 #define PCI_EX_CONF_CAP 0xE0 82 83 84 /* 85 * Constants used in setting flow control thresholds 86 */ 87 #define E1000_PBA_MASK 0xffff 88 #define E1000_PBA_SHIFT 10 89 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 90 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 91 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 92 93 /* PHY Extended Status Register */ 94 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 95 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 96 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 97 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 98 99 /* VMDq MODE supported by hardware */ 100 #define E1000_VMDQ_OFF 0 101 #define E1000_VMDQ_MAC 1 102 #define E1000_VMDQ_MAC_RSS 2 103 104 /* VMDq based on packet destination MAC address */ 105 #define E1000_MRQC_ENABLE_VMDQ_MAC_GROUP 0x00000003 106 /* VMDq based on packet destination MAC address and RSS */ 107 #define E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP 0x00000005 108 /* The default queue in each VMDqs */ 109 #define E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE 0x100 110 111 #define E1000_WRITE_FLUSH(a) (void) E1000_READ_REG(a, E1000_STATUS) 112 113 #define E1000_WRITE_REG(hw, reg, value) \ 114 ddi_put32((OS_DEP(hw))->reg_handle, \ 115 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), (value)) 116 117 #define E1000_READ_REG(hw, reg) \ 118 ddi_get32((OS_DEP(hw))->reg_handle, \ 119 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg)) 120 121 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ 122 ddi_put32((OS_DEP(hw))->reg_handle, \ 123 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)), \ 124 (value)) 125 126 #define E1000_READ_REG_ARRAY(hw, reg, offset) \ 127 ddi_get32((OS_DEP(hw))->reg_handle, \ 128 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2))) 129 130 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ 131 E1000_WRITE_REG_ARRAY(a, reg, offset, value) 132 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \ 133 E1000_READ_REG_ARRAY(a, reg, offset) 134 135 #define UNREFERENCED_1PARAMETER(_p) _NOTE(ARGUNUSED(_p)) 136 #define UNREFERENCED_2PARAMETER(_p, _q) _NOTE(ARGUNUSED(_p, _q)) 137 #define UNREFERENCED_3PARAMETER(_p, _q, _r) _NOTE(ARGUNUSED(_p, _q, _r)) 138 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q, _r, _s)) 139 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) \ 140 _NOTE(ARGUNUSED(_p, _q, _r, _s, _t)) 141 142 #define __le16 u16 143 #define __le32 u32 144 #define __le64 u64 145 146 typedef int8_t s8; 147 typedef int16_t s16; 148 typedef int32_t s32; 149 typedef int64_t s64; 150 typedef uint8_t u8; 151 typedef uint16_t u16; 152 typedef uint32_t u32; 153 typedef uint64_t u64; 154 typedef boolean_t bool; 155 156 struct igb_osdep { 157 ddi_acc_handle_t reg_handle; 158 ddi_acc_handle_t cfg_handle; 159 struct igb *igb; 160 }; 161 162 163 #ifdef __cplusplus 164 } 165 #endif 166 167 #endif /* _IGB_OSDEP_H */ 168