15779Sxy150489 /* 25779Sxy150489 * CDDL HEADER START 35779Sxy150489 * 4*8571SChenlu.Chen@Sun.COM * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 55779Sxy150489 * The contents of this file are subject to the terms of the 65779Sxy150489 * Common Development and Distribution License (the "License"). 75779Sxy150489 * You may not use this file except in compliance with the License. 85779Sxy150489 * 95779Sxy150489 * You can obtain a copy of the license at: 105779Sxy150489 * http://www.opensolaris.org/os/licensing. 115779Sxy150489 * See the License for the specific language governing permissions 125779Sxy150489 * and limitations under the License. 135779Sxy150489 * 145779Sxy150489 * When using or redistributing this file, you may do so under the 155779Sxy150489 * License only. No other modification of this header is permitted. 165779Sxy150489 * 175779Sxy150489 * If applicable, add the following below this CDDL HEADER, with the 185779Sxy150489 * fields enclosed by brackets "[]" replaced with your own identifying 195779Sxy150489 * information: Portions Copyright [yyyy] [name of copyright owner] 205779Sxy150489 * 215779Sxy150489 * CDDL HEADER END 225779Sxy150489 */ 235779Sxy150489 245779Sxy150489 /* 25*8571SChenlu.Chen@Sun.COM * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 265779Sxy150489 * Use is subject to license terms of the CDDL. 275779Sxy150489 */ 285779Sxy150489 29*8571SChenlu.Chen@Sun.COM /* IntelVersion: 1.18 v2008-10-7 */ 305812Sxy150489 315779Sxy150489 #ifndef _IGB_MANAGE_H 325779Sxy150489 #define _IGB_MANAGE_H 335779Sxy150489 345779Sxy150489 #ifdef __cplusplus 355779Sxy150489 extern "C" { 365779Sxy150489 #endif 375779Sxy150489 385779Sxy150489 bool e1000_check_mng_mode_generic(struct e1000_hw *hw); 395779Sxy150489 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw); 405779Sxy150489 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw); 415779Sxy150489 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, 425779Sxy150489 u16 length, u16 offset, u8 *sum); 435779Sxy150489 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, 445779Sxy150489 struct e1000_host_mng_command_header *hdr); 455779Sxy150489 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, 465779Sxy150489 u8 *buffer, u16 length); 47*8571SChenlu.Chen@Sun.COM bool e1000_enable_mng_pass_thru(struct e1000_hw *hw); 485779Sxy150489 49*8571SChenlu.Chen@Sun.COM enum e1000_mng_mode { 505779Sxy150489 e1000_mng_mode_none = 0, 515779Sxy150489 e1000_mng_mode_asf, 525779Sxy150489 e1000_mng_mode_pt, 535779Sxy150489 e1000_mng_mode_ipmi, 545779Sxy150489 e1000_mng_mode_host_if_only 55*8571SChenlu.Chen@Sun.COM }; 565779Sxy150489 575779Sxy150489 #define E1000_FACTPS_MNGCG 0x20000000 585779Sxy150489 595779Sxy150489 #define E1000_FWSM_MODE_MASK 0xE 605779Sxy150489 #define E1000_FWSM_MODE_SHIFT 1 615779Sxy150489 625779Sxy150489 #define E1000_MNG_IAMT_MODE 0x3 635779Sxy150489 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 645779Sxy150489 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 655779Sxy150489 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 665779Sxy150489 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 675779Sxy150489 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 685779Sxy150489 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 695779Sxy150489 705779Sxy150489 #define E1000_VFTA_ENTRY_SHIFT 5 715779Sxy150489 #define E1000_VFTA_ENTRY_MASK 0x7F 725779Sxy150489 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 735779Sxy150489 745779Sxy150489 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 755779Sxy150489 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 765779Sxy150489 /* Process HI command limit */ 775779Sxy150489 #define E1000_HI_COMMAND_TIMEOUT 500 785779Sxy150489 795779Sxy150489 #define E1000_HICR_EN 0x01 /* Enable bit - RO */ 805779Sxy150489 /* Driver sets this bit when done to put command in RAM */ 815779Sxy150489 #define E1000_HICR_C 0x02 825779Sxy150489 #define E1000_HICR_SV 0x04 /* Status Validity */ 835779Sxy150489 #define E1000_HICR_FW_RESET_ENABLE 0x40 845779Sxy150489 #define E1000_HICR_FW_RESET 0x80 855779Sxy150489 865779Sxy150489 /* Intel(R) Active Management Technology signature */ 875779Sxy150489 #define E1000_IAMT_SIGNATURE 0x544D4149 885779Sxy150489 895779Sxy150489 #ifdef __cplusplus 905779Sxy150489 } 915779Sxy150489 #endif 925779Sxy150489 935779Sxy150489 #endif /* _IGB_MANAGE_H */ 94