xref: /onnv-gate/usr/src/uts/common/io/igb/igb_manage.h (revision 12111:a462ebfcbf99)
15779Sxy150489 /*
25779Sxy150489  * CDDL HEADER START
35779Sxy150489  *
45779Sxy150489  * The contents of this file are subject to the terms of the
55779Sxy150489  * Common Development and Distribution License (the "License").
65779Sxy150489  * You may not use this file except in compliance with the License.
75779Sxy150489  *
8*12111SGuoqing.Zhu@Sun.COM  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*12111SGuoqing.Zhu@Sun.COM  * or http://www.opensolaris.org/os/licensing.
105779Sxy150489  * See the License for the specific language governing permissions
115779Sxy150489  * and limitations under the License.
125779Sxy150489  *
13*12111SGuoqing.Zhu@Sun.COM  * When distributing Covered Code, include this CDDL HEADER in each
14*12111SGuoqing.Zhu@Sun.COM  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
155779Sxy150489  * If applicable, add the following below this CDDL HEADER, with the
165779Sxy150489  * fields enclosed by brackets "[]" replaced with your own identifying
175779Sxy150489  * information: Portions Copyright [yyyy] [name of copyright owner]
185779Sxy150489  *
195779Sxy150489  * CDDL HEADER END
205779Sxy150489  */
215779Sxy150489 
225779Sxy150489 /*
23*12111SGuoqing.Zhu@Sun.COM  * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
245779Sxy150489  */
255779Sxy150489 
26*12111SGuoqing.Zhu@Sun.COM /*
27*12111SGuoqing.Zhu@Sun.COM  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28*12111SGuoqing.Zhu@Sun.COM  */
29*12111SGuoqing.Zhu@Sun.COM 
30*12111SGuoqing.Zhu@Sun.COM /* IntelVersion: 1.18 v3_3_14_3_BHSW1 */
315812Sxy150489 
325779Sxy150489 #ifndef _IGB_MANAGE_H
335779Sxy150489 #define	_IGB_MANAGE_H
345779Sxy150489 
355779Sxy150489 #ifdef __cplusplus
365779Sxy150489 extern "C" {
375779Sxy150489 #endif
385779Sxy150489 
395779Sxy150489 bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
405779Sxy150489 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
415779Sxy150489 s32  e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
425779Sxy150489 s32  e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
435779Sxy150489     u16 length, u16 offset, u8 *sum);
445779Sxy150489 s32  e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
455779Sxy150489     struct e1000_host_mng_command_header *hdr);
465779Sxy150489 s32  e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
475779Sxy150489     u8 *buffer, u16 length);
488571SChenlu.Chen@Sun.COM bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
495779Sxy150489 
508571SChenlu.Chen@Sun.COM enum e1000_mng_mode {
515779Sxy150489 	e1000_mng_mode_none = 0,
525779Sxy150489 	e1000_mng_mode_asf,
535779Sxy150489 	e1000_mng_mode_pt,
545779Sxy150489 	e1000_mng_mode_ipmi,
555779Sxy150489 	e1000_mng_mode_host_if_only
568571SChenlu.Chen@Sun.COM };
575779Sxy150489 
585779Sxy150489 #define	E1000_FACTPS_MNGCG    0x20000000
595779Sxy150489 
605779Sxy150489 #define	E1000_FWSM_MODE_MASK  0xE
615779Sxy150489 #define	E1000_FWSM_MODE_SHIFT 1
625779Sxy150489 
635779Sxy150489 #define	E1000_MNG_IAMT_MODE			0x3
645779Sxy150489 #define	E1000_MNG_DHCP_COOKIE_LENGTH		0x10
655779Sxy150489 #define	E1000_MNG_DHCP_COOKIE_OFFSET		0x6F0
665779Sxy150489 #define	E1000_MNG_DHCP_COMMAND_TIMEOUT		10
675779Sxy150489 #define	E1000_MNG_DHCP_TX_PAYLOAD_CMD		64
685779Sxy150489 #define	E1000_MNG_DHCP_COOKIE_STATUS_PARSING	0x1
695779Sxy150489 #define	E1000_MNG_DHCP_COOKIE_STATUS_VLAN	0x2
705779Sxy150489 
715779Sxy150489 #define	E1000_VFTA_ENTRY_SHIFT			5
725779Sxy150489 #define	E1000_VFTA_ENTRY_MASK			0x7F
735779Sxy150489 #define	E1000_VFTA_ENTRY_BIT_SHIFT_MASK		0x1F
745779Sxy150489 
755779Sxy150489 #define	E1000_HI_MAX_BLOCK_BYTE_LENGTH		1792 /* Num of bytes in range */
765779Sxy150489 #define	E1000_HI_MAX_BLOCK_DWORD_LENGTH		448 /* Num of dwords in range */
775779Sxy150489 /* Process HI command limit */
785779Sxy150489 #define	E1000_HI_COMMAND_TIMEOUT		500
795779Sxy150489 
805779Sxy150489 #define	E1000_HICR_EN			0x01  /* Enable bit - RO */
815779Sxy150489 /* Driver sets this bit when done to put command in RAM */
825779Sxy150489 #define	E1000_HICR_C			0x02
835779Sxy150489 #define	E1000_HICR_SV			0x04  /* Status Validity */
845779Sxy150489 #define	E1000_HICR_FW_RESET_ENABLE	0x40
855779Sxy150489 #define	E1000_HICR_FW_RESET		0x80
865779Sxy150489 
875779Sxy150489 /* Intel(R) Active Management Technology signature */
885779Sxy150489 #define	E1000_IAMT_SIGNATURE  0x544D4149
895779Sxy150489 
905779Sxy150489 #ifdef __cplusplus
915779Sxy150489 }
925779Sxy150489 #endif
935779Sxy150489 
945779Sxy150489 #endif	/* _IGB_MANAGE_H */
95