1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.92 v2008-10-7 */ 30 31 #include "igb_api.h" 32 33 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw); 34 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); 35 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); 36 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 37 38 /* 39 * e1000_init_mac_ops_generic - Initialize MAC function pointers 40 * @hw: pointer to the HW structure 41 * 42 * Setups up the function pointers to no-op functions 43 */ 44 void 45 e1000_init_mac_ops_generic(struct e1000_hw *hw) 46 { 47 struct e1000_mac_info *mac = &hw->mac; 48 DEBUGFUNC("e1000_init_mac_ops_generic"); 49 50 /* General Setup */ 51 mac->ops.init_params = e1000_null_ops_generic; 52 mac->ops.init_hw = e1000_null_ops_generic; 53 mac->ops.reset_hw = e1000_null_ops_generic; 54 mac->ops.setup_physical_interface = e1000_null_ops_generic; 55 mac->ops.get_bus_info = e1000_null_ops_generic; 56 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 57 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 58 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 59 /* LED */ 60 mac->ops.cleanup_led = e1000_null_ops_generic; 61 mac->ops.setup_led = e1000_null_ops_generic; 62 mac->ops.blink_led = e1000_null_ops_generic; 63 mac->ops.led_on = e1000_null_ops_generic; 64 mac->ops.led_off = e1000_null_ops_generic; 65 /* LINK */ 66 mac->ops.setup_link = e1000_null_ops_generic; 67 mac->ops.get_link_up_info = e1000_null_link_info; 68 mac->ops.check_for_link = e1000_null_ops_generic; 69 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 70 /* Management */ 71 mac->ops.check_mng_mode = e1000_null_mng_mode; 72 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 73 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 74 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 75 /* VLAN, MC, etc. */ 76 mac->ops.update_mc_addr_list = e1000_null_update_mc; 77 mac->ops.clear_vfta = e1000_null_mac_generic; 78 mac->ops.write_vfta = e1000_null_write_vfta; 79 mac->ops.mta_set = e1000_null_mta_set; 80 mac->ops.rar_set = e1000_rar_set_generic; 81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82 } 83 84 /* 85 * e1000_null_ops_generic - No-op function, returns 0 86 * @hw: pointer to the HW structure 87 */ 88 s32 89 e1000_null_ops_generic(struct e1000_hw *hw) 90 { 91 DEBUGFUNC("e1000_null_ops_generic"); 92 UNREFERENCED_1PARAMETER(hw); 93 return (E1000_SUCCESS); 94 } 95 96 /* 97 * e1000_null_mac_generic - No-op function, return void 98 * @hw: pointer to the HW structure 99 */ 100 void 101 e1000_null_mac_generic(struct e1000_hw *hw) 102 { 103 DEBUGFUNC("e1000_null_mac_generic"); 104 UNREFERENCED_1PARAMETER(hw); 105 } 106 107 /* 108 * e1000_null_link_info - No-op function, return 0 109 * @hw: pointer to the HW structure 110 */ 111 s32 112 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 113 { 114 DEBUGFUNC("e1000_null_link_info"); 115 UNREFERENCED_3PARAMETER(hw, s, d); 116 return (E1000_SUCCESS); 117 } 118 119 /* 120 * e1000_null_mng_mode - No-op function, return false 121 * @hw: pointer to the HW structure 122 */ 123 bool 124 e1000_null_mng_mode(struct e1000_hw *hw) 125 { 126 DEBUGFUNC("e1000_null_mng_mode"); 127 UNREFERENCED_1PARAMETER(hw); 128 return (false); 129 } 130 131 /* 132 * e1000_null_update_mc - No-op function, return void 133 * @hw: pointer to the HW structure 134 */ 135 void 136 e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a, u32 b, u32 c) 137 { 138 DEBUGFUNC("e1000_null_update_mc"); 139 UNREFERENCED_5PARAMETER(hw, h, a, b, c); 140 } 141 142 /* 143 * e1000_null_write_vfta - No-op function, return void 144 * @hw: pointer to the HW structure 145 */ 146 void 147 e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 148 { 149 DEBUGFUNC("e1000_null_write_vfta"); 150 UNREFERENCED_3PARAMETER(hw, a, b); 151 } 152 153 /* 154 * e1000_null_set_mta - No-op function, return void 155 * @hw: pointer to the HW structure 156 */ 157 void 158 e1000_null_mta_set(struct e1000_hw *hw, u32 a) 159 { 160 DEBUGFUNC("e1000_null_mta_set"); 161 UNREFERENCED_2PARAMETER(hw, a); 162 } 163 164 /* 165 * e1000_null_rar_set - No-op function, return void 166 * @hw: pointer to the HW structure 167 */ 168 void 169 e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 170 { 171 DEBUGFUNC("e1000_null_rar_set"); 172 UNREFERENCED_3PARAMETER(hw, h, a); 173 } 174 175 /* 176 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 177 * @hw: pointer to the HW structure 178 * 179 * Determines and stores the system bus information for a particular 180 * network interface. The following bus information is determined and stored: 181 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 182 */ 183 s32 184 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 185 { 186 struct e1000_bus_info *bus = &hw->bus; 187 u32 status = E1000_READ_REG(hw, E1000_STATUS); 188 s32 ret_val = E1000_SUCCESS; 189 u16 pci_header_type; 190 191 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 192 193 /* PCI or PCI-X? */ 194 bus->type = (status & E1000_STATUS_PCIX_MODE) 195 ? e1000_bus_type_pcix 196 : e1000_bus_type_pci; 197 198 /* Bus speed */ 199 if (bus->type == e1000_bus_type_pci) { 200 bus->speed = (status & E1000_STATUS_PCI66) 201 ? e1000_bus_speed_66 202 : e1000_bus_speed_33; 203 } else { 204 switch (status & E1000_STATUS_PCIX_SPEED) { 205 case E1000_STATUS_PCIX_SPEED_66: 206 bus->speed = e1000_bus_speed_66; 207 break; 208 case E1000_STATUS_PCIX_SPEED_100: 209 bus->speed = e1000_bus_speed_100; 210 break; 211 case E1000_STATUS_PCIX_SPEED_133: 212 bus->speed = e1000_bus_speed_133; 213 break; 214 default: 215 bus->speed = e1000_bus_speed_reserved; 216 break; 217 } 218 } 219 220 /* Bus width */ 221 bus->width = (status & E1000_STATUS_BUS64) 222 ? e1000_bus_width_64 223 : e1000_bus_width_32; 224 225 /* Which PCI(-X) function? */ 226 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 227 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) 228 bus->func = (status & E1000_STATUS_FUNC_MASK) 229 >> E1000_STATUS_FUNC_SHIFT; 230 else 231 bus->func = 0; 232 233 return (ret_val); 234 } 235 236 /* 237 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 238 * @hw: pointer to the HW structure 239 * 240 * Determines and stores the system bus information for a particular 241 * network interface. The following bus information is determined and stored: 242 * bus speed, bus width, type (PCIe), and PCIe function. 243 */ 244 s32 245 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 246 { 247 struct e1000_bus_info *bus = &hw->bus; 248 s32 ret_val; 249 u32 status; 250 u16 pcie_link_status, pci_header_type; 251 252 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 253 254 bus->type = e1000_bus_type_pci_express; 255 bus->speed = e1000_bus_speed_2500; 256 257 ret_val = e1000_read_pcie_cap_reg(hw, 258 PCIE_LINK_STATUS, &pcie_link_status); 259 if (ret_val) 260 bus->width = e1000_bus_width_unknown; 261 else 262 bus->width = (enum e1000_bus_width)((pcie_link_status & 263 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 264 265 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 266 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 267 status = E1000_READ_REG(hw, E1000_STATUS); 268 bus->func = (status & E1000_STATUS_FUNC_MASK) 269 >> E1000_STATUS_FUNC_SHIFT; 270 } else { 271 bus->func = 0; 272 } 273 274 return (E1000_SUCCESS); 275 } 276 277 /* 278 * e1000_clear_vfta_generic - Clear VLAN filter table 279 * @hw: pointer to the HW structure 280 * 281 * Clears the register array which contains the VLAN filter table by 282 * setting all the values to 0. 283 */ 284 void 285 e1000_clear_vfta_generic(struct e1000_hw *hw) 286 { 287 u32 offset; 288 289 DEBUGFUNC("e1000_clear_vfta_generic"); 290 291 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 292 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 293 E1000_WRITE_FLUSH(hw); 294 } 295 } 296 297 /* 298 * e1000_write_vfta_generic - Write value to VLAN filter table 299 * @hw: pointer to the HW structure 300 * @offset: register offset in VLAN filter table 301 * @value: register value written to VLAN filter table 302 * 303 * Writes value at the given offset in the register array which stores 304 * the VLAN filter table. 305 */ 306 void 307 e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 308 { 309 DEBUGFUNC("e1000_write_vfta_generic"); 310 311 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 312 E1000_WRITE_FLUSH(hw); 313 } 314 315 /* 316 * e1000_init_rx_addrs_generic - Initialize receive address's 317 * @hw: pointer to the HW structure 318 * @rar_count: receive address registers 319 * 320 * Setups the receive address registers by setting the base receive address 321 * register to the devices MAC address and clearing all the other receive 322 * address registers to 0. 323 */ 324 void 325 e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 326 { 327 u32 i; 328 329 DEBUGFUNC("e1000_init_rx_addrs_generic"); 330 331 /* Setup the receive address */ 332 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 333 334 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 335 336 /* Zero out the other (rar_entry_count - 1) receive addresses */ 337 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 338 for (i = 1; i < rar_count; i++) { 339 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); 340 E1000_WRITE_FLUSH(hw); 341 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); 342 E1000_WRITE_FLUSH(hw); 343 } 344 } 345 346 /* 347 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 348 * @hw: pointer to the HW structure 349 * 350 * Checks the nvm for an alternate MAC address. An alternate MAC address 351 * can be setup by pre-boot software and must be treated like a permanent 352 * address and must override the actual permanent MAC address. If an 353 * alternate MAC address is found it is saved in the hw struct and 354 * programmed into RAR0 and the function returns success, otherwise the 355 * function returns an error. 356 */ 357 s32 358 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 359 { 360 u32 i; 361 s32 ret_val = E1000_SUCCESS; 362 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 363 u8 alt_mac_addr[ETH_ADDR_LEN]; 364 365 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 366 367 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 368 &nvm_alt_mac_addr_offset); 369 if (ret_val) { 370 DEBUGOUT("NVM Read Error\n"); 371 goto out; 372 } 373 374 if (nvm_alt_mac_addr_offset == 0xFFFF) { 375 ret_val = -(E1000_NOT_IMPLEMENTED); 376 goto out; 377 } 378 379 if (hw->bus.func == E1000_FUNC_1) 380 nvm_alt_mac_addr_offset += ETH_ADDR_LEN / sizeof (u16); 381 382 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 383 offset = nvm_alt_mac_addr_offset + (i >> 1); 384 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 385 if (ret_val) { 386 DEBUGOUT("NVM Read Error\n"); 387 goto out; 388 } 389 390 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 391 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 392 } 393 394 /* if multicast bit is set, the alternate address will not be used */ 395 if (alt_mac_addr[0] & 0x01) { 396 ret_val = -(E1000_NOT_IMPLEMENTED); 397 goto out; 398 } 399 400 for (i = 0; i < ETH_ADDR_LEN; i++) 401 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; 402 403 hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0); 404 405 out: 406 return (ret_val); 407 } 408 409 /* 410 * e1000_rar_set_generic - Set receive address register 411 * @hw: pointer to the HW structure 412 * @addr: pointer to the receive address 413 * @index: receive address array register 414 * 415 * Sets the receive address array register at index to the address passed 416 * in by addr. 417 */ 418 void 419 e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 420 { 421 u32 rar_low, rar_high; 422 423 DEBUGFUNC("e1000_rar_set_generic"); 424 425 /* 426 * HW expects these in little endian so we reverse the byte order 427 * from network order (big endian) to little endian 428 */ 429 rar_low = ((u32) addr[0] | 430 ((u32) addr[1] << 8) | 431 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 432 433 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 434 435 /* If MAC address zero, no need to set the AV bit */ 436 if (rar_low || rar_high) 437 rar_high |= E1000_RAH_AV; 438 439 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 440 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 441 } 442 443 /* 444 * e1000_mta_set_generic - Set multicast filter table address 445 * @hw: pointer to the HW structure 446 * @hash_value: determines the MTA register and bit to set 447 * 448 * The multicast table address is a register array of 32-bit registers. 449 * The hash_value is used to determine what register the bit is in, the 450 * current value is read, the new bit is OR'd in and the new value is 451 * written back into the register. 452 */ 453 void 454 e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 455 { 456 u32 hash_bit, hash_reg, mta; 457 458 DEBUGFUNC("e1000_mta_set_generic"); 459 /* 460 * The MTA is a register array of 32-bit registers. It is 461 * treated like an array of (32*mta_reg_count) bits. We want to 462 * set bit BitArray[hash_value]. So we figure out what register 463 * the bit is in, read it, OR in the new bit, then write 464 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 465 * mask to bits 31:5 of the hash value which gives us the 466 * register we're modifying. The hash bit within that register 467 * is determined by the lower 5 bits of the hash value. 468 */ 469 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 470 hash_bit = hash_value & 0x1F; 471 472 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 473 474 mta |= (1 << hash_bit); 475 476 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 477 E1000_WRITE_FLUSH(hw); 478 } 479 480 /* 481 * e1000_update_mc_addr_list_generic - Update Multicast addresses 482 * @hw: pointer to the HW structure 483 * @mc_addr_list: array of multicast addresses to program 484 * @mc_addr_count: number of multicast addresses to program 485 * @rar_used_count: the first RAR register free to program 486 * @rar_count: total number of supported Receive Address Registers 487 * 488 * Updates the Receive Address Registers and Multicast Table Array. 489 * The caller must have a packed mc_addr_list of multicast addresses. 490 * The parameter rar_count will usually be hw->mac.rar_entry_count 491 * unless there are workarounds that change this. 492 */ 493 void 494 e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 495 u8 *mc_addr_list, u32 mc_addr_count, 496 u32 rar_used_count, u32 rar_count) 497 { 498 u32 hash_value; 499 u32 i; 500 501 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 502 503 /* 504 * Load the first set of multicast addresses into the exact 505 * filters (RAR). If there are not enough to fill the RAR 506 * array, clear the filters. 507 */ 508 for (i = rar_used_count; i < rar_count; i++) { 509 if (mc_addr_count) { 510 hw->mac.ops.rar_set(hw, mc_addr_list, i); 511 mc_addr_count--; 512 mc_addr_list += ETH_ADDR_LEN; 513 } else { 514 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); 515 E1000_WRITE_FLUSH(hw); 516 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); 517 E1000_WRITE_FLUSH(hw); 518 } 519 } 520 521 /* Clear the old settings from the MTA */ 522 DEBUGOUT("Clearing MTA\n"); 523 for (i = 0; i < hw->mac.mta_reg_count; i++) { 524 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 525 E1000_WRITE_FLUSH(hw); 526 } 527 528 /* Load any remaining multicast addresses into the hash table. */ 529 for (; mc_addr_count > 0; mc_addr_count--) { 530 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 531 DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 532 hw->mac.ops.mta_set(hw, hash_value); 533 mc_addr_list += ETH_ADDR_LEN; 534 } 535 } 536 537 /* 538 * e1000_hash_mc_addr_generic - Generate a multicast hash value 539 * @hw: pointer to the HW structure 540 * @mc_addr: pointer to a multicast address 541 * 542 * Generates a multicast address hash value which is used to determine 543 * the multicast filter table array address and new table value. See 544 * e1000_mta_set_generic() 545 */ 546 u32 547 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 548 { 549 u32 hash_value, hash_mask; 550 u8 bit_shift = 0; 551 552 DEBUGFUNC("e1000_hash_mc_addr_generic"); 553 554 /* Register count multiplied by bits per register */ 555 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 556 557 /* 558 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 559 * where 0xFF would still fall within the hash mask. 560 */ 561 while (hash_mask >> bit_shift != 0xFF) 562 bit_shift++; 563 564 /* 565 * The portion of the address that is used for the hash table 566 * is determined by the mc_filter_type setting. 567 * The algorithm is such that there is a total of 8 bits of shifting. 568 * The bit_shift for a mc_filter_type of 0 represents the number of 569 * left-shifts where the MSB of mc_addr[5] would still fall within 570 * the hash_mask. Case 0 does this exactly. Since there are a total 571 * of 8 bits of shifting, then mc_addr[4] will shift right the 572 * remaining number of bits. Thus 8 - bit_shift. The rest of the 573 * cases are a variation of this algorithm...essentially raising the 574 * number of bits to shift mc_addr[5] left, while still keeping the 575 * 8-bit shifting total. 576 * 577 * For example, given the following Destination MAC Address and an 578 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 579 * we can see that the bit_shift for case 0 is 4. These are the hash 580 * values resulting from each mc_filter_type... 581 * [0] [1] [2] [3] [4] [5] 582 * 01 AA 00 12 34 56 583 * LSB MSB 584 * 585 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 586 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 587 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 588 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 589 */ 590 switch (hw->mac.mc_filter_type) { 591 default: 592 case 0: 593 break; 594 case 1: 595 bit_shift += 1; 596 break; 597 case 2: 598 bit_shift += 2; 599 break; 600 case 3: 601 bit_shift += 4; 602 break; 603 } 604 605 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 606 (((u16) mc_addr[5]) << bit_shift))); 607 608 return (hash_value); 609 } 610 611 /* 612 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 613 * @hw: pointer to the HW structure 614 * 615 * In certain situations, a system BIOS may report that the PCIx maximum 616 * memory read byte count (MMRBC) value is higher than than the actual 617 * value. We check the PCIx command register with the current PCIx status 618 * register. 619 */ 620 void 621 e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 622 { 623 u16 cmd_mmrbc; 624 u16 pcix_cmd; 625 u16 pcix_stat_hi_word; 626 u16 stat_mmrbc; 627 628 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 629 630 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 631 if (hw->bus.type != e1000_bus_type_pcix) 632 return; 633 634 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 635 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 636 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 637 PCIX_COMMAND_MMRBC_SHIFT; 638 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 639 PCIX_STATUS_HI_MMRBC_SHIFT; 640 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 641 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 642 if (cmd_mmrbc > stat_mmrbc) { 643 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 644 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 645 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 646 } 647 } 648 649 /* 650 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 651 * @hw: pointer to the HW structure 652 * 653 * Clears the base hardware counters by reading the counter registers. 654 */ 655 void 656 e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 657 { 658 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 659 660 (void) E1000_READ_REG(hw, E1000_CRCERRS); 661 (void) E1000_READ_REG(hw, E1000_SYMERRS); 662 (void) E1000_READ_REG(hw, E1000_MPC); 663 (void) E1000_READ_REG(hw, E1000_SCC); 664 (void) E1000_READ_REG(hw, E1000_ECOL); 665 (void) E1000_READ_REG(hw, E1000_MCC); 666 (void) E1000_READ_REG(hw, E1000_LATECOL); 667 (void) E1000_READ_REG(hw, E1000_COLC); 668 (void) E1000_READ_REG(hw, E1000_DC); 669 (void) E1000_READ_REG(hw, E1000_SEC); 670 (void) E1000_READ_REG(hw, E1000_RLEC); 671 (void) E1000_READ_REG(hw, E1000_XONRXC); 672 (void) E1000_READ_REG(hw, E1000_XONTXC); 673 (void) E1000_READ_REG(hw, E1000_XOFFRXC); 674 (void) E1000_READ_REG(hw, E1000_XOFFTXC); 675 (void) E1000_READ_REG(hw, E1000_FCRUC); 676 (void) E1000_READ_REG(hw, E1000_GPRC); 677 (void) E1000_READ_REG(hw, E1000_BPRC); 678 (void) E1000_READ_REG(hw, E1000_MPRC); 679 (void) E1000_READ_REG(hw, E1000_GPTC); 680 (void) E1000_READ_REG(hw, E1000_GORCL); 681 (void) E1000_READ_REG(hw, E1000_GORCH); 682 (void) E1000_READ_REG(hw, E1000_GOTCL); 683 (void) E1000_READ_REG(hw, E1000_GOTCH); 684 (void) E1000_READ_REG(hw, E1000_RNBC); 685 (void) E1000_READ_REG(hw, E1000_RUC); 686 (void) E1000_READ_REG(hw, E1000_RFC); 687 (void) E1000_READ_REG(hw, E1000_ROC); 688 (void) E1000_READ_REG(hw, E1000_RJC); 689 (void) E1000_READ_REG(hw, E1000_TORL); 690 (void) E1000_READ_REG(hw, E1000_TORH); 691 (void) E1000_READ_REG(hw, E1000_TOTL); 692 (void) E1000_READ_REG(hw, E1000_TOTH); 693 (void) E1000_READ_REG(hw, E1000_TPR); 694 (void) E1000_READ_REG(hw, E1000_TPT); 695 (void) E1000_READ_REG(hw, E1000_MPTC); 696 (void) E1000_READ_REG(hw, E1000_BPTC); 697 } 698 699 /* 700 * e1000_check_for_copper_link_generic - Check for link (Copper) 701 * @hw: pointer to the HW structure 702 * 703 * Checks to see of the link status of the hardware has changed. If a 704 * change in link status has been detected, then we read the PHY registers 705 * to get the current speed/duplex if link exists. 706 */ 707 s32 708 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 709 { 710 struct e1000_mac_info *mac = &hw->mac; 711 s32 ret_val; 712 bool link; 713 714 DEBUGFUNC("e1000_check_for_copper_link"); 715 716 /* 717 * We only want to go out to the PHY registers to see if Auto-Neg 718 * has completed and/or if our link status has changed. The 719 * get_link_status flag is set upon receiving a Link Status 720 * Change or Rx Sequence Error interrupt. 721 */ 722 if (!mac->get_link_status) { 723 ret_val = E1000_SUCCESS; 724 goto out; 725 } 726 727 /* 728 * First we want to see if the MII Status Register reports 729 * link. If so, then we want to get the current speed/duplex 730 * of the PHY. 731 */ 732 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 733 if (ret_val) 734 goto out; 735 736 if (!link) 737 goto out; /* No link detected */ 738 739 mac->get_link_status = false; 740 741 /* 742 * Check if there was DownShift, must be checked 743 * immediately after link-up 744 */ 745 (void) e1000_check_downshift_generic(hw); 746 747 /* 748 * If we are forcing speed/duplex, then we simply return since 749 * we have already determined whether we have link or not. 750 */ 751 if (!mac->autoneg) { 752 ret_val = -E1000_ERR_CONFIG; 753 goto out; 754 } 755 756 /* 757 * Auto-Neg is enabled. Auto Speed Detection takes care 758 * of MAC speed/duplex configuration. So we only need to 759 * configure Collision Distance in the MAC. 760 */ 761 e1000_config_collision_dist_generic(hw); 762 763 /* 764 * Configure Flow Control now that Auto-Neg has completed. 765 * First, we need to restore the desired flow control 766 * settings because we may have had to re-autoneg with a 767 * different link partner. 768 */ 769 ret_val = e1000_config_fc_after_link_up_generic(hw); 770 if (ret_val) 771 DEBUGOUT("Error configuring flow control\n"); 772 773 out: 774 return (ret_val); 775 } 776 777 /* 778 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 779 * @hw: pointer to the HW structure 780 * 781 * Checks for link up on the hardware. If link is not up and we have 782 * a signal, then we need to force link up. 783 */ 784 s32 785 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 786 { 787 struct e1000_mac_info *mac = &hw->mac; 788 u32 rxcw; 789 u32 ctrl; 790 u32 status; 791 s32 ret_val = E1000_SUCCESS; 792 793 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 794 795 ctrl = E1000_READ_REG(hw, E1000_CTRL); 796 status = E1000_READ_REG(hw, E1000_STATUS); 797 rxcw = E1000_READ_REG(hw, E1000_RXCW); 798 799 /* 800 * If we don't have link (auto-negotiation failed or link partner 801 * cannot auto-negotiate), the cable is plugged in (we have signal), 802 * and our link partner is not trying to auto-negotiate with us (we 803 * are receiving idles or data), we need to force link up. We also 804 * need to give auto-negotiation time to complete, in case the cable 805 * was just plugged in. The autoneg_failed flag does this. 806 */ 807 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 808 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 809 (!(rxcw & E1000_RXCW_C))) { 810 if (mac->autoneg_failed == 0) { 811 mac->autoneg_failed = 1; 812 goto out; 813 } 814 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 815 816 /* Disable auto-negotiation in the TXCW register */ 817 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 818 819 /* Force link-up and also force full-duplex. */ 820 ctrl = E1000_READ_REG(hw, E1000_CTRL); 821 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 822 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 823 824 /* Configure Flow Control after forcing link up. */ 825 ret_val = e1000_config_fc_after_link_up_generic(hw); 826 if (ret_val) { 827 DEBUGOUT("Error configuring flow control\n"); 828 goto out; 829 } 830 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 831 /* 832 * If we are forcing link and we are receiving /C/ ordered 833 * sets, re-enable auto-negotiation in the TXCW register 834 * and disable forced link in the Device Control register 835 * in an attempt to auto-negotiate with our link partner. 836 */ 837 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 838 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 839 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 840 841 mac->serdes_has_link = true; 842 } 843 844 out: 845 return (ret_val); 846 } 847 848 /* 849 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 850 * @hw: pointer to the HW structure 851 * 852 * Checks for link up on the hardware. If link is not up and we have 853 * a signal, then we need to force link up. 854 */ 855 s32 856 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 857 { 858 struct e1000_mac_info *mac = &hw->mac; 859 u32 rxcw; 860 u32 ctrl; 861 u32 status; 862 s32 ret_val = E1000_SUCCESS; 863 864 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 865 866 ctrl = E1000_READ_REG(hw, E1000_CTRL); 867 status = E1000_READ_REG(hw, E1000_STATUS); 868 rxcw = E1000_READ_REG(hw, E1000_RXCW); 869 870 /* 871 * If we don't have link (auto-negotiation failed or link partner 872 * cannot auto-negotiate), and our link partner is not trying to 873 * auto-negotiate with us (we are receiving idles or data), 874 * we need to force link up. We also need to give auto-negotiation 875 * time to complete. 876 */ 877 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 878 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 879 if (mac->autoneg_failed == 0) { 880 mac->autoneg_failed = 1; 881 goto out; 882 } 883 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 884 885 /* Disable auto-negotiation in the TXCW register */ 886 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 887 888 /* Force link-up and also force full-duplex. */ 889 ctrl = E1000_READ_REG(hw, E1000_CTRL); 890 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 891 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 892 893 /* Configure Flow Control after forcing link up. */ 894 ret_val = e1000_config_fc_after_link_up_generic(hw); 895 if (ret_val) { 896 DEBUGOUT("Error configuring flow control\n"); 897 goto out; 898 } 899 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 900 /* 901 * If we are forcing link and we are receiving /C/ ordered 902 * sets, re-enable auto-negotiation in the TXCW register 903 * and disable forced link in the Device Control register 904 * in an attempt to auto-negotiate with our link partner. 905 */ 906 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 907 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 908 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 909 910 mac->serdes_has_link = true; 911 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 912 /* 913 * If we force link for non-auto-negotiation switch, check 914 * link status based on MAC synchronization for internal 915 * serdes media type. 916 */ 917 /* SYNCH bit and IV bit are sticky. */ 918 usec_delay(10); 919 rxcw = E1000_READ_REG(hw, E1000_RXCW); 920 if (rxcw & E1000_RXCW_SYNCH) { 921 if (!(rxcw & E1000_RXCW_IV)) { 922 mac->serdes_has_link = true; 923 DEBUGOUT("SERDES: Link up - forced.\n"); 924 } 925 } else { 926 mac->serdes_has_link = false; 927 DEBUGOUT("SERDES: Link down - force failed.\n"); 928 } 929 } 930 931 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 932 status = E1000_READ_REG(hw, E1000_STATUS); 933 if (status & E1000_STATUS_LU) { 934 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 935 usec_delay(10); 936 rxcw = E1000_READ_REG(hw, E1000_RXCW); 937 if (rxcw & E1000_RXCW_SYNCH) { 938 if (!(rxcw & E1000_RXCW_IV)) { 939 mac->serdes_has_link = true; 940 DEBUGOUT("SERDES: Link up - autoneg " 941 "completed sucessfully.\n"); 942 } else { 943 mac->serdes_has_link = false; 944 DEBUGOUT("SERDES: Link down - invalid" 945 "codewords detected in autoneg.\n"); 946 } 947 } else { 948 mac->serdes_has_link = false; 949 DEBUGOUT("SERDES: Link down - no sync.\n"); 950 } 951 } else { 952 mac->serdes_has_link = false; 953 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 954 } 955 } 956 957 out: 958 return (ret_val); 959 } 960 961 /* 962 * e1000_setup_link_generic - Setup flow control and link settings 963 * @hw: pointer to the HW structure 964 * 965 * Determines which flow control settings to use, then configures flow 966 * control. Calls the appropriate media-specific link configuration 967 * function. Assuming the adapter has a valid link partner, a valid link 968 * should be established. Assumes the hardware has previously been reset 969 * and the transmitter and receiver are not enabled. 970 */ 971 s32 972 e1000_setup_link_generic(struct e1000_hw *hw) 973 { 974 s32 ret_val = E1000_SUCCESS; 975 976 DEBUGFUNC("e1000_setup_link_generic"); 977 978 /* 979 * In the case of the phy reset being blocked, we already have a link. 980 * We do not need to set it up again. 981 */ 982 if (hw->phy.ops.check_reset_block) 983 if (hw->phy.ops.check_reset_block(hw)) 984 goto out; 985 986 /* 987 * If requested flow control is set to default, set flow control 988 * based on the EEPROM flow control settings. 989 */ 990 if (hw->fc.requested_mode == e1000_fc_default) { 991 ret_val = e1000_set_default_fc_generic(hw); 992 if (ret_val) 993 goto out; 994 } 995 996 /* 997 * Save off the requested flow control mode for use later. Depending 998 * on the link partner's capabilities, we may or may not use this mode. 999 */ 1000 hw->fc.current_mode = hw->fc.requested_mode; 1001 1002 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1003 hw->fc.current_mode); 1004 1005 /* Call the necessary media_type subroutine to configure the link. */ 1006 ret_val = hw->mac.ops.setup_physical_interface(hw); 1007 if (ret_val) 1008 goto out; 1009 1010 /* 1011 * Initialize the flow control address, type, and PAUSE timer 1012 * registers to their default values. This is done even if flow 1013 * control is disabled, because it does not hurt anything to 1014 * initialize these registers. 1015 */ 1016 DEBUGOUT("Initializing the Flow Control address,type and timer regs\n"); 1017 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1018 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1019 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1020 1021 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1022 1023 ret_val = e1000_set_fc_watermarks_generic(hw); 1024 1025 out: 1026 return (ret_val); 1027 } 1028 1029 /* 1030 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1031 * @hw: pointer to the HW structure 1032 * 1033 * Configures collision distance and flow control for fiber and serdes 1034 * links. Upon successful setup, poll for link. 1035 */ 1036 s32 1037 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1038 { 1039 u32 ctrl; 1040 s32 ret_val = E1000_SUCCESS; 1041 1042 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1043 1044 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1045 1046 /* Take the link out of reset */ 1047 ctrl &= ~E1000_CTRL_LRST; 1048 1049 e1000_config_collision_dist_generic(hw); 1050 1051 ret_val = e1000_commit_fc_settings_generic(hw); 1052 if (ret_val) 1053 goto out; 1054 1055 /* 1056 * Since auto-negotiation is enabled, take the link out of reset (the 1057 * link will be in reset, because we previously reset the chip). This 1058 * will restart auto-negotiation. If auto-negotiation is successful 1059 * then the link-up status bit will be set and the flow control enable 1060 * bits (RFCE and TFCE) will be set according to their negotiated value. 1061 */ 1062 DEBUGOUT("Auto-negotiation enabled\n"); 1063 1064 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1065 E1000_WRITE_FLUSH(hw); 1066 msec_delay(1); 1067 1068 /* 1069 * For these adapters, the SW definable pin 1 is set when the optics 1070 * detect a signal. If we have a signal, then poll for a "Link-Up" 1071 * indication. 1072 */ 1073 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1074 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1075 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1076 } else { 1077 DEBUGOUT("No signal detected\n"); 1078 } 1079 1080 out: 1081 return (ret_val); 1082 } 1083 1084 /* 1085 * e1000_config_collision_dist_generic - Configure collision distance 1086 * @hw: pointer to the HW structure 1087 * 1088 * Configures the collision distance to the default value and is used 1089 * during link setup. Currently no func pointer exists and all 1090 * implementations are handled in the generic version of this function. 1091 */ 1092 void 1093 e1000_config_collision_dist_generic(struct e1000_hw *hw) 1094 { 1095 u32 tctl; 1096 1097 DEBUGFUNC("e1000_config_collision_dist_generic"); 1098 1099 tctl = E1000_READ_REG(hw, E1000_TCTL); 1100 1101 tctl &= ~E1000_TCTL_COLD; 1102 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1103 1104 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1105 E1000_WRITE_FLUSH(hw); 1106 } 1107 1108 /* 1109 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1110 * @hw: pointer to the HW structure 1111 * 1112 * Polls for link up by reading the status register, if link fails to come 1113 * up with auto-negotiation, then the link is forced if a signal is detected. 1114 */ 1115 s32 1116 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1117 { 1118 struct e1000_mac_info *mac = &hw->mac; 1119 u32 i, status; 1120 s32 ret_val = E1000_SUCCESS; 1121 1122 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1123 1124 /* 1125 * If we have a signal (the cable is plugged in, or assumed true for 1126 * serdes media) then poll for a "Link-Up" indication in the Device 1127 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1128 * seconds (Auto-negotiation should complete in less than 500 1129 * milliseconds even if the other end is doing it in SW). 1130 */ 1131 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1132 msec_delay(10); 1133 status = E1000_READ_REG(hw, E1000_STATUS); 1134 if (status & E1000_STATUS_LU) 1135 break; 1136 } 1137 if (i == FIBER_LINK_UP_LIMIT) { 1138 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1139 mac->autoneg_failed = 1; 1140 /* 1141 * AutoNeg failed to achieve a link, so we'll call 1142 * mac->check_for_link. This routine will force the 1143 * link up if we detect a signal. This will allow us to 1144 * communicate with non-autonegotiating link partners. 1145 */ 1146 ret_val = hw->mac.ops.check_for_link(hw); 1147 if (ret_val) { 1148 DEBUGOUT("Error while checking for link\n"); 1149 goto out; 1150 } 1151 mac->autoneg_failed = 0; 1152 } else { 1153 mac->autoneg_failed = 0; 1154 DEBUGOUT("Valid Link Found\n"); 1155 } 1156 1157 out: 1158 return (ret_val); 1159 } 1160 1161 /* 1162 * e1000_commit_fc_settings_generic - Configure flow control 1163 * @hw: pointer to the HW structure 1164 * 1165 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1166 * base on the flow control settings in e1000_mac_info. 1167 */ 1168 s32 1169 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1170 { 1171 struct e1000_mac_info *mac = &hw->mac; 1172 u32 txcw; 1173 s32 ret_val = E1000_SUCCESS; 1174 1175 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1176 1177 /* 1178 * Check for a software override of the flow control settings, and 1179 * setup the device accordingly. If auto-negotiation is enabled, then 1180 * software will have to set the "PAUSE" bits to the correct value in 1181 * the Transmit Config Word Register (TXCW) and re-start auto- 1182 * negotiation. However, if auto-negotiation is disabled, then 1183 * software will have to manually configure the two flow control enable 1184 * bits in the CTRL register. 1185 * 1186 * The possible values of the "fc" parameter are: 1187 * 0: Flow control is completely disabled 1188 * 1: Rx flow control is enabled (we can receive pause frames, 1189 * but not send pause frames). 1190 * 2: Tx flow control is enabled (we can send pause frames but we 1191 * do not support receiving pause frames). 1192 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1193 */ 1194 switch (hw->fc.current_mode) { 1195 case e1000_fc_none: 1196 /* Flow control completely disabled by a software over-ride. */ 1197 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1198 break; 1199 case e1000_fc_rx_pause: 1200 /* 1201 * Rx Flow control is enabled and Tx Flow control is disabled 1202 * by a software over-ride. Since there really isn't a way to 1203 * advertise that we are capable of Rx Pause ONLY, we will 1204 * advertise that we support both symmetric and asymmetric RX 1205 * PAUSE. Later, we will disable the adapter's ability to send 1206 * PAUSE frames. 1207 */ 1208 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1209 break; 1210 case e1000_fc_tx_pause: 1211 /* 1212 * Tx Flow control is enabled, and Rx Flow control is disabled, 1213 * by a software over-ride. 1214 */ 1215 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1216 break; 1217 case e1000_fc_full: 1218 /* 1219 * Flow control (both Rx and Tx) is enabled by a software 1220 * over-ride. 1221 */ 1222 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1223 break; 1224 default: 1225 DEBUGOUT("Flow control param set incorrectly\n"); 1226 ret_val = -E1000_ERR_CONFIG; 1227 goto out; 1228 } 1229 1230 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1231 mac->txcw = txcw; 1232 1233 out: 1234 return (ret_val); 1235 } 1236 1237 /* 1238 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1239 * @hw: pointer to the HW structure 1240 * 1241 * Sets the flow control high/low threshold (watermark) registers. If 1242 * flow control XON frame transmission is enabled, then set XON frame 1243 * transmission as well. 1244 */ 1245 s32 1246 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1247 { 1248 s32 ret_val = E1000_SUCCESS; 1249 u32 fcrtl = 0, fcrth = 0; 1250 1251 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1252 1253 /* 1254 * Set the flow control receive threshold registers. Normally, 1255 * these registers will be set to a default threshold that may be 1256 * adjusted later by the driver's runtime code. However, if the 1257 * ability to transmit pause frames is not enabled, then these 1258 * registers will be set to 0. 1259 */ 1260 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1261 /* 1262 * We need to set up the Receive Threshold high and low water 1263 * marks as well as (optionally) enabling the transmission of 1264 * XON frames. 1265 */ 1266 fcrtl = hw->fc.low_water; 1267 if (hw->fc.send_xon) 1268 fcrtl |= E1000_FCRTL_XONE; 1269 1270 fcrth = hw->fc.high_water; 1271 } 1272 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1273 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1274 1275 return (ret_val); 1276 } 1277 1278 /* 1279 * e1000_set_default_fc_generic - Set flow control default values 1280 * @hw: pointer to the HW structure 1281 * 1282 * Read the EEPROM for the default values for flow control and store the 1283 * values. 1284 */ 1285 s32 1286 e1000_set_default_fc_generic(struct e1000_hw *hw) 1287 { 1288 s32 ret_val = E1000_SUCCESS; 1289 u16 nvm_data; 1290 1291 DEBUGFUNC("e1000_set_default_fc_generic"); 1292 1293 /* 1294 * Read and store word 0x0F of the EEPROM. This word contains bits 1295 * that determine the hardware's default PAUSE (flow control) mode, 1296 * a bit that determines whether the HW defaults to enabling or 1297 * disabling auto-negotiation, and the direction of the 1298 * SW defined pins. If there is no SW over-ride of the flow 1299 * control setting, then the variable hw->fc will 1300 * be initialized based on a value in the EEPROM. 1301 */ 1302 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1303 1304 if (ret_val) { 1305 DEBUGOUT("NVM Read Error\n"); 1306 goto out; 1307 } 1308 1309 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1310 hw->fc.requested_mode = e1000_fc_none; 1311 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1312 NVM_WORD0F_ASM_DIR) 1313 hw->fc.requested_mode = e1000_fc_tx_pause; 1314 else 1315 hw->fc.requested_mode = e1000_fc_full; 1316 1317 out: 1318 return (ret_val); 1319 } 1320 1321 /* 1322 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1323 * @hw: pointer to the HW structure 1324 * 1325 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1326 * device control register to reflect the adapter settings. TFCE and RFCE 1327 * need to be explicitly set by software when a copper PHY is used because 1328 * autonegotiation is managed by the PHY rather than the MAC. Software must 1329 * also configure these bits when link is forced on a fiber connection. 1330 */ 1331 s32 1332 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1333 { 1334 u32 ctrl; 1335 s32 ret_val = E1000_SUCCESS; 1336 1337 DEBUGFUNC("e1000_force_mac_fc_generic"); 1338 1339 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1340 1341 /* 1342 * Because we didn't get link via the internal auto-negotiation 1343 * mechanism (we either forced link or we got link via PHY 1344 * auto-neg), we have to manually enable/disable transmit an 1345 * receive flow control. 1346 * 1347 * The "Case" statement below enables/disable flow control 1348 * according to the "hw->fc.current_mode" parameter. 1349 * 1350 * The possible values of the "fc" parameter are: 1351 * 0: Flow control is completely disabled 1352 * 1: Rx flow control is enabled (we can receive pause 1353 * frames but not send pause frames). 1354 * 2: Tx flow control is enabled (we can send pause frames 1355 * frames but we do not receive pause frames). 1356 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1357 * other: No other values should be possible at this point. 1358 */ 1359 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1360 1361 switch (hw->fc.current_mode) { 1362 case e1000_fc_none: 1363 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1364 break; 1365 case e1000_fc_rx_pause: 1366 ctrl &= (~E1000_CTRL_TFCE); 1367 ctrl |= E1000_CTRL_RFCE; 1368 break; 1369 case e1000_fc_tx_pause: 1370 ctrl &= (~E1000_CTRL_RFCE); 1371 ctrl |= E1000_CTRL_TFCE; 1372 break; 1373 case e1000_fc_full: 1374 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1375 break; 1376 default: 1377 DEBUGOUT("Flow control param set incorrectly\n"); 1378 ret_val = -E1000_ERR_CONFIG; 1379 goto out; 1380 } 1381 1382 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1383 1384 out: 1385 return (ret_val); 1386 } 1387 1388 /* 1389 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1390 * @hw: pointer to the HW structure 1391 * 1392 * Checks the status of auto-negotiation after link up to ensure that the 1393 * speed and duplex were not forced. If the link needed to be forced, then 1394 * flow control needs to be forced also. If auto-negotiation is enabled 1395 * and did not fail, then we configure flow control based on our link 1396 * partner. 1397 */ 1398 s32 1399 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1400 { 1401 struct e1000_mac_info *mac = &hw->mac; 1402 s32 ret_val = E1000_SUCCESS; 1403 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1404 u16 speed, duplex; 1405 1406 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1407 1408 /* 1409 * Check for the case where we have fiber media and auto-neg failed 1410 * so we had to force link. In this case, we need to force the 1411 * configuration of the MAC to match the "fc" parameter. 1412 */ 1413 if (mac->autoneg_failed) { 1414 if (hw->phy.media_type == e1000_media_type_fiber || 1415 hw->phy.media_type == e1000_media_type_internal_serdes) 1416 ret_val = e1000_force_mac_fc_generic(hw); 1417 } else { 1418 if (hw->phy.media_type == e1000_media_type_copper) 1419 ret_val = e1000_force_mac_fc_generic(hw); 1420 } 1421 1422 if (ret_val) { 1423 DEBUGOUT("Error forcing flow control settings\n"); 1424 goto out; 1425 } 1426 1427 /* 1428 * Check for the case where we have copper media and auto-neg is 1429 * enabled. In this case, we need to check and see if Auto-Neg 1430 * has completed, and if so, how the PHY and link partner has 1431 * flow control configured. 1432 */ 1433 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1434 /* 1435 * Read the MII Status Register and check to see if AutoNeg 1436 * has completed. We read this twice because this reg has 1437 * some "sticky" (latched) bits. 1438 */ 1439 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1440 if (ret_val) 1441 goto out; 1442 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1443 if (ret_val) 1444 goto out; 1445 1446 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1447 DEBUGOUT("Copper PHY and Auto Neg " 1448 "has not completed.\n"); 1449 goto out; 1450 } 1451 1452 /* 1453 * The AutoNeg process has completed, so we now need to 1454 * read both the Auto Negotiation Advertisement 1455 * Register (Address 4) and the Auto_Negotiation Base 1456 * Page Ability Register (Address 5) to determine how 1457 * flow control was negotiated. 1458 */ 1459 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1460 &mii_nway_adv_reg); 1461 if (ret_val) 1462 goto out; 1463 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1464 &mii_nway_lp_ability_reg); 1465 if (ret_val) 1466 goto out; 1467 1468 /* 1469 * Two bits in the Auto Negotiation Advertisement Register 1470 * (Address 4) and two bits in the Auto Negotiation Base 1471 * Page Ability Register (Address 5) determine flow control 1472 * for both the PHY and the link partner. The following 1473 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1474 * 1999, describes these PAUSE resolution bits and how flow 1475 * control is determined based upon these settings. 1476 * NOTE: DC = Don't Care 1477 * 1478 * LOCAL DEVICE | LINK PARTNER 1479 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1480 * ------|---------|-------|---------|-------------------- 1481 * 0 | 0 | DC | DC | e1000_fc_none 1482 * 0 | 1 | 0 | DC | e1000_fc_none 1483 * 0 | 1 | 1 | 0 | e1000_fc_none 1484 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1485 * 1 | 0 | 0 | DC | e1000_fc_none 1486 * 1 | DC | 1 | DC | e1000_fc_full 1487 * 1 | 1 | 0 | 0 | e1000_fc_none 1488 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1489 * 1490 * Are both PAUSE bits set to 1? If so, this implies 1491 * Symmetric Flow Control is enabled at both ends. The 1492 * ASM_DIR bits are irrelevant per the spec. 1493 * 1494 * For Symmetric Flow Control: 1495 * 1496 * LOCAL DEVICE | LINK PARTNER 1497 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1498 * ------|---------|-------|---------|-------------------- 1499 * 1 | DC | 1 | DC | E1000_fc_full 1500 * 1501 */ 1502 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1503 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1504 /* 1505 * Now we need to check if the user selected Rx ONLY 1506 * of pause frames. In this case, we had to advertise 1507 * FULL flow control because we could not advertise RX 1508 * ONLY. Hence, we must now check to see if we need to 1509 * turn OFF the TRANSMISSION of PAUSE frames. 1510 */ 1511 if (hw->fc.requested_mode == e1000_fc_full) { 1512 hw->fc.current_mode = e1000_fc_full; 1513 DEBUGOUT("Flow Control = FULL.\r\n"); 1514 } else { 1515 hw->fc.current_mode = e1000_fc_rx_pause; 1516 DEBUGOUT("Flow Control = " 1517 "RX PAUSE frames only.\r\n"); 1518 } 1519 } 1520 /* 1521 * For receiving PAUSE frames ONLY. 1522 * 1523 * LOCAL DEVICE | LINK PARTNER 1524 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1525 * ------|---------|-------|---------|-------------------- 1526 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1527 */ 1528 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1529 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1530 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1531 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1532 hw->fc.current_mode = e1000_fc_tx_pause; 1533 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1534 } 1535 /* 1536 * For transmitting PAUSE frames ONLY. 1537 * 1538 * LOCAL DEVICE | LINK PARTNER 1539 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1540 * ------|---------|-------|---------|-------------------- 1541 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1542 */ 1543 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1544 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1545 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1546 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1547 hw->fc.current_mode = e1000_fc_rx_pause; 1548 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1549 } else { 1550 /* 1551 * Per the IEEE spec, at this point flow control 1552 * should be disabled. 1553 */ 1554 hw->fc.current_mode = e1000_fc_none; 1555 DEBUGOUT("Flow Control = NONE.\r\n"); 1556 } 1557 1558 /* 1559 * Now we need to do one last check... If we auto- 1560 * negotiated to HALF DUPLEX, flow control should not be 1561 * enabled per IEEE 802.3 spec. 1562 */ 1563 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1564 if (ret_val) { 1565 DEBUGOUT("Error getting link speed and duplex\n"); 1566 goto out; 1567 } 1568 1569 if (duplex == HALF_DUPLEX) 1570 hw->fc.current_mode = e1000_fc_none; 1571 1572 /* 1573 * Now we call a subroutine to actually force the MAC 1574 * controller to use the correct flow control settings. 1575 */ 1576 ret_val = e1000_force_mac_fc_generic(hw); 1577 if (ret_val) { 1578 DEBUGOUT("Error forcing flow control settings\n"); 1579 goto out; 1580 } 1581 } 1582 1583 out: 1584 return (ret_val); 1585 } 1586 1587 /* 1588 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1589 * @hw: pointer to the HW structure 1590 * @speed: stores the current speed 1591 * @duplex: stores the current duplex 1592 * 1593 * Read the status register for the current speed/duplex and store the current 1594 * speed and duplex for copper connections. 1595 */ 1596 s32 1597 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1598 u16 *duplex) 1599 { 1600 u32 status; 1601 1602 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1603 1604 status = E1000_READ_REG(hw, E1000_STATUS); 1605 if (status & E1000_STATUS_SPEED_1000) { 1606 *speed = SPEED_1000; 1607 DEBUGOUT("1000 Mbs, "); 1608 } else if (status & E1000_STATUS_SPEED_100) { 1609 *speed = SPEED_100; 1610 DEBUGOUT("100 Mbs, "); 1611 } else { 1612 *speed = SPEED_10; 1613 DEBUGOUT("10 Mbs, "); 1614 } 1615 1616 if (status & E1000_STATUS_FD) { 1617 *duplex = FULL_DUPLEX; 1618 DEBUGOUT("Full Duplex\n"); 1619 } else { 1620 *duplex = HALF_DUPLEX; 1621 DEBUGOUT("Half Duplex\n"); 1622 } 1623 1624 return (E1000_SUCCESS); 1625 } 1626 1627 /* 1628 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1629 * @hw: pointer to the HW structure 1630 * @speed: stores the current speed 1631 * @duplex: stores the current duplex 1632 * 1633 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1634 * for fiber/serdes links. 1635 */ 1636 s32 1637 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1638 u16 *speed, u16 *duplex) 1639 { 1640 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1641 UNREFERENCED_1PARAMETER(hw); 1642 1643 *speed = SPEED_1000; 1644 *duplex = FULL_DUPLEX; 1645 1646 return (E1000_SUCCESS); 1647 } 1648 1649 /* 1650 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1651 * @hw: pointer to the HW structure 1652 * 1653 * Acquire the HW semaphore to access the PHY or NVM 1654 */ 1655 s32 1656 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1657 { 1658 u32 swsm; 1659 s32 ret_val = E1000_SUCCESS; 1660 s32 timeout = hw->nvm.word_size + 1; 1661 s32 i = 0; 1662 1663 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1664 1665 /* Get the SW semaphore */ 1666 while (i < timeout) { 1667 swsm = E1000_READ_REG(hw, E1000_SWSM); 1668 if (!(swsm & E1000_SWSM_SMBI)) 1669 break; 1670 1671 usec_delay(50); 1672 i++; 1673 } 1674 1675 if (i == timeout) { 1676 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1677 ret_val = -E1000_ERR_NVM; 1678 goto out; 1679 } 1680 1681 /* Get the FW semaphore. */ 1682 for (i = 0; i < timeout; i++) { 1683 swsm = E1000_READ_REG(hw, E1000_SWSM); 1684 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1685 1686 /* Semaphore acquired if bit latched */ 1687 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1688 break; 1689 1690 usec_delay(50); 1691 } 1692 1693 if (i == timeout) { 1694 /* Release semaphores */ 1695 e1000_put_hw_semaphore_generic(hw); 1696 DEBUGOUT("Driver can't access the NVM\n"); 1697 ret_val = -E1000_ERR_NVM; 1698 goto out; 1699 } 1700 1701 out: 1702 return (ret_val); 1703 } 1704 1705 /* 1706 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1707 * @hw: pointer to the HW structure 1708 * 1709 * Release hardware semaphore used to access the PHY or NVM 1710 */ 1711 void 1712 e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1713 { 1714 u32 swsm; 1715 1716 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1717 1718 swsm = E1000_READ_REG(hw, E1000_SWSM); 1719 1720 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1721 1722 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1723 } 1724 1725 /* 1726 * e1000_get_auto_rd_done_generic - Check for auto read completion 1727 * @hw: pointer to the HW structure 1728 * 1729 * Check EEPROM for Auto Read done bit. 1730 */ 1731 s32 1732 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1733 { 1734 s32 i = 0; 1735 s32 ret_val = E1000_SUCCESS; 1736 1737 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1738 1739 while (i < AUTO_READ_DONE_TIMEOUT) { 1740 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1741 break; 1742 msec_delay(1); 1743 i++; 1744 } 1745 1746 if (i == AUTO_READ_DONE_TIMEOUT) { 1747 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1748 ret_val = -E1000_ERR_RESET; 1749 goto out; 1750 } 1751 1752 out: 1753 return (ret_val); 1754 } 1755 1756 /* 1757 * e1000_valid_led_default_generic - Verify a valid default LED config 1758 * @hw: pointer to the HW structure 1759 * @data: pointer to the NVM (EEPROM) 1760 * 1761 * Read the EEPROM for the current default LED configuration. If the 1762 * LED configuration is not valid, set to a valid LED configuration. 1763 */ 1764 s32 1765 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1766 { 1767 s32 ret_val; 1768 1769 DEBUGFUNC("e1000_valid_led_default_generic"); 1770 1771 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1772 if (ret_val) { 1773 DEBUGOUT("NVM Read Error\n"); 1774 goto out; 1775 } 1776 1777 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1778 *data = ID_LED_DEFAULT; 1779 1780 out: 1781 return (ret_val); 1782 } 1783 1784 /* 1785 * e1000_id_led_init_generic - 1786 * @hw: pointer to the HW structure 1787 * 1788 */ 1789 s32 1790 e1000_id_led_init_generic(struct e1000_hw *hw) 1791 { 1792 struct e1000_mac_info *mac = &hw->mac; 1793 s32 ret_val; 1794 const u32 ledctl_mask = 0x000000FF; 1795 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1796 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1797 u16 data, i, temp; 1798 const u16 led_mask = 0x0F; 1799 1800 DEBUGFUNC("e1000_id_led_init_generic"); 1801 1802 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1803 if (ret_val) 1804 goto out; 1805 1806 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1807 mac->ledctl_mode1 = mac->ledctl_default; 1808 mac->ledctl_mode2 = mac->ledctl_default; 1809 1810 for (i = 0; i < 4; i++) { 1811 temp = (data >> (i << 2)) & led_mask; 1812 switch (temp) { 1813 case ID_LED_ON1_DEF2: 1814 case ID_LED_ON1_ON2: 1815 case ID_LED_ON1_OFF2: 1816 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1817 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1818 break; 1819 case ID_LED_OFF1_DEF2: 1820 case ID_LED_OFF1_ON2: 1821 case ID_LED_OFF1_OFF2: 1822 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1823 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1824 break; 1825 default: 1826 /* Do nothing */ 1827 break; 1828 } 1829 switch (temp) { 1830 case ID_LED_DEF1_ON2: 1831 case ID_LED_ON1_ON2: 1832 case ID_LED_OFF1_ON2: 1833 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1834 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1835 break; 1836 case ID_LED_DEF1_OFF2: 1837 case ID_LED_ON1_OFF2: 1838 case ID_LED_OFF1_OFF2: 1839 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1840 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1841 break; 1842 default: 1843 /* Do nothing */ 1844 break; 1845 } 1846 } 1847 1848 out: 1849 return (ret_val); 1850 } 1851 1852 /* 1853 * e1000_setup_led_generic - Configures SW controllable LED 1854 * @hw: pointer to the HW structure 1855 * 1856 * This prepares the SW controllable LED for use and saves the current state 1857 * of the LED so it can be later restored. 1858 */ 1859 s32 1860 e1000_setup_led_generic(struct e1000_hw *hw) 1861 { 1862 u32 ledctl; 1863 s32 ret_val = E1000_SUCCESS; 1864 1865 DEBUGFUNC("e1000_setup_led_generic"); 1866 1867 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1868 ret_val = -E1000_ERR_CONFIG; 1869 goto out; 1870 } 1871 1872 if (hw->phy.media_type == e1000_media_type_fiber) { 1873 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1874 hw->mac.ledctl_default = ledctl; 1875 /* Turn off LED0 */ 1876 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1877 E1000_LEDCTL_LED0_BLINK | 1878 E1000_LEDCTL_LED0_MODE_MASK); 1879 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1880 E1000_LEDCTL_LED0_MODE_SHIFT); 1881 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1882 } else if (hw->phy.media_type == e1000_media_type_copper) { 1883 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1884 } 1885 1886 out: 1887 return (ret_val); 1888 } 1889 1890 /* 1891 * e1000_cleanup_led_generic - Set LED config to default operation 1892 * @hw: pointer to the HW structure 1893 * 1894 * Remove the current LED configuration and set the LED configuration 1895 * to the default value, saved from the EEPROM. 1896 */ 1897 s32 1898 e1000_cleanup_led_generic(struct e1000_hw *hw) 1899 { 1900 s32 ret_val = E1000_SUCCESS; 1901 1902 DEBUGFUNC("e1000_cleanup_led_generic"); 1903 1904 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1905 ret_val = -E1000_ERR_CONFIG; 1906 goto out; 1907 } 1908 1909 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1910 1911 out: 1912 return (ret_val); 1913 } 1914 1915 /* 1916 * e1000_blink_led_generic - Blink LED 1917 * @hw: pointer to the HW structure 1918 * 1919 * Blink the LEDs which are set to be on. 1920 */ 1921 s32 1922 e1000_blink_led_generic(struct e1000_hw *hw) 1923 { 1924 u32 ledctl_blink = 0; 1925 u32 i; 1926 1927 DEBUGFUNC("e1000_blink_led_generic"); 1928 1929 if (hw->phy.media_type == e1000_media_type_fiber) { 1930 /* always blink LED0 for PCI-E fiber */ 1931 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1932 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1933 } else { 1934 /* 1935 * set the blink bit for each LED that's "on" (0x0E) 1936 * in ledctl_mode2 1937 */ 1938 ledctl_blink = hw->mac.ledctl_mode2; 1939 for (i = 0; i < 4; i++) 1940 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1941 E1000_LEDCTL_MODE_LED_ON) 1942 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1943 (i * 8)); 1944 } 1945 1946 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1947 1948 return (E1000_SUCCESS); 1949 } 1950 1951 /* 1952 * e1000_led_on_generic - Turn LED on 1953 * @hw: pointer to the HW structure 1954 * 1955 * Turn LED on. 1956 */ 1957 s32 1958 e1000_led_on_generic(struct e1000_hw *hw) 1959 { 1960 u32 ctrl; 1961 1962 DEBUGFUNC("e1000_led_on_generic"); 1963 1964 switch (hw->phy.media_type) { 1965 case e1000_media_type_fiber: 1966 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1967 ctrl &= ~E1000_CTRL_SWDPIN0; 1968 ctrl |= E1000_CTRL_SWDPIO0; 1969 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1970 break; 1971 case e1000_media_type_copper: 1972 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1973 break; 1974 default: 1975 break; 1976 } 1977 1978 return (E1000_SUCCESS); 1979 } 1980 1981 /* 1982 * e1000_led_off_generic - Turn LED off 1983 * @hw: pointer to the HW structure 1984 * 1985 * Turn LED off. 1986 */ 1987 s32 1988 e1000_led_off_generic(struct e1000_hw *hw) 1989 { 1990 u32 ctrl; 1991 1992 DEBUGFUNC("e1000_led_off_generic"); 1993 1994 switch (hw->phy.media_type) { 1995 case e1000_media_type_fiber: 1996 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1997 ctrl |= E1000_CTRL_SWDPIN0; 1998 ctrl |= E1000_CTRL_SWDPIO0; 1999 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2000 break; 2001 case e1000_media_type_copper: 2002 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2003 break; 2004 default: 2005 break; 2006 } 2007 2008 return (E1000_SUCCESS); 2009 } 2010 2011 /* 2012 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2013 * @hw: pointer to the HW structure 2014 * @no_snoop: bitmap of snoop events 2015 * 2016 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2017 */ 2018 void 2019 e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2020 { 2021 u32 gcr; 2022 2023 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2024 2025 if (hw->bus.type != e1000_bus_type_pci_express) 2026 return; 2027 2028 if (no_snoop) { 2029 gcr = E1000_READ_REG(hw, E1000_GCR); 2030 gcr &= ~(PCIE_NO_SNOOP_ALL); 2031 gcr |= no_snoop; 2032 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2033 } 2034 } 2035 2036 /* 2037 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2038 * @hw: pointer to the HW structure 2039 * 2040 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 2041 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2042 * the master requests to be disabled. 2043 * 2044 * Disables PCI-Express master access and verifies there are no pending 2045 * requests. 2046 */ 2047 s32 2048 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2049 { 2050 u32 ctrl; 2051 s32 timeout = MASTER_DISABLE_TIMEOUT; 2052 s32 ret_val = E1000_SUCCESS; 2053 2054 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2055 2056 if (hw->bus.type != e1000_bus_type_pci_express) 2057 goto out; 2058 2059 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2060 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2061 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2062 2063 while (timeout) { 2064 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2065 E1000_STATUS_GIO_MASTER_ENABLE)) 2066 break; 2067 usec_delay(100); 2068 timeout--; 2069 } 2070 2071 if (!timeout) { 2072 DEBUGOUT("Master requests are pending.\n"); 2073 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2074 goto out; 2075 } 2076 2077 out: 2078 return (ret_val); 2079 } 2080 2081 /* 2082 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2083 * @hw: pointer to the HW structure 2084 * 2085 * Reset the Adaptive Interframe Spacing throttle to default values. 2086 */ 2087 void 2088 e1000_reset_adaptive_generic(struct e1000_hw *hw) 2089 { 2090 struct e1000_mac_info *mac = &hw->mac; 2091 2092 DEBUGFUNC("e1000_reset_adaptive_generic"); 2093 2094 if (!mac->adaptive_ifs) { 2095 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2096 return; 2097 } 2098 2099 mac->current_ifs_val = 0; 2100 mac->ifs_min_val = IFS_MIN; 2101 mac->ifs_max_val = IFS_MAX; 2102 mac->ifs_step_size = IFS_STEP; 2103 mac->ifs_ratio = IFS_RATIO; 2104 2105 mac->in_ifs_mode = false; 2106 E1000_WRITE_REG(hw, E1000_AIT, 0); 2107 } 2108 2109 /* 2110 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2111 * @hw: pointer to the HW structure 2112 * 2113 * Update the Adaptive Interframe Spacing Throttle value based on the 2114 * time between transmitted packets and time between collisions. 2115 */ 2116 void 2117 e1000_update_adaptive_generic(struct e1000_hw *hw) 2118 { 2119 struct e1000_mac_info *mac = &hw->mac; 2120 2121 DEBUGFUNC("e1000_update_adaptive_generic"); 2122 2123 if (!mac->adaptive_ifs) { 2124 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2125 return; 2126 } 2127 2128 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2129 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2130 mac->in_ifs_mode = true; 2131 if (mac->current_ifs_val < mac->ifs_max_val) { 2132 if (!mac->current_ifs_val) 2133 mac->current_ifs_val = mac->ifs_min_val; 2134 else 2135 mac->current_ifs_val += 2136 mac->ifs_step_size; 2137 E1000_WRITE_REG(hw, E1000_AIT, 2138 mac->current_ifs_val); 2139 } 2140 } 2141 } else { 2142 if (mac->in_ifs_mode && 2143 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2144 mac->current_ifs_val = 0; 2145 mac->in_ifs_mode = false; 2146 E1000_WRITE_REG(hw, E1000_AIT, 0); 2147 } 2148 } 2149 } 2150 2151 /* 2152 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2153 * @hw: pointer to the HW structure 2154 * 2155 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2156 * set, which is forced to MDI mode only. 2157 */ 2158 s32 2159 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2160 { 2161 s32 ret_val = E1000_SUCCESS; 2162 2163 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2164 2165 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2166 DEBUGOUT("Invalid MDI setting detected\n"); 2167 hw->phy.mdix = 1; 2168 ret_val = -E1000_ERR_CONFIG; 2169 goto out; 2170 } 2171 2172 out: 2173 return (ret_val); 2174 } 2175 2176 /* 2177 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2178 * @hw: pointer to the HW structure 2179 * @reg: 32bit register offset such as E1000_SCTL 2180 * @offset: register offset to write to 2181 * @data: data to write at register offset 2182 * 2183 * Writes an address/data control type register. There are several of these 2184 * and they all have the format address << 8 | data and bit 31 is polled for 2185 * completion. 2186 */ 2187 s32 2188 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2189 u32 offset, u8 data) 2190 { 2191 u32 i, regvalue = 0; 2192 s32 ret_val = E1000_SUCCESS; 2193 2194 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2195 2196 /* Set up the address and data */ 2197 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2198 E1000_WRITE_REG(hw, reg, regvalue); 2199 2200 /* Poll the ready bit to see if the MDI read completed */ 2201 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2202 usec_delay(5); 2203 regvalue = E1000_READ_REG(hw, reg); 2204 if (regvalue & E1000_GEN_CTL_READY) 2205 break; 2206 } 2207 if (!(regvalue & E1000_GEN_CTL_READY)) { 2208 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2209 ret_val = -E1000_ERR_PHY; 2210 goto out; 2211 } 2212 2213 out: 2214 return (ret_val); 2215 } 2216