1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_api.h" 32 #include "igb_mac.h" 33 34 /* 35 * e1000_remove_device_generic - Free device specific structure 36 * @hw: pointer to the HW structure 37 * 38 * If a device specific structure was allocated, this function will 39 * free it. 40 */ 41 void 42 e1000_remove_device_generic(struct e1000_hw *hw) 43 { 44 DEBUGFUNC("e1000_remove_device_generic"); 45 46 /* Freeing the dev_spec member of e1000_hw structure */ 47 e1000_free_dev_spec_struct(hw); 48 } 49 50 /* 51 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 52 * @hw: pointer to the HW structure 53 * 54 * Determines and stores the system bus information for a particular 55 * network interface. The following bus information is determined and stored: 56 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 57 */ 58 s32 59 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 60 { 61 struct e1000_bus_info *bus = &hw->bus; 62 u32 status = E1000_READ_REG(hw, E1000_STATUS); 63 s32 ret_val = E1000_SUCCESS; 64 u16 pci_header_type; 65 66 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 67 68 /* PCI or PCI-X? */ 69 bus->type = (status & E1000_STATUS_PCIX_MODE) 70 ? e1000_bus_type_pcix : e1000_bus_type_pci; 71 72 /* Bus speed */ 73 if (bus->type == e1000_bus_type_pci) { 74 bus->speed = (status & E1000_STATUS_PCI66) 75 ? e1000_bus_speed_66 : e1000_bus_speed_33; 76 } else { 77 switch (status & E1000_STATUS_PCIX_SPEED) { 78 case E1000_STATUS_PCIX_SPEED_66: 79 bus->speed = e1000_bus_speed_66; 80 break; 81 case E1000_STATUS_PCIX_SPEED_100: 82 bus->speed = e1000_bus_speed_100; 83 break; 84 case E1000_STATUS_PCIX_SPEED_133: 85 bus->speed = e1000_bus_speed_133; 86 break; 87 default: 88 bus->speed = e1000_bus_speed_reserved; 89 break; 90 } 91 } 92 93 /* Bus width */ 94 bus->width = (status & E1000_STATUS_BUS64) 95 ? e1000_bus_width_64 : e1000_bus_width_32; 96 97 /* Which PCI(-X) function? */ 98 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 99 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) 100 bus->func = (status & E1000_STATUS_FUNC_MASK) 101 >> E1000_STATUS_FUNC_SHIFT; 102 else 103 bus->func = 0; 104 105 return (ret_val); 106 } 107 108 /* 109 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 110 * @hw: pointer to the HW structure 111 * 112 * Determines and stores the system bus information for a particular 113 * network interface. The following bus information is determined and stored: 114 * bus speed, bus width, type (PCIe), and PCIe function. 115 */ 116 s32 117 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 118 { 119 struct e1000_bus_info *bus = &hw->bus; 120 s32 ret_val; 121 u32 status; 122 u16 pcie_link_status, pci_header_type; 123 124 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 125 126 bus->type = e1000_bus_type_pci_express; 127 bus->speed = e1000_bus_speed_2500; 128 129 ret_val = e1000_read_pcie_cap_reg(hw, 130 PCIE_LINK_STATUS, &pcie_link_status); 131 if (ret_val) 132 bus->width = e1000_bus_width_unknown; 133 else 134 bus->width = (e1000_bus_width)((pcie_link_status & 135 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 136 137 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 138 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 139 status = E1000_READ_REG(hw, E1000_STATUS); 140 bus->func = (status & E1000_STATUS_FUNC_MASK) 141 >> E1000_STATUS_FUNC_SHIFT; 142 } else { 143 bus->func = 0; 144 } 145 146 return (E1000_SUCCESS); 147 } 148 149 /* 150 * e1000_clear_vfta_generic - Clear VLAN filter table 151 * @hw: pointer to the HW structure 152 * 153 * Clears the register array which contains the VLAN filter table by 154 * setting all the values to 0. 155 */ 156 void 157 e1000_clear_vfta_generic(struct e1000_hw *hw) 158 { 159 u32 offset; 160 161 DEBUGFUNC("e1000_clear_vfta_generic"); 162 163 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 164 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 165 E1000_WRITE_FLUSH(hw); 166 } 167 } 168 169 /* 170 * e1000_write_vfta_generic - Write value to VLAN filter table 171 * @hw: pointer to the HW structure 172 * @offset: register offset in VLAN filter table 173 * @value: register value written to VLAN filter table 174 * 175 * Writes value at the given offset in the register array which stores 176 * the VLAN filter table. 177 */ 178 void 179 e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 180 { 181 DEBUGFUNC("e1000_write_vfta_generic"); 182 183 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 184 E1000_WRITE_FLUSH(hw); 185 } 186 187 /* 188 * e1000_init_rx_addrs_generic - Initialize receive address's 189 * @hw: pointer to the HW structure 190 * @rar_count: receive address registers 191 * 192 * Setups the receive address registers by setting the base receive address 193 * register to the devices MAC address and clearing all the other receive 194 * address registers to 0. 195 */ 196 void 197 e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 198 { 199 u32 i; 200 201 DEBUGFUNC("e1000_init_rx_addrs_generic"); 202 203 /* Setup the receive address */ 204 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 205 206 e1000_rar_set_generic(hw, hw->mac.addr, 0); 207 208 /* Zero out the other (rar_entry_count - 1) receive addresses */ 209 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 210 for (i = 1; i < rar_count; i++) { 211 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); 212 E1000_WRITE_FLUSH(hw); 213 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); 214 E1000_WRITE_FLUSH(hw); 215 } 216 } 217 218 /* 219 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 220 * @hw: pointer to the HW structure 221 * 222 * Checks the nvm for an alternate MAC address. An alternate MAC address 223 * can be setup by pre-boot software and must be treated like a permanent 224 * address and must override the actual permanent MAC address. If an 225 * alternate MAC address is found it is saved in the hw struct and 226 * programmed into RAR0 and the function returns success, otherwise the 227 * function returns an error. 228 */ 229 s32 230 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 231 { 232 u32 i; 233 s32 ret_val = E1000_SUCCESS; 234 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 235 u8 alt_mac_addr[ETH_ADDR_LEN]; 236 237 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 238 239 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 240 &nvm_alt_mac_addr_offset); 241 if (ret_val) { 242 DEBUGOUT("NVM Read Error\n"); 243 goto out; 244 } 245 246 if (nvm_alt_mac_addr_offset == 0xFFFF) { 247 ret_val = -(E1000_NOT_IMPLEMENTED); 248 goto out; 249 } 250 251 if (hw->bus.func == E1000_FUNC_1) 252 nvm_alt_mac_addr_offset += ETH_ADDR_LEN / sizeof (u16); 253 254 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 255 offset = nvm_alt_mac_addr_offset + (i >> 1); 256 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); 257 if (ret_val) { 258 DEBUGOUT("NVM Read Error\n"); 259 goto out; 260 } 261 262 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 263 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 264 } 265 266 /* if multicast bit is set, the alternate address will not be used */ 267 if (alt_mac_addr[0] & 0x01) { 268 ret_val = -(E1000_NOT_IMPLEMENTED); 269 goto out; 270 } 271 272 for (i = 0; i < ETH_ADDR_LEN; i++) 273 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; 274 275 e1000_rar_set(hw, hw->mac.perm_addr, 0); 276 277 out: 278 return (ret_val); 279 } 280 281 /* 282 * e1000_rar_set_generic - Set receive address register 283 * @hw: pointer to the HW structure 284 * @addr: pointer to the receive address 285 * @index: receive address array register 286 * 287 * Sets the receive address array register at index to the address passed 288 * in by addr. 289 */ 290 void 291 e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 292 { 293 u32 rar_low, rar_high; 294 295 DEBUGFUNC("e1000_rar_set_generic"); 296 297 /* 298 * HW expects these in little endian so we reverse the byte order 299 * from network order (big endian) to little endian 300 */ 301 rar_low = ((u32) addr[0] | 302 ((u32) addr[1] << 8) | 303 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 304 305 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 306 307 /* If MAC address zero, no need to set the AV bit */ 308 if (rar_low || rar_high) { 309 if (!hw->mac.disable_av) 310 rar_high |= E1000_RAH_AV; 311 } 312 313 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 314 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 315 } 316 317 /* 318 * e1000_mta_set_generic - Set multicast filter table address 319 * @hw: pointer to the HW structure 320 * @hash_value: determines the MTA register and bit to set 321 * 322 * The multicast table address is a register array of 32-bit registers. 323 * The hash_value is used to determine what register the bit is in, the 324 * current value is read, the new bit is OR'd in and the new value is 325 * written back into the register. 326 */ 327 void 328 e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 329 { 330 u32 hash_bit, hash_reg, mta; 331 332 DEBUGFUNC("e1000_mta_set_generic"); 333 /* 334 * The MTA is a register array of 32-bit registers. It is 335 * treated like an array of (32*mta_reg_count) bits. We want to 336 * set bit BitArray[hash_value]. So we figure out what register 337 * the bit is in, read it, OR in the new bit, then write 338 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 339 * mask to bits 31:5 of the hash value which gives us the 340 * register we're modifying. The hash bit within that register 341 * is determined by the lower 5 bits of the hash value. 342 */ 343 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 344 hash_bit = hash_value & 0x1F; 345 346 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 347 348 mta |= (1 << hash_bit); 349 350 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 351 E1000_WRITE_FLUSH(hw); 352 } 353 354 /* 355 * e1000_update_mc_addr_list_generic - Update Multicast addresses 356 * @hw: pointer to the HW structure 357 * @mc_addr_list: array of multicast addresses to program 358 * @mc_addr_count: number of multicast addresses to program 359 * @rar_used_count: the first RAR register free to program 360 * @rar_count: total number of supported Receive Address Registers 361 * 362 * Updates the Receive Address Registers and Multicast Table Array. 363 * The caller must have a packed mc_addr_list of multicast addresses. 364 * The parameter rar_count will usually be hw->mac.rar_entry_count 365 * unless there are workarounds that change this. 366 */ 367 void 368 e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 369 u8 *mc_addr_list, u32 mc_addr_count, 370 u32 rar_used_count, u32 rar_count) 371 { 372 u32 hash_value; 373 u32 i; 374 375 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 376 377 /* 378 * Load the first set of multicast addresses into the exact 379 * filters (RAR). If there are not enough to fill the RAR 380 * array, clear the filters. 381 */ 382 for (i = rar_used_count; i < rar_count; i++) { 383 if (mc_addr_count) { 384 e1000_rar_set(hw, mc_addr_list, i); 385 mc_addr_count--; 386 mc_addr_list += ETH_ADDR_LEN; 387 } else { 388 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); 389 E1000_WRITE_FLUSH(hw); 390 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); 391 E1000_WRITE_FLUSH(hw); 392 } 393 } 394 395 /* Clear the old settings from the MTA */ 396 DEBUGOUT("Clearing MTA\n"); 397 for (i = 0; i < hw->mac.mta_reg_count; i++) { 398 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 399 E1000_WRITE_FLUSH(hw); 400 } 401 402 /* Load any remaining multicast addresses into the hash table. */ 403 for (; mc_addr_count > 0; mc_addr_count--) { 404 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 405 DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 406 e1000_mta_set(hw, hash_value); 407 mc_addr_list += ETH_ADDR_LEN; 408 } 409 } 410 411 /* 412 * e1000_hash_mc_addr_generic - Generate a multicast hash value 413 * @hw: pointer to the HW structure 414 * @mc_addr: pointer to a multicast address 415 * 416 * Generates a multicast address hash value which is used to determine 417 * the multicast filter table array address and new table value. See 418 * e1000_mta_set_generic() 419 */ 420 u32 421 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 422 { 423 u32 hash_value, hash_mask; 424 u8 bit_shift = 0; 425 426 DEBUGFUNC("e1000_hash_mc_addr_generic"); 427 428 /* Register count multiplied by bits per register */ 429 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 430 431 /* 432 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 433 * where 0xFF would still fall within the hash mask. 434 */ 435 while (hash_mask >> bit_shift != 0xFF) 436 bit_shift++; 437 438 /* 439 * The portion of the address that is used for the hash table 440 * is determined by the mc_filter_type setting. 441 * The algorithm is such that there is a total of 8 bits of shifting. 442 * The bit_shift for a mc_filter_type of 0 represents the number of 443 * left-shifts where the MSB of mc_addr[5] would still fall within 444 * the hash_mask. Case 0 does this exactly. Since there are a total 445 * of 8 bits of shifting, then mc_addr[4] will shift right the 446 * remaining number of bits. Thus 8 - bit_shift. The rest of the 447 * cases are a variation of this algorithm...essentially raising the 448 * number of bits to shift mc_addr[5] left, while still keeping the 449 * 8-bit shifting total. 450 * 451 * For example, given the following Destination MAC Address and an 452 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 453 * we can see that the bit_shift for case 0 is 4. These are the hash 454 * values resulting from each mc_filter_type... 455 * [0] [1] [2] [3] [4] [5] 456 * 01 AA 00 12 34 56 457 * LSB MSB 458 * 459 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 460 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 461 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 462 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 463 */ 464 switch (hw->mac.mc_filter_type) { 465 default: 466 case 0: 467 break; 468 case 1: 469 bit_shift += 1; 470 break; 471 case 2: 472 bit_shift += 2; 473 break; 474 case 3: 475 bit_shift += 4; 476 break; 477 } 478 479 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 480 (((u16) mc_addr[5]) << bit_shift))); 481 482 return (hash_value); 483 } 484 485 /* 486 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 487 * @hw: pointer to the HW structure 488 * 489 * In certain situations, a system BIOS may report that the PCIx maximum 490 * memory read byte count (MMRBC) value is higher than than the actual 491 * value. We check the PCIx command regsiter with the current PCIx status 492 * regsiter. 493 */ 494 void 495 e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 496 { 497 u16 cmd_mmrbc; 498 u16 pcix_cmd; 499 u16 pcix_stat_hi_word; 500 u16 stat_mmrbc; 501 502 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 503 504 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 505 if (hw->bus.type != e1000_bus_type_pcix) 506 return; 507 508 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 509 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 510 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 511 PCIX_COMMAND_MMRBC_SHIFT; 512 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 513 PCIX_STATUS_HI_MMRBC_SHIFT; 514 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 515 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 516 if (cmd_mmrbc > stat_mmrbc) { 517 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 518 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 519 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 520 } 521 } 522 523 /* 524 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 525 * @hw: pointer to the HW structure 526 * 527 * Clears the base hardware counters by reading the counter registers. 528 */ 529 void 530 e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 531 { 532 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 533 534 (void) E1000_READ_REG(hw, E1000_CRCERRS); 535 (void) E1000_READ_REG(hw, E1000_SYMERRS); 536 (void) E1000_READ_REG(hw, E1000_MPC); 537 (void) E1000_READ_REG(hw, E1000_SCC); 538 (void) E1000_READ_REG(hw, E1000_ECOL); 539 (void) E1000_READ_REG(hw, E1000_MCC); 540 (void) E1000_READ_REG(hw, E1000_LATECOL); 541 (void) E1000_READ_REG(hw, E1000_COLC); 542 (void) E1000_READ_REG(hw, E1000_DC); 543 (void) E1000_READ_REG(hw, E1000_SEC); 544 (void) E1000_READ_REG(hw, E1000_RLEC); 545 (void) E1000_READ_REG(hw, E1000_XONRXC); 546 (void) E1000_READ_REG(hw, E1000_XONTXC); 547 (void) E1000_READ_REG(hw, E1000_XOFFRXC); 548 (void) E1000_READ_REG(hw, E1000_XOFFTXC); 549 (void) E1000_READ_REG(hw, E1000_FCRUC); 550 (void) E1000_READ_REG(hw, E1000_GPRC); 551 (void) E1000_READ_REG(hw, E1000_BPRC); 552 (void) E1000_READ_REG(hw, E1000_MPRC); 553 (void) E1000_READ_REG(hw, E1000_GPTC); 554 (void) E1000_READ_REG(hw, E1000_GORCL); 555 (void) E1000_READ_REG(hw, E1000_GORCH); 556 (void) E1000_READ_REG(hw, E1000_GOTCL); 557 (void) E1000_READ_REG(hw, E1000_GOTCH); 558 (void) E1000_READ_REG(hw, E1000_RNBC); 559 (void) E1000_READ_REG(hw, E1000_RUC); 560 (void) E1000_READ_REG(hw, E1000_RFC); 561 (void) E1000_READ_REG(hw, E1000_ROC); 562 (void) E1000_READ_REG(hw, E1000_RJC); 563 (void) E1000_READ_REG(hw, E1000_TORL); 564 (void) E1000_READ_REG(hw, E1000_TORH); 565 (void) E1000_READ_REG(hw, E1000_TOTL); 566 (void) E1000_READ_REG(hw, E1000_TOTH); 567 (void) E1000_READ_REG(hw, E1000_TPR); 568 (void) E1000_READ_REG(hw, E1000_TPT); 569 (void) E1000_READ_REG(hw, E1000_MPTC); 570 (void) E1000_READ_REG(hw, E1000_BPTC); 571 } 572 573 /* 574 * e1000_check_for_copper_link_generic - Check for link (Copper) 575 * @hw: pointer to the HW structure 576 * 577 * Checks to see of the link status of the hardware has changed. If a 578 * change in link status has been detected, then we read the PHY registers 579 * to get the current speed/duplex if link exists. 580 */ 581 s32 582 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 583 { 584 struct e1000_mac_info *mac = &hw->mac; 585 s32 ret_val; 586 bool link; 587 588 DEBUGFUNC("e1000_check_for_copper_link"); 589 590 /* 591 * We only want to go out to the PHY registers to see if Auto-Neg 592 * has completed and/or if our link status has changed. The 593 * get_link_status flag is set upon receiving a Link Status 594 * Change or Rx Sequence Error interrupt. 595 */ 596 if (!mac->get_link_status) { 597 ret_val = E1000_SUCCESS; 598 goto out; 599 } 600 601 /* 602 * First we want to see if the MII Status Register reports 603 * link. If so, then we want to get the current speed/duplex 604 * of the PHY. 605 */ 606 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 607 if (ret_val) 608 goto out; 609 610 if (!link) 611 goto out; /* No link detected */ 612 613 mac->get_link_status = FALSE; 614 615 /* 616 * Check if there was DownShift, must be checked 617 * immediately after link-up 618 */ 619 (void) e1000_check_downshift_generic(hw); 620 621 /* 622 * If we are forcing speed/duplex, then we simply return since 623 * we have already determined whether we have link or not. 624 */ 625 if (!mac->autoneg) { 626 ret_val = -E1000_ERR_CONFIG; 627 goto out; 628 } 629 630 /* 631 * Auto-Neg is enabled. Auto Speed Detection takes care 632 * of MAC speed/duplex configuration. So we only need to 633 * configure Collision Distance in the MAC. 634 */ 635 e1000_config_collision_dist_generic(hw); 636 637 /* 638 * Configure Flow Control now that Auto-Neg has completed. 639 * First, we need to restore the desired flow control 640 * settings because we may have had to re-autoneg with a 641 * different link partner. 642 */ 643 ret_val = e1000_config_fc_after_link_up_generic(hw); 644 if (ret_val) { 645 DEBUGOUT("Error configuring flow control\n"); 646 } 647 648 out: 649 return (ret_val); 650 } 651 652 /* 653 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 654 * @hw: pointer to the HW structure 655 * 656 * Checks for link up on the hardware. If link is not up and we have 657 * a signal, then we need to force link up. 658 */ 659 s32 660 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 661 { 662 struct e1000_mac_info *mac = &hw->mac; 663 u32 rxcw; 664 u32 ctrl; 665 u32 status; 666 s32 ret_val = E1000_SUCCESS; 667 668 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 669 670 ctrl = E1000_READ_REG(hw, E1000_CTRL); 671 status = E1000_READ_REG(hw, E1000_STATUS); 672 rxcw = E1000_READ_REG(hw, E1000_RXCW); 673 674 /* 675 * If we don't have link (auto-negotiation failed or link partner 676 * cannot auto-negotiate), the cable is plugged in (we have signal), 677 * and our link partner is not trying to auto-negotiate with us (we 678 * are receiving idles or data), we need to force link up. We also 679 * need to give auto-negotiation time to complete, in case the cable 680 * was just plugged in. The autoneg_failed flag does this. 681 */ 682 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 683 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 684 (!(rxcw & E1000_RXCW_C))) { 685 if (mac->autoneg_failed == 0) { 686 mac->autoneg_failed = 1; 687 goto out; 688 } 689 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 690 691 /* Disable auto-negotiation in the TXCW register */ 692 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 693 694 /* Force link-up and also force full-duplex. */ 695 ctrl = E1000_READ_REG(hw, E1000_CTRL); 696 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 697 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 698 699 /* Configure Flow Control after forcing link up. */ 700 ret_val = e1000_config_fc_after_link_up_generic(hw); 701 if (ret_val) { 702 DEBUGOUT("Error configuring flow control\n"); 703 goto out; 704 } 705 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 706 /* 707 * If we are forcing link and we are receiving /C/ ordered 708 * sets, re-enable auto-negotiation in the TXCW register 709 * and disable forced link in the Device Control register 710 * in an attempt to auto-negotiate with our link partner. 711 */ 712 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 713 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 714 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 715 716 mac->serdes_has_link = TRUE; 717 } 718 719 out: 720 return (ret_val); 721 } 722 723 /* 724 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 725 * @hw: pointer to the HW structure 726 * 727 * Checks for link up on the hardware. If link is not up and we have 728 * a signal, then we need to force link up. 729 */ 730 s32 731 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 732 { 733 struct e1000_mac_info *mac = &hw->mac; 734 u32 rxcw; 735 u32 ctrl; 736 u32 status; 737 s32 ret_val = E1000_SUCCESS; 738 739 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 740 741 ctrl = E1000_READ_REG(hw, E1000_CTRL); 742 status = E1000_READ_REG(hw, E1000_STATUS); 743 rxcw = E1000_READ_REG(hw, E1000_RXCW); 744 745 /* 746 * If we don't have link (auto-negotiation failed or link partner 747 * cannot auto-negotiate), and our link partner is not trying to 748 * auto-negotiate with us (we are receiving idles or data), 749 * we need to force link up. We also need to give auto-negotiation 750 * time to complete. 751 */ 752 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 753 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 754 if (mac->autoneg_failed == 0) { 755 mac->autoneg_failed = 1; 756 goto out; 757 } 758 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 759 760 /* Disable auto-negotiation in the TXCW register */ 761 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 762 763 /* Force link-up and also force full-duplex. */ 764 ctrl = E1000_READ_REG(hw, E1000_CTRL); 765 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 766 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 767 768 /* Configure Flow Control after forcing link up. */ 769 ret_val = e1000_config_fc_after_link_up_generic(hw); 770 if (ret_val) { 771 DEBUGOUT("Error configuring flow control\n"); 772 goto out; 773 } 774 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 775 /* 776 * If we are forcing link and we are receiving /C/ ordered 777 * sets, re-enable auto-negotiation in the TXCW register 778 * and disable forced link in the Device Control register 779 * in an attempt to auto-negotiate with our link partner. 780 */ 781 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 782 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 783 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 784 785 mac->serdes_has_link = TRUE; 786 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 787 /* 788 * If we force link for non-auto-negotiation switch, check 789 * link status based on MAC synchronization for internal 790 * serdes media type. 791 */ 792 /* SYNCH bit and IV bit are sticky. */ 793 usec_delay(10); 794 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) { 795 if (!(rxcw & E1000_RXCW_IV)) { 796 mac->serdes_has_link = TRUE; 797 DEBUGOUT("SERDES: Link is up.\n"); 798 } 799 } else { 800 mac->serdes_has_link = FALSE; 801 DEBUGOUT("SERDES: Link is down.\n"); 802 } 803 } 804 805 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 806 status = E1000_READ_REG(hw, E1000_STATUS); 807 mac->serdes_has_link = (status & E1000_STATUS_LU) 808 ? TRUE : FALSE; 809 } 810 811 out: 812 return (ret_val); 813 } 814 815 /* 816 * e1000_setup_link_generic - Setup flow control and link settings 817 * @hw: pointer to the HW structure 818 * 819 * Determines which flow control settings to use, then configures flow 820 * control. Calls the appropriate media-specific link configuration 821 * function. Assuming the adapter has a valid link partner, a valid link 822 * should be established. Assumes the hardware has previously been reset 823 * and the transmitter and receiver are not enabled. 824 */ 825 s32 826 e1000_setup_link_generic(struct e1000_hw *hw) 827 { 828 struct e1000_functions *func = &hw->func; 829 s32 ret_val = E1000_SUCCESS; 830 831 DEBUGFUNC("e1000_setup_link_generic"); 832 833 /* 834 * In the case of the phy reset being blocked, we already have a link. 835 * We do not need to set it up again. 836 */ 837 if (e1000_check_reset_block(hw)) 838 goto out; 839 840 /* 841 * If flow control is set to default, set flow control based on 842 * the EEPROM flow control settings. 843 */ 844 if (hw->fc.type == e1000_fc_default) { 845 ret_val = e1000_set_default_fc_generic(hw); 846 if (ret_val) 847 goto out; 848 } 849 850 /* 851 * We want to save off the original Flow Control configuration just 852 * in case we get disconnected and then reconnected into a different 853 * hub or switch with different Flow Control capabilities. 854 */ 855 hw->fc.original_type = hw->fc.type; 856 857 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 858 859 /* Call the necessary media_type subroutine to configure the link. */ 860 ret_val = func->setup_physical_interface(hw); 861 if (ret_val) 862 goto out; 863 864 /* 865 * Initialize the flow control address, type, and PAUSE timer 866 * registers to their default values. This is done even if flow 867 * control is disabled, because it does not hurt anything to 868 * initialize these registers. 869 */ 870 DEBUGOUT("Initializing the Flow Control address,type and timer regs\n"); 871 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 872 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 873 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 874 875 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 876 877 ret_val = e1000_set_fc_watermarks_generic(hw); 878 879 out: 880 return (ret_val); 881 } 882 883 /* 884 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 885 * @hw: pointer to the HW structure 886 * 887 * Configures collision distance and flow control for fiber and serdes 888 * links. Upon successful setup, poll for link. 889 */ 890 s32 891 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 892 { 893 u32 ctrl; 894 s32 ret_val = E1000_SUCCESS; 895 896 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 897 898 ctrl = E1000_READ_REG(hw, E1000_CTRL); 899 900 /* Take the link out of reset */ 901 ctrl &= ~E1000_CTRL_LRST; 902 903 e1000_config_collision_dist_generic(hw); 904 905 ret_val = e1000_commit_fc_settings_generic(hw); 906 if (ret_val) 907 goto out; 908 909 /* 910 * Since auto-negotiation is enabled, take the link out of reset (the 911 * link will be in reset, because we previously reset the chip). This 912 * will restart auto-negotiation. If auto-negotiation is successful 913 * then the link-up status bit will be set and the flow control enable 914 * bits (RFCE and TFCE) will be set according to their negotiated value. 915 */ 916 DEBUGOUT("Auto-negotiation enabled\n"); 917 918 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 919 E1000_WRITE_FLUSH(hw); 920 msec_delay(1); 921 922 /* 923 * For these adapters, the SW defineable pin 1 is set when the optics 924 * detect a signal. If we have a signal, then poll for a "Link-Up" 925 * indication. 926 */ 927 if (hw->phy.media_type == e1000_media_type_internal_serdes || 928 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 929 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 930 } else { 931 DEBUGOUT("No signal detected\n"); 932 } 933 934 out: 935 return (ret_val); 936 } 937 938 /* 939 * e1000_config_collision_dist_generic - Configure collision distance 940 * @hw: pointer to the HW structure 941 * 942 * Configures the collision distance to the default value and is used 943 * during link setup. Currently no func pointer exists and all 944 * implementations are handled in the generic version of this function. 945 */ 946 void 947 e1000_config_collision_dist_generic(struct e1000_hw *hw) 948 { 949 u32 tctl; 950 951 DEBUGFUNC("e1000_config_collision_dist_generic"); 952 953 tctl = E1000_READ_REG(hw, E1000_TCTL); 954 955 tctl &= ~E1000_TCTL_COLD; 956 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 957 958 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 959 E1000_WRITE_FLUSH(hw); 960 } 961 962 /* 963 * e1000_poll_fiber_serdes_link_generic - Poll for link up 964 * @hw: pointer to the HW structure 965 * 966 * Polls for link up by reading the status register, if link fails to come 967 * up with auto-negotiation, then the link is forced if a signal is detected. 968 */ 969 s32 970 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 971 { 972 struct e1000_mac_info *mac = &hw->mac; 973 u32 i, status; 974 s32 ret_val = E1000_SUCCESS; 975 976 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 977 978 /* 979 * If we have a signal (the cable is plugged in, or assumed true for 980 * serdes media) then poll for a "Link-Up" indication in the Device 981 * Status Register. Time-out if a link isn't seen in 500 milliseconds 982 * seconds (Auto-negotiation should complete in less than 500 983 * milliseconds even if the other end is doing it in SW). 984 */ 985 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 986 msec_delay(10); 987 status = E1000_READ_REG(hw, E1000_STATUS); 988 if (status & E1000_STATUS_LU) 989 break; 990 } 991 if (i == FIBER_LINK_UP_LIMIT) { 992 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 993 mac->autoneg_failed = 1; 994 /* 995 * AutoNeg failed to achieve a link, so we'll call 996 * mac->check_for_link. This routine will force the 997 * link up if we detect a signal. This will allow us to 998 * communicate with non-autonegotiating link partners. 999 */ 1000 ret_val = e1000_check_for_link(hw); 1001 if (ret_val) { 1002 DEBUGOUT("Error while checking for link\n"); 1003 goto out; 1004 } 1005 mac->autoneg_failed = 0; 1006 } else { 1007 mac->autoneg_failed = 0; 1008 DEBUGOUT("Valid Link Found\n"); 1009 } 1010 1011 out: 1012 return (ret_val); 1013 } 1014 1015 /* 1016 * e1000_commit_fc_settings_generic - Configure flow control 1017 * @hw: pointer to the HW structure 1018 * 1019 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1020 * base on the flow control settings in e1000_mac_info. 1021 */ 1022 s32 1023 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1024 { 1025 struct e1000_mac_info *mac = &hw->mac; 1026 u32 txcw; 1027 s32 ret_val = E1000_SUCCESS; 1028 1029 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1030 1031 /* 1032 * Check for a software override of the flow control settings, and 1033 * setup the device accordingly. If auto-negotiation is enabled, then 1034 * software will have to set the "PAUSE" bits to the correct value in 1035 * the Transmit Config Word Register (TXCW) and re-start auto- 1036 * negotiation. However, if auto-negotiation is disabled, then 1037 * software will have to manually configure the two flow control enable 1038 * bits in the CTRL register. 1039 * 1040 * The possible values of the "fc" parameter are: 1041 * 0: Flow control is completely disabled 1042 * 1: Rx flow control is enabled (we can receive pause frames, 1043 * but not send pause frames). 1044 * 2: Tx flow control is enabled (we can send pause frames but we 1045 * do not support receiving pause frames). 1046 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1047 */ 1048 switch (hw->fc.type) { 1049 case e1000_fc_none: 1050 /* Flow control completely disabled by a software over-ride. */ 1051 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1052 break; 1053 case e1000_fc_rx_pause: 1054 /* 1055 * Rx Flow control is enabled and Tx Flow control is disabled 1056 * by a software over-ride. Since there really isn't a way to 1057 * advertise that we are capable of Rx Pause ONLY, we will 1058 * advertise that we support both symmetric and asymmetric RX 1059 * PAUSE. Later, we will disable the adapter's ability to send 1060 * PAUSE frames. 1061 */ 1062 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1063 break; 1064 case e1000_fc_tx_pause: 1065 /* 1066 * Tx Flow control is enabled, and Rx Flow control is disabled, 1067 * by a software over-ride. 1068 */ 1069 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1070 break; 1071 case e1000_fc_full: 1072 /* 1073 * Flow control (both Rx and Tx) is enabled by a software 1074 * over-ride. 1075 */ 1076 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1077 break; 1078 default: 1079 DEBUGOUT("Flow control param set incorrectly\n"); 1080 ret_val = -E1000_ERR_CONFIG; 1081 goto out; 1082 } 1083 1084 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1085 mac->txcw = txcw; 1086 1087 out: 1088 return (ret_val); 1089 } 1090 1091 /* 1092 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1093 * @hw: pointer to the HW structure 1094 * 1095 * Sets the flow control high/low threshold (watermark) registers. If 1096 * flow control XON frame transmission is enabled, then set XON frame 1097 * tansmission as well. 1098 */ 1099 s32 1100 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1101 { 1102 s32 ret_val = E1000_SUCCESS; 1103 u32 fcrtl = 0, fcrth = 0; 1104 1105 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1106 1107 /* 1108 * Set the flow control receive threshold registers. Normally, 1109 * these registers will be set to a default threshold that may be 1110 * adjusted later by the driver's runtime code. However, if the 1111 * ability to transmit pause frames is not enabled, then these 1112 * registers will be set to 0. 1113 */ 1114 if (hw->fc.type & e1000_fc_tx_pause) { 1115 /* 1116 * We need to set up the Receive Threshold high and low water 1117 * marks as well as (optionally) enabling the transmission of 1118 * XON frames. 1119 */ 1120 fcrtl = hw->fc.low_water; 1121 if (hw->fc.send_xon) 1122 fcrtl |= E1000_FCRTL_XONE; 1123 1124 fcrth = hw->fc.high_water; 1125 } 1126 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1127 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1128 1129 return (ret_val); 1130 } 1131 1132 /* 1133 * e1000_set_default_fc_generic - Set flow control default values 1134 * @hw: pointer to the HW structure 1135 * 1136 * Read the EEPROM for the default values for flow control and store the 1137 * values. 1138 */ 1139 s32 1140 e1000_set_default_fc_generic(struct e1000_hw *hw) 1141 { 1142 s32 ret_val = E1000_SUCCESS; 1143 u16 nvm_data; 1144 1145 DEBUGFUNC("e1000_set_default_fc_generic"); 1146 1147 /* 1148 * Read and store word 0x0F of the EEPROM. This word contains bits 1149 * that determine the hardware's default PAUSE (flow control) mode, 1150 * a bit that determines whether the HW defaults to enabling or 1151 * disabling auto-negotiation, and the direction of the 1152 * SW defined pins. If there is no SW over-ride of the flow 1153 * control setting, then the variable hw->fc will 1154 * be initialized based on a value in the EEPROM. 1155 */ 1156 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1157 1158 if (ret_val) { 1159 DEBUGOUT("NVM Read Error\n"); 1160 goto out; 1161 } 1162 1163 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1164 hw->fc.type = e1000_fc_none; 1165 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1166 NVM_WORD0F_ASM_DIR) 1167 hw->fc.type = e1000_fc_tx_pause; 1168 else 1169 hw->fc.type = e1000_fc_full; 1170 1171 out: 1172 return (ret_val); 1173 } 1174 1175 /* 1176 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1177 * @hw: pointer to the HW structure 1178 * 1179 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1180 * device control register to reflect the adapter settings. TFCE and RFCE 1181 * need to be explicitly set by software when a copper PHY is used because 1182 * autonegotiation is managed by the PHY rather than the MAC. Software must 1183 * also configure these bits when link is forced on a fiber connection. 1184 */ 1185 s32 1186 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1187 { 1188 u32 ctrl; 1189 s32 ret_val = E1000_SUCCESS; 1190 1191 DEBUGFUNC("e1000_force_mac_fc_generic"); 1192 1193 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1194 1195 /* 1196 * Because we didn't get link via the internal auto-negotiation 1197 * mechanism (we either forced link or we got link via PHY 1198 * auto-neg), we have to manually enable/disable transmit an 1199 * receive flow control. 1200 * 1201 * The "Case" statement below enables/disable flow control 1202 * according to the "hw->fc.type" parameter. 1203 * 1204 * The possible values of the "fc" parameter are: 1205 * 0: Flow control is completely disabled 1206 * 1: Rx flow control is enabled (we can receive pause 1207 * frames but not send pause frames). 1208 * 2: Tx flow control is enabled (we can send pause frames 1209 * frames but we do not receive pause frames). 1210 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1211 * other: No other values should be possible at this point. 1212 */ 1213 DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type); 1214 1215 switch (hw->fc.type) { 1216 case e1000_fc_none: 1217 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1218 break; 1219 case e1000_fc_rx_pause: 1220 ctrl &= (~E1000_CTRL_TFCE); 1221 ctrl |= E1000_CTRL_RFCE; 1222 break; 1223 case e1000_fc_tx_pause: 1224 ctrl &= (~E1000_CTRL_RFCE); 1225 ctrl |= E1000_CTRL_TFCE; 1226 break; 1227 case e1000_fc_full: 1228 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1229 break; 1230 default: 1231 DEBUGOUT("Flow control param set incorrectly\n"); 1232 ret_val = -E1000_ERR_CONFIG; 1233 goto out; 1234 } 1235 1236 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1237 1238 out: 1239 return (ret_val); 1240 } 1241 1242 /* 1243 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1244 * @hw: pointer to the HW structure 1245 * 1246 * Checks the status of auto-negotiation after link up to ensure that the 1247 * speed and duplex were not forced. If the link needed to be forced, then 1248 * flow control needs to be forced also. If auto-negotiation is enabled 1249 * and did not fail, then we configure flow control based on our link 1250 * partner. 1251 */ 1252 s32 1253 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1254 { 1255 struct e1000_mac_info *mac = &hw->mac; 1256 s32 ret_val = E1000_SUCCESS; 1257 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1258 u16 speed, duplex; 1259 1260 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1261 1262 /* 1263 * Check for the case where we have fiber media and auto-neg failed 1264 * so we had to force link. In this case, we need to force the 1265 * configuration of the MAC to match the "fc" parameter. 1266 */ 1267 if (mac->autoneg_failed) { 1268 if (hw->phy.media_type == e1000_media_type_fiber || 1269 hw->phy.media_type == e1000_media_type_internal_serdes) 1270 ret_val = e1000_force_mac_fc_generic(hw); 1271 } else { 1272 if (hw->phy.media_type == e1000_media_type_copper) 1273 ret_val = e1000_force_mac_fc_generic(hw); 1274 } 1275 1276 if (ret_val) { 1277 DEBUGOUT("Error forcing flow control settings\n"); 1278 goto out; 1279 } 1280 1281 /* 1282 * Check for the case where we have copper media and auto-neg is 1283 * enabled. In this case, we need to check and see if Auto-Neg 1284 * has completed, and if so, how the PHY and link partner has 1285 * flow control configured. 1286 */ 1287 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1288 /* 1289 * Read the MII Status Register and check to see if AutoNeg 1290 * has completed. We read this twice because this reg has 1291 * some "sticky" (latched) bits. 1292 */ 1293 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1294 if (ret_val) 1295 goto out; 1296 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1297 if (ret_val) 1298 goto out; 1299 1300 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1301 DEBUGOUT("Copper PHY and Auto Neg " 1302 "has not completed.\n"); 1303 goto out; 1304 } 1305 1306 /* 1307 * The AutoNeg process has completed, so we now need to 1308 * read both the Auto Negotiation Advertisement 1309 * Register (Address 4) and the Auto_Negotiation Base 1310 * Page Ability Register (Address 5) to determine how 1311 * flow control was negotiated. 1312 */ 1313 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 1314 &mii_nway_adv_reg); 1315 if (ret_val) 1316 goto out; 1317 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 1318 &mii_nway_lp_ability_reg); 1319 if (ret_val) 1320 goto out; 1321 1322 /* 1323 * Two bits in the Auto Negotiation Advertisement Register 1324 * (Address 4) and two bits in the Auto Negotiation Base 1325 * Page Ability Register (Address 5) determine flow control 1326 * for both the PHY and the link partner. The following 1327 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1328 * 1999, describes these PAUSE resolution bits and how flow 1329 * control is determined based upon these settings. 1330 * NOTE: DC = Don't Care 1331 * 1332 * LOCAL DEVICE | LINK PARTNER 1333 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1334 * ------|---------|-------|---------|-------------------- 1335 * 0 | 0 | DC | DC | e1000_fc_none 1336 * 0 | 1 | 0 | DC | e1000_fc_none 1337 * 0 | 1 | 1 | 0 | e1000_fc_none 1338 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1339 * 1 | 0 | 0 | DC | e1000_fc_none 1340 * 1 | DC | 1 | DC | e1000_fc_full 1341 * 1 | 1 | 0 | 0 | e1000_fc_none 1342 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1343 * 1344 * Are both PAUSE bits set to 1? If so, this implies 1345 * Symmetric Flow Control is enabled at both ends. The 1346 * ASM_DIR bits are irrelevant per the spec. 1347 * 1348 * For Symmetric Flow Control: 1349 * 1350 * LOCAL DEVICE | LINK PARTNER 1351 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1352 * ------|---------|-------|---------|-------------------- 1353 * 1 | DC | 1 | DC | E1000_fc_full 1354 * 1355 */ 1356 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1357 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1358 /* 1359 * Now we need to check if the user selected Rx ONLY 1360 * of pause frames. In this case, we had to advertise 1361 * FULL flow control because we could not advertise RX 1362 * ONLY. Hence, we must now check to see if we need to 1363 * turn OFF the TRANSMISSION of PAUSE frames. 1364 */ 1365 if (hw->fc.original_type == e1000_fc_full) { 1366 hw->fc.type = e1000_fc_full; 1367 DEBUGOUT("Flow Control = FULL.\r\n"); 1368 } else { 1369 hw->fc.type = e1000_fc_rx_pause; 1370 DEBUGOUT("Flow Control = " 1371 "RX PAUSE frames only.\r\n"); 1372 } 1373 } 1374 /* 1375 * For receiving PAUSE frames ONLY. 1376 * 1377 * LOCAL DEVICE | LINK PARTNER 1378 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1379 * ------|---------|-------|---------|-------------------- 1380 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1381 */ 1382 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1383 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1384 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1385 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1386 hw->fc.type = e1000_fc_tx_pause; 1387 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1388 } 1389 /* 1390 * For transmitting PAUSE frames ONLY. 1391 * 1392 * LOCAL DEVICE | LINK PARTNER 1393 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1394 * ------|---------|-------|---------|-------------------- 1395 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1396 */ 1397 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1398 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1399 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1400 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1401 hw->fc.type = e1000_fc_rx_pause; 1402 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1403 } else { 1404 /* 1405 * Per the IEEE spec, at this point flow control 1406 * should be disabled. 1407 */ 1408 hw->fc.type = e1000_fc_none; 1409 DEBUGOUT("Flow Control = NONE.\r\n"); 1410 } 1411 1412 /* 1413 * Now we need to do one last check... If we auto- 1414 * negotiated to HALF DUPLEX, flow control should not be 1415 * enabled per IEEE 802.3 spec. 1416 */ 1417 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1418 if (ret_val) { 1419 DEBUGOUT("Error getting link speed and duplex\n"); 1420 goto out; 1421 } 1422 1423 if (duplex == HALF_DUPLEX) 1424 hw->fc.type = e1000_fc_none; 1425 1426 /* 1427 * Now we call a subroutine to actually force the MAC 1428 * controller to use the correct flow control settings. 1429 */ 1430 ret_val = e1000_force_mac_fc_generic(hw); 1431 if (ret_val) { 1432 DEBUGOUT("Error forcing flow control settings\n"); 1433 goto out; 1434 } 1435 } 1436 1437 out: 1438 return (ret_val); 1439 } 1440 1441 /* 1442 * e1000_get_speed_and_duplex_copper_generic - Retreive current speed/duplex 1443 * @hw: pointer to the HW structure 1444 * @speed: stores the current speed 1445 * @duplex: stores the current duplex 1446 * 1447 * Read the status register for the current speed/duplex and store the current 1448 * speed and duplex for copper connections. 1449 */ 1450 s32 1451 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1452 u16 *duplex) 1453 { 1454 u32 status; 1455 1456 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1457 1458 status = E1000_READ_REG(hw, E1000_STATUS); 1459 if (status & E1000_STATUS_SPEED_1000) { 1460 *speed = SPEED_1000; 1461 DEBUGOUT("1000 Mbs, "); 1462 } else if (status & E1000_STATUS_SPEED_100) { 1463 *speed = SPEED_100; 1464 DEBUGOUT("100 Mbs, "); 1465 } else { 1466 *speed = SPEED_10; 1467 DEBUGOUT("10 Mbs, "); 1468 } 1469 1470 if (status & E1000_STATUS_FD) { 1471 *duplex = FULL_DUPLEX; 1472 DEBUGOUT("Full Duplex\n"); 1473 } else { 1474 *duplex = HALF_DUPLEX; 1475 DEBUGOUT("Half Duplex\n"); 1476 } 1477 1478 return (E1000_SUCCESS); 1479 } 1480 1481 /* 1482 * e1000_get_speed_and_duplex_fiber_generic - Retreive current speed/duplex 1483 * @hw: pointer to the HW structure 1484 * @speed: stores the current speed 1485 * @duplex: stores the current duplex 1486 * 1487 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1488 * for fiber/serdes links. 1489 */ 1490 s32 1491 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1492 u16 *speed, u16 *duplex) 1493 { 1494 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1495 UNREFERENCED_PARAMETER(hw); 1496 1497 *speed = SPEED_1000; 1498 *duplex = FULL_DUPLEX; 1499 1500 return (E1000_SUCCESS); 1501 } 1502 1503 /* 1504 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1505 * @hw: pointer to the HW structure 1506 * 1507 * Acquire the HW semaphore to access the PHY or NVM 1508 */ 1509 s32 1510 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1511 { 1512 u32 swsm; 1513 s32 ret_val = E1000_SUCCESS; 1514 s32 timeout = hw->nvm.word_size + 1; 1515 s32 i = 0; 1516 1517 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1518 1519 /* Get the SW semaphore */ 1520 while (i < timeout) { 1521 swsm = E1000_READ_REG(hw, E1000_SWSM); 1522 if (!(swsm & E1000_SWSM_SMBI)) 1523 break; 1524 1525 usec_delay(50); 1526 i++; 1527 } 1528 1529 if (i == timeout) { 1530 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1531 ret_val = -E1000_ERR_NVM; 1532 goto out; 1533 } 1534 1535 /* Get the FW semaphore. */ 1536 for (i = 0; i < timeout; i++) { 1537 swsm = E1000_READ_REG(hw, E1000_SWSM); 1538 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1539 1540 /* Semaphore acquired if bit latched */ 1541 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1542 break; 1543 1544 usec_delay(50); 1545 } 1546 1547 if (i == timeout) { 1548 /* Release semaphores */ 1549 e1000_put_hw_semaphore_generic(hw); 1550 DEBUGOUT("Driver can't access the NVM\n"); 1551 ret_val = -E1000_ERR_NVM; 1552 goto out; 1553 } 1554 1555 out: 1556 return (ret_val); 1557 } 1558 1559 /* 1560 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1561 * @hw: pointer to the HW structure 1562 * 1563 * Release hardware semaphore used to access the PHY or NVM 1564 */ 1565 void 1566 e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1567 { 1568 u32 swsm; 1569 1570 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1571 1572 swsm = E1000_READ_REG(hw, E1000_SWSM); 1573 1574 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1575 1576 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1577 } 1578 1579 /* 1580 * e1000_get_auto_rd_done_generic - Check for auto read completion 1581 * @hw: pointer to the HW structure 1582 * 1583 * Check EEPROM for Auto Read done bit. 1584 */ 1585 s32 1586 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1587 { 1588 s32 i = 0; 1589 s32 ret_val = E1000_SUCCESS; 1590 1591 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1592 1593 while (i < AUTO_READ_DONE_TIMEOUT) { 1594 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1595 break; 1596 msec_delay(1); 1597 i++; 1598 } 1599 1600 if (i == AUTO_READ_DONE_TIMEOUT) { 1601 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1602 ret_val = -E1000_ERR_RESET; 1603 goto out; 1604 } 1605 1606 out: 1607 return (ret_val); 1608 } 1609 1610 /* 1611 * e1000_valid_led_default_generic - Verify a valid default LED config 1612 * @hw: pointer to the HW structure 1613 * @data: pointer to the NVM (EEPROM) 1614 * 1615 * Read the EEPROM for the current default LED configuration. If the 1616 * LED configuration is not valid, set to a valid LED configuration. 1617 */ 1618 s32 1619 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1620 { 1621 s32 ret_val; 1622 1623 DEBUGFUNC("e1000_valid_led_default_generic"); 1624 1625 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1626 if (ret_val) { 1627 DEBUGOUT("NVM Read Error\n"); 1628 goto out; 1629 } 1630 1631 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1632 *data = ID_LED_DEFAULT; 1633 1634 out: 1635 return (ret_val); 1636 } 1637 1638 /* 1639 * e1000_id_led_init_generic - 1640 * @hw: pointer to the HW structure 1641 * 1642 */ 1643 s32 1644 e1000_id_led_init_generic(struct e1000_hw *hw) 1645 { 1646 struct e1000_mac_info *mac = &hw->mac; 1647 s32 ret_val; 1648 const u32 ledctl_mask = 0x000000FF; 1649 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1650 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1651 u16 data, i, temp; 1652 const u16 led_mask = 0x0F; 1653 1654 DEBUGFUNC("e1000_id_led_init_generic"); 1655 1656 ret_val = hw->func.valid_led_default(hw, &data); 1657 if (ret_val) 1658 goto out; 1659 1660 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1661 mac->ledctl_mode1 = mac->ledctl_default; 1662 mac->ledctl_mode2 = mac->ledctl_default; 1663 1664 for (i = 0; i < 4; i++) { 1665 temp = (data >> (i << 2)) & led_mask; 1666 switch (temp) { 1667 case ID_LED_ON1_DEF2: 1668 case ID_LED_ON1_ON2: 1669 case ID_LED_ON1_OFF2: 1670 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1671 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1672 break; 1673 case ID_LED_OFF1_DEF2: 1674 case ID_LED_OFF1_ON2: 1675 case ID_LED_OFF1_OFF2: 1676 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1677 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1678 break; 1679 default: 1680 /* Do nothing */ 1681 break; 1682 } 1683 switch (temp) { 1684 case ID_LED_DEF1_ON2: 1685 case ID_LED_ON1_ON2: 1686 case ID_LED_OFF1_ON2: 1687 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1688 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1689 break; 1690 case ID_LED_DEF1_OFF2: 1691 case ID_LED_ON1_OFF2: 1692 case ID_LED_OFF1_OFF2: 1693 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1694 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1695 break; 1696 default: 1697 /* Do nothing */ 1698 break; 1699 } 1700 } 1701 1702 out: 1703 return (ret_val); 1704 } 1705 1706 /* 1707 * e1000_setup_led_generic - Configures SW controllable LED 1708 * @hw: pointer to the HW structure 1709 * 1710 * This prepares the SW controllable LED for use and saves the current state 1711 * of the LED so it can be later restored. 1712 */ 1713 s32 1714 e1000_setup_led_generic(struct e1000_hw *hw) 1715 { 1716 u32 ledctl; 1717 s32 ret_val = E1000_SUCCESS; 1718 1719 DEBUGFUNC("e1000_setup_led_generic"); 1720 1721 if (hw->func.setup_led != e1000_setup_led_generic) { 1722 ret_val = -E1000_ERR_CONFIG; 1723 goto out; 1724 } 1725 1726 if (hw->phy.media_type == e1000_media_type_fiber) { 1727 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1728 hw->mac.ledctl_default = ledctl; 1729 /* Turn off LED0 */ 1730 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1731 E1000_LEDCTL_LED0_BLINK | 1732 E1000_LEDCTL_LED0_MODE_MASK); 1733 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1734 E1000_LEDCTL_LED0_MODE_SHIFT); 1735 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1736 } else if (hw->phy.media_type == e1000_media_type_copper) { 1737 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1738 } 1739 1740 out: 1741 return (ret_val); 1742 } 1743 1744 /* 1745 * e1000_cleanup_led_generic - Set LED config to default operation 1746 * @hw: pointer to the HW structure 1747 * 1748 * Remove the current LED configuration and set the LED configuration 1749 * to the default value, saved from the EEPROM. 1750 */ 1751 s32 1752 e1000_cleanup_led_generic(struct e1000_hw *hw) 1753 { 1754 s32 ret_val = E1000_SUCCESS; 1755 1756 DEBUGFUNC("e1000_cleanup_led_generic"); 1757 1758 if (hw->func.cleanup_led != e1000_cleanup_led_generic) { 1759 ret_val = -E1000_ERR_CONFIG; 1760 goto out; 1761 } 1762 1763 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1764 1765 out: 1766 return (ret_val); 1767 } 1768 1769 /* 1770 * e1000_blink_led_generic - Blink LED 1771 * @hw: pointer to the HW structure 1772 * 1773 * Blink the led's which are set to be on. 1774 */ 1775 s32 1776 e1000_blink_led_generic(struct e1000_hw *hw) 1777 { 1778 u32 ledctl_blink = 0; 1779 u32 i; 1780 1781 DEBUGFUNC("e1000_blink_led_generic"); 1782 1783 if (hw->phy.media_type == e1000_media_type_fiber) { 1784 /* always blink LED0 for PCI-E fiber */ 1785 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1786 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1787 } else { 1788 /* 1789 * set the blink bit for each LED that's "on" (0x0E) 1790 * in ledctl_mode2 1791 */ 1792 ledctl_blink = hw->mac.ledctl_mode2; 1793 for (i = 0; i < 4; i++) 1794 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1795 E1000_LEDCTL_MODE_LED_ON) 1796 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1797 (i * 8)); 1798 } 1799 1800 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1801 1802 return (E1000_SUCCESS); 1803 } 1804 1805 /* 1806 * e1000_led_on_generic - Turn LED on 1807 * @hw: pointer to the HW structure 1808 * 1809 * Turn LED on. 1810 */ 1811 s32 1812 e1000_led_on_generic(struct e1000_hw *hw) 1813 { 1814 u32 ctrl; 1815 1816 DEBUGFUNC("e1000_led_on_generic"); 1817 1818 switch (hw->phy.media_type) { 1819 case e1000_media_type_fiber: 1820 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1821 ctrl &= ~E1000_CTRL_SWDPIN0; 1822 ctrl |= E1000_CTRL_SWDPIO0; 1823 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1824 break; 1825 case e1000_media_type_copper: 1826 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1827 break; 1828 default: 1829 break; 1830 } 1831 1832 return (E1000_SUCCESS); 1833 } 1834 1835 /* 1836 * e1000_led_off_generic - Turn LED off 1837 * @hw: pointer to the HW structure 1838 * 1839 * Turn LED off. 1840 */ 1841 s32 1842 e1000_led_off_generic(struct e1000_hw *hw) 1843 { 1844 u32 ctrl; 1845 1846 DEBUGFUNC("e1000_led_off_generic"); 1847 1848 switch (hw->phy.media_type) { 1849 case e1000_media_type_fiber: 1850 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1851 ctrl |= E1000_CTRL_SWDPIN0; 1852 ctrl |= E1000_CTRL_SWDPIO0; 1853 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1854 break; 1855 case e1000_media_type_copper: 1856 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1857 break; 1858 default: 1859 break; 1860 } 1861 1862 return (E1000_SUCCESS); 1863 } 1864 1865 /* 1866 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1867 * @hw: pointer to the HW structure 1868 * @no_snoop: bitmap of snoop events 1869 * 1870 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1871 */ 1872 void 1873 e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1874 { 1875 u32 gcr; 1876 1877 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1878 1879 if (hw->bus.type != e1000_bus_type_pci_express) 1880 return; 1881 1882 if (no_snoop) { 1883 gcr = E1000_READ_REG(hw, E1000_GCR); 1884 gcr &= ~(PCIE_NO_SNOOP_ALL); 1885 gcr |= no_snoop; 1886 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1887 } 1888 } 1889 1890 /* 1891 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1892 * @hw: pointer to the HW structure 1893 * 1894 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1895 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued 1896 * the master requests to be disabled. 1897 * 1898 * Disables PCI-Express master access and verifies there are no pending 1899 * requests. 1900 */ 1901 s32 1902 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1903 { 1904 u32 ctrl; 1905 s32 timeout = MASTER_DISABLE_TIMEOUT; 1906 s32 ret_val = E1000_SUCCESS; 1907 1908 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1909 1910 if (hw->bus.type != e1000_bus_type_pci_express) 1911 goto out; 1912 1913 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1914 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1915 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1916 1917 while (timeout) { 1918 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1919 E1000_STATUS_GIO_MASTER_ENABLE)) 1920 break; 1921 usec_delay(100); 1922 timeout--; 1923 } 1924 1925 if (!timeout) { 1926 DEBUGOUT("Master requests are pending.\n"); 1927 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1928 goto out; 1929 } 1930 1931 out: 1932 return (ret_val); 1933 } 1934 1935 /* 1936 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 1937 * @hw: pointer to the HW structure 1938 * 1939 * Reset the Adaptive Interframe Spacing throttle to default values. 1940 */ 1941 void 1942 e1000_reset_adaptive_generic(struct e1000_hw *hw) 1943 { 1944 struct e1000_mac_info *mac = &hw->mac; 1945 1946 DEBUGFUNC("e1000_reset_adaptive_generic"); 1947 1948 if (!mac->adaptive_ifs) { 1949 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1950 return; 1951 } 1952 1953 if (!mac->ifs_params_forced) { 1954 mac->current_ifs_val = 0; 1955 mac->ifs_min_val = IFS_MIN; 1956 mac->ifs_max_val = IFS_MAX; 1957 mac->ifs_step_size = IFS_STEP; 1958 mac->ifs_ratio = IFS_RATIO; 1959 } 1960 1961 mac->in_ifs_mode = FALSE; 1962 E1000_WRITE_REG(hw, E1000_AIT, 0); 1963 } 1964 1965 /* 1966 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 1967 * @hw: pointer to the HW structure 1968 * 1969 * Update the Adaptive Interframe Spacing Throttle value based on the 1970 * time between transmitted packets and time between collisions. 1971 */ 1972 void 1973 e1000_update_adaptive_generic(struct e1000_hw *hw) 1974 { 1975 struct e1000_mac_info *mac = &hw->mac; 1976 1977 DEBUGFUNC("e1000_update_adaptive_generic"); 1978 1979 if (!mac->adaptive_ifs) { 1980 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1981 return; 1982 } 1983 1984 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1985 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1986 mac->in_ifs_mode = TRUE; 1987 if (mac->current_ifs_val < mac->ifs_max_val) { 1988 if (!mac->current_ifs_val) 1989 mac->current_ifs_val = mac->ifs_min_val; 1990 else 1991 mac->current_ifs_val += 1992 mac->ifs_step_size; 1993 E1000_WRITE_REG(hw, E1000_AIT, 1994 mac->current_ifs_val); 1995 } 1996 } 1997 } else { 1998 if (mac->in_ifs_mode && 1999 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2000 mac->current_ifs_val = 0; 2001 mac->in_ifs_mode = FALSE; 2002 E1000_WRITE_REG(hw, E1000_AIT, 0); 2003 } 2004 } 2005 } 2006 2007 /* 2008 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2009 * @hw: pointer to the HW structure 2010 * 2011 * Verify that when not using auto-negotitation that MDI/MDIx is correctly 2012 * set, which is forced to MDI mode only. 2013 */ 2014 s32 2015 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2016 { 2017 s32 ret_val = E1000_SUCCESS; 2018 2019 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2020 2021 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2022 DEBUGOUT("Invalid MDI setting detected\n"); 2023 hw->phy.mdix = 1; 2024 ret_val = -E1000_ERR_CONFIG; 2025 goto out; 2026 } 2027 2028 out: 2029 return (ret_val); 2030 } 2031 2032 /* 2033 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2034 * @hw: pointer to the HW structure 2035 * @reg: 32bit register offset such as E1000_SCTL 2036 * @offset: register offset to write to 2037 * @data: data to write at register offset 2038 * 2039 * Writes an address/data control type register. There are several of these 2040 * and they all have the format address << 8 | data and bit 31 is polled for 2041 * completion. 2042 */ 2043 s32 2044 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2045 u32 offset, u8 data) 2046 { 2047 u32 i, regvalue = 0; 2048 s32 ret_val = E1000_SUCCESS; 2049 2050 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2051 2052 /* Set up the address and data */ 2053 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2054 E1000_WRITE_REG(hw, reg, regvalue); 2055 2056 /* Poll the ready bit to see if the MDI read completed */ 2057 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2058 usec_delay(5); 2059 regvalue = E1000_READ_REG(hw, reg); 2060 if (regvalue & E1000_GEN_CTL_READY) 2061 break; 2062 } 2063 if (!(regvalue & E1000_GEN_CTL_READY)) { 2064 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2065 ret_val = -E1000_ERR_PHY; 2066 goto out; 2067 } 2068 2069 out: 2070 return (ret_val); 2071 } 2072