1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.104 v2-9-8_2009-6-12 */ 30 31 #include "igb_api.h" 32 33 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw); 34 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); 35 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); 36 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 37 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 38 39 /* 40 * e1000_init_mac_ops_generic - Initialize MAC function pointers 41 * @hw: pointer to the HW structure 42 * 43 * Setups up the function pointers to no-op functions 44 */ 45 void 46 e1000_init_mac_ops_generic(struct e1000_hw *hw) 47 { 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.mta_set = e1000_null_mta_set; 82 mac->ops.rar_set = e1000_rar_set_generic; 83 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 84 } 85 86 /* 87 * e1000_null_ops_generic - No-op function, returns 0 88 * @hw: pointer to the HW structure 89 */ 90 s32 91 e1000_null_ops_generic(struct e1000_hw *hw) 92 { 93 DEBUGFUNC("e1000_null_ops_generic"); 94 UNREFERENCED_1PARAMETER(hw); 95 return (E1000_SUCCESS); 96 } 97 98 /* 99 * e1000_null_mac_generic - No-op function, return void 100 * @hw: pointer to the HW structure 101 */ 102 void 103 e1000_null_mac_generic(struct e1000_hw *hw) 104 { 105 DEBUGFUNC("e1000_null_mac_generic"); 106 UNREFERENCED_1PARAMETER(hw); 107 } 108 109 /* 110 * e1000_null_link_info - No-op function, return 0 111 * @hw: pointer to the HW structure 112 */ 113 s32 114 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 115 { 116 DEBUGFUNC("e1000_null_link_info"); 117 UNREFERENCED_3PARAMETER(hw, s, d); 118 return (E1000_SUCCESS); 119 } 120 121 /* 122 * e1000_null_mng_mode - No-op function, return false 123 * @hw: pointer to the HW structure 124 */ 125 bool 126 e1000_null_mng_mode(struct e1000_hw *hw) 127 { 128 DEBUGFUNC("e1000_null_mng_mode"); 129 UNREFERENCED_1PARAMETER(hw); 130 return (false); 131 } 132 133 /* 134 * e1000_null_update_mc - No-op function, return void 135 * @hw: pointer to the HW structure 136 */ 137 void 138 e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 139 { 140 DEBUGFUNC("e1000_null_update_mc"); 141 UNREFERENCED_3PARAMETER(hw, h, a); 142 } 143 144 /* 145 * e1000_null_write_vfta - No-op function, return void 146 * @hw: pointer to the HW structure 147 */ 148 void 149 e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 150 { 151 DEBUGFUNC("e1000_null_write_vfta"); 152 UNREFERENCED_3PARAMETER(hw, a, b); 153 } 154 155 /* 156 * e1000_null_set_mta - No-op function, return void 157 * @hw: pointer to the HW structure 158 */ 159 void 160 e1000_null_mta_set(struct e1000_hw *hw, u32 a) 161 { 162 DEBUGFUNC("e1000_null_mta_set"); 163 UNREFERENCED_2PARAMETER(hw, a); 164 } 165 166 /* 167 * e1000_null_rar_set - No-op function, return void 168 * @hw: pointer to the HW structure 169 */ 170 void 171 e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 172 { 173 DEBUGFUNC("e1000_null_rar_set"); 174 UNREFERENCED_3PARAMETER(hw, h, a); 175 } 176 177 /* 178 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 179 * @hw: pointer to the HW structure 180 * 181 * Determines and stores the system bus information for a particular 182 * network interface. The following bus information is determined and stored: 183 * bus speed, bus width, type (PCIe), and PCIe function. 184 */ 185 s32 186 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 187 { 188 struct e1000_mac_info *mac = &hw->mac; 189 struct e1000_bus_info *bus = &hw->bus; 190 s32 ret_val; 191 u16 pcie_link_status; 192 193 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 194 195 bus->type = e1000_bus_type_pci_express; 196 bus->speed = e1000_bus_speed_2500; 197 198 ret_val = e1000_read_pcie_cap_reg(hw, 199 PCIE_LINK_STATUS, &pcie_link_status); 200 if (ret_val) 201 bus->width = e1000_bus_width_unknown; 202 else 203 bus->width = (enum e1000_bus_width)((pcie_link_status & 204 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 205 206 mac->ops.set_lan_id(hw); 207 208 return (E1000_SUCCESS); 209 } 210 211 /* 212 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 213 * 214 * @hw: pointer to the HW structure 215 * 216 * Determines the LAN function id by reading memory-mapped registers 217 * and swaps the port value if requested. 218 */ 219 static void 220 e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 221 { 222 struct e1000_bus_info *bus = &hw->bus; 223 u32 reg; 224 225 /* 226 * The status register reports the correct function number 227 * for the device regardless of function swap state. 228 */ 229 reg = E1000_READ_REG(hw, E1000_STATUS); 230 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 231 } 232 233 /* 234 * e1000_set_lan_id_single_port - Set LAN id for a single port device 235 * @hw: pointer to the HW structure 236 * 237 * Sets the LAN function id to zero for a single port device. 238 */ 239 void 240 e1000_set_lan_id_single_port(struct e1000_hw *hw) 241 { 242 struct e1000_bus_info *bus = &hw->bus; 243 244 bus->func = 0; 245 } 246 247 /* 248 * e1000_clear_vfta_generic - Clear VLAN filter table 249 * @hw: pointer to the HW structure 250 * 251 * Clears the register array which contains the VLAN filter table by 252 * setting all the values to 0. 253 */ 254 void 255 e1000_clear_vfta_generic(struct e1000_hw *hw) 256 { 257 u32 offset; 258 259 DEBUGFUNC("e1000_clear_vfta_generic"); 260 261 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 262 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 263 E1000_WRITE_FLUSH(hw); 264 } 265 } 266 267 /* 268 * e1000_write_vfta_generic - Write value to VLAN filter table 269 * @hw: pointer to the HW structure 270 * @offset: register offset in VLAN filter table 271 * @value: register value written to VLAN filter table 272 * 273 * Writes value at the given offset in the register array which stores 274 * the VLAN filter table. 275 */ 276 void 277 e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 278 { 279 DEBUGFUNC("e1000_write_vfta_generic"); 280 281 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 282 E1000_WRITE_FLUSH(hw); 283 } 284 285 /* 286 * e1000_init_rx_addrs_generic - Initialize receive address's 287 * @hw: pointer to the HW structure 288 * @rar_count: receive address registers 289 * 290 * Setups the receive address registers by setting the base receive address 291 * register to the devices MAC address and clearing all the other receive 292 * address registers to 0. 293 */ 294 void 295 e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 296 { 297 u32 i; 298 u8 mac_addr[ETH_ADDR_LEN] = {0}; 299 300 DEBUGFUNC("e1000_init_rx_addrs_generic"); 301 302 /* Setup the receive address */ 303 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 304 305 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 306 307 /* Zero out the other (rar_entry_count - 1) receive addresses */ 308 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 309 for (i = 1; i < rar_count; i++) 310 hw->mac.ops.rar_set(hw, mac_addr, i); 311 } 312 313 /* 314 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 315 * @hw: pointer to the HW structure 316 * 317 * Checks the nvm for an alternate MAC address. An alternate MAC address 318 * can be setup by pre-boot software and must be treated like a permanent 319 * address and must override the actual permanent MAC address. If an 320 * alternate MAC address is found it is programmed into RAR0, replacing 321 * the permanent address that was installed into RAR0 by the Si on reset. 322 * This function will return SUCCESS unless it encounters an error while 323 * reading the EEPROM. 324 */ 325 s32 326 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 327 { 328 u32 i; 329 s32 ret_val = E1000_SUCCESS; 330 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 331 u8 alt_mac_addr[ETH_ADDR_LEN]; 332 333 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 334 335 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 336 &nvm_alt_mac_addr_offset); 337 if (ret_val) { 338 DEBUGOUT("NVM Read Error\n"); 339 goto out; 340 } 341 342 if (nvm_alt_mac_addr_offset == 0xFFFF) { 343 /* There is no Alternate MAC Address */ 344 goto out; 345 } 346 347 if (hw->bus.func == E1000_FUNC_1) 348 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 349 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 350 offset = nvm_alt_mac_addr_offset + (i >> 1); 351 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 352 if (ret_val) { 353 DEBUGOUT("NVM Read Error\n"); 354 goto out; 355 } 356 357 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 358 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 359 } 360 361 /* if multicast bit is set, the alternate address will not be used */ 362 if (alt_mac_addr[0] & 0x01) { 363 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 364 goto out; 365 } 366 367 /* 368 * We have a valid alternate MAC address, and we want to treat it the 369 * same as the normal permanent MAC address stored by the HW into the 370 * RAR. Do this by mapping this address into RAR0. 371 */ 372 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 373 374 out: 375 return (ret_val); 376 } 377 378 /* 379 * e1000_rar_set_generic - Set receive address register 380 * @hw: pointer to the HW structure 381 * @addr: pointer to the receive address 382 * @index: receive address array register 383 * 384 * Sets the receive address array register at index to the address passed 385 * in by addr. 386 */ 387 void 388 e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 389 { 390 u32 rar_low, rar_high; 391 392 DEBUGFUNC("e1000_rar_set_generic"); 393 394 /* 395 * HW expects these in little endian so we reverse the byte order 396 * from network order (big endian) to little endian 397 */ 398 rar_low = ((u32) addr[0] | 399 ((u32) addr[1] << 8) | 400 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 401 402 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 403 404 /* If MAC address zero, no need to set the AV bit */ 405 if (rar_low || rar_high) 406 rar_high |= E1000_RAH_AV; 407 408 /* 409 * Some bridges will combine consecutive 32-bit writes into 410 * a single burst write, which will malfunction on some parts. 411 * The flushes avoid this. 412 */ 413 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 414 E1000_WRITE_FLUSH(hw); 415 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 416 E1000_WRITE_FLUSH(hw); 417 } 418 419 /* 420 * e1000_mta_set_generic - Set multicast filter table address 421 * @hw: pointer to the HW structure 422 * @hash_value: determines the MTA register and bit to set 423 * 424 * The multicast table address is a register array of 32-bit registers. 425 * The hash_value is used to determine what register the bit is in, the 426 * current value is read, the new bit is OR'd in and the new value is 427 * written back into the register. 428 */ 429 void 430 e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 431 { 432 u32 hash_bit, hash_reg, mta; 433 434 DEBUGFUNC("e1000_mta_set_generic"); 435 /* 436 * The MTA is a register array of 32-bit registers. It is 437 * treated like an array of (32*mta_reg_count) bits. We want to 438 * set bit BitArray[hash_value]. So we figure out what register 439 * the bit is in, read it, OR in the new bit, then write 440 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 441 * mask to bits 31:5 of the hash value which gives us the 442 * register we're modifying. The hash bit within that register 443 * is determined by the lower 5 bits of the hash value. 444 */ 445 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 446 hash_bit = hash_value & 0x1F; 447 448 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 449 450 mta |= (1 << hash_bit); 451 452 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 453 E1000_WRITE_FLUSH(hw); 454 } 455 456 /* 457 * e1000_update_mc_addr_list_generic - Update Multicast addresses 458 * @hw: pointer to the HW structure 459 * @mc_addr_list: array of multicast addresses to program 460 * @mc_addr_count: number of multicast addresses to program 461 * 462 * Updates the Multicast Table Array. 463 * The caller must have a packed mc_addr_list of multicast addresses. 464 */ 465 void 466 e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 467 u8 *mc_addr_list, u32 mc_addr_count) 468 { 469 u32 hash_value, hash_bit, hash_reg; 470 int i; 471 472 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 473 474 /* clear mta_shadow */ 475 memset(&hw->mac.mta_shadow, 0, sizeof (hw->mac.mta_shadow)); 476 477 /* update mta_shadow from mc_addr_list */ 478 for (i = 0; (u32) i < mc_addr_count; i++) { 479 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 480 481 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 482 hash_bit = hash_value & 0x1F; 483 484 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 485 mc_addr_list += (ETH_ADDR_LEN); 486 } 487 488 /* replace the entire MTA table */ 489 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 490 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 491 E1000_WRITE_FLUSH(hw); 492 } 493 494 /* 495 * e1000_hash_mc_addr_generic - Generate a multicast hash value 496 * @hw: pointer to the HW structure 497 * @mc_addr: pointer to a multicast address 498 * 499 * Generates a multicast address hash value which is used to determine 500 * the multicast filter table array address and new table value. See 501 * e1000_mta_set_generic() 502 */ 503 u32 504 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 505 { 506 u32 hash_value, hash_mask; 507 u8 bit_shift = 0; 508 509 DEBUGFUNC("e1000_hash_mc_addr_generic"); 510 511 /* Register count multiplied by bits per register */ 512 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 513 514 /* 515 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 516 * where 0xFF would still fall within the hash mask. 517 */ 518 while (hash_mask >> bit_shift != 0xFF) 519 bit_shift++; 520 521 /* 522 * The portion of the address that is used for the hash table 523 * is determined by the mc_filter_type setting. 524 * The algorithm is such that there is a total of 8 bits of shifting. 525 * The bit_shift for a mc_filter_type of 0 represents the number of 526 * left-shifts where the MSB of mc_addr[5] would still fall within 527 * the hash_mask. Case 0 does this exactly. Since there are a total 528 * of 8 bits of shifting, then mc_addr[4] will shift right the 529 * remaining number of bits. Thus 8 - bit_shift. The rest of the 530 * cases are a variation of this algorithm...essentially raising the 531 * number of bits to shift mc_addr[5] left, while still keeping the 532 * 8-bit shifting total. 533 * 534 * For example, given the following Destination MAC Address and an 535 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 536 * we can see that the bit_shift for case 0 is 4. These are the hash 537 * values resulting from each mc_filter_type... 538 * [0] [1] [2] [3] [4] [5] 539 * 01 AA 00 12 34 56 540 * LSB MSB 541 * 542 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 543 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 544 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 545 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 546 */ 547 switch (hw->mac.mc_filter_type) { 548 default: 549 case 0: 550 break; 551 case 1: 552 bit_shift += 1; 553 break; 554 case 2: 555 bit_shift += 2; 556 break; 557 case 3: 558 bit_shift += 4; 559 break; 560 } 561 562 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 563 (((u16) mc_addr[5]) << bit_shift))); 564 565 return (hash_value); 566 } 567 568 /* 569 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 570 * @hw: pointer to the HW structure 571 * 572 * Clears the base hardware counters by reading the counter registers. 573 */ 574 void 575 e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 576 { 577 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 578 579 (void) E1000_READ_REG(hw, E1000_CRCERRS); 580 (void) E1000_READ_REG(hw, E1000_SYMERRS); 581 (void) E1000_READ_REG(hw, E1000_MPC); 582 (void) E1000_READ_REG(hw, E1000_SCC); 583 (void) E1000_READ_REG(hw, E1000_ECOL); 584 (void) E1000_READ_REG(hw, E1000_MCC); 585 (void) E1000_READ_REG(hw, E1000_LATECOL); 586 (void) E1000_READ_REG(hw, E1000_COLC); 587 (void) E1000_READ_REG(hw, E1000_DC); 588 (void) E1000_READ_REG(hw, E1000_SEC); 589 (void) E1000_READ_REG(hw, E1000_RLEC); 590 (void) E1000_READ_REG(hw, E1000_XONRXC); 591 (void) E1000_READ_REG(hw, E1000_XONTXC); 592 (void) E1000_READ_REG(hw, E1000_XOFFRXC); 593 (void) E1000_READ_REG(hw, E1000_XOFFTXC); 594 (void) E1000_READ_REG(hw, E1000_FCRUC); 595 (void) E1000_READ_REG(hw, E1000_GPRC); 596 (void) E1000_READ_REG(hw, E1000_BPRC); 597 (void) E1000_READ_REG(hw, E1000_MPRC); 598 (void) E1000_READ_REG(hw, E1000_GPTC); 599 (void) E1000_READ_REG(hw, E1000_GORCL); 600 (void) E1000_READ_REG(hw, E1000_GORCH); 601 (void) E1000_READ_REG(hw, E1000_GOTCL); 602 (void) E1000_READ_REG(hw, E1000_GOTCH); 603 (void) E1000_READ_REG(hw, E1000_RNBC); 604 (void) E1000_READ_REG(hw, E1000_RUC); 605 (void) E1000_READ_REG(hw, E1000_RFC); 606 (void) E1000_READ_REG(hw, E1000_ROC); 607 (void) E1000_READ_REG(hw, E1000_RJC); 608 (void) E1000_READ_REG(hw, E1000_TORL); 609 (void) E1000_READ_REG(hw, E1000_TORH); 610 (void) E1000_READ_REG(hw, E1000_TOTL); 611 (void) E1000_READ_REG(hw, E1000_TOTH); 612 (void) E1000_READ_REG(hw, E1000_TPR); 613 (void) E1000_READ_REG(hw, E1000_TPT); 614 (void) E1000_READ_REG(hw, E1000_MPTC); 615 (void) E1000_READ_REG(hw, E1000_BPTC); 616 } 617 618 /* 619 * e1000_check_for_copper_link_generic - Check for link (Copper) 620 * @hw: pointer to the HW structure 621 * 622 * Checks to see of the link status of the hardware has changed. If a 623 * change in link status has been detected, then we read the PHY registers 624 * to get the current speed/duplex if link exists. 625 */ 626 s32 627 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 628 { 629 struct e1000_mac_info *mac = &hw->mac; 630 s32 ret_val; 631 bool link; 632 633 DEBUGFUNC("e1000_check_for_copper_link"); 634 635 /* 636 * We only want to go out to the PHY registers to see if Auto-Neg 637 * has completed and/or if our link status has changed. The 638 * get_link_status flag is set upon receiving a Link Status 639 * Change or Rx Sequence Error interrupt. 640 */ 641 if (!mac->get_link_status) { 642 ret_val = E1000_SUCCESS; 643 goto out; 644 } 645 646 /* 647 * First we want to see if the MII Status Register reports 648 * link. If so, then we want to get the current speed/duplex 649 * of the PHY. 650 */ 651 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 652 if (ret_val) 653 goto out; 654 655 if (!link) 656 goto out; /* No link detected */ 657 658 mac->get_link_status = false; 659 660 /* 661 * Check if there was DownShift, must be checked 662 * immediately after link-up 663 */ 664 (void) e1000_check_downshift_generic(hw); 665 666 /* 667 * If we are forcing speed/duplex, then we simply return since 668 * we have already determined whether we have link or not. 669 */ 670 if (!mac->autoneg) { 671 ret_val = -E1000_ERR_CONFIG; 672 goto out; 673 } 674 675 /* 676 * Auto-Neg is enabled. Auto Speed Detection takes care 677 * of MAC speed/duplex configuration. So we only need to 678 * configure Collision Distance in the MAC. 679 */ 680 e1000_config_collision_dist_generic(hw); 681 682 /* 683 * Configure Flow Control now that Auto-Neg has completed. 684 * First, we need to restore the desired flow control 685 * settings because we may have had to re-autoneg with a 686 * different link partner. 687 */ 688 ret_val = e1000_config_fc_after_link_up_generic(hw); 689 if (ret_val) 690 DEBUGOUT("Error configuring flow control\n"); 691 692 out: 693 return (ret_val); 694 } 695 696 /* 697 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 698 * @hw: pointer to the HW structure 699 * 700 * Checks for link up on the hardware. If link is not up and we have 701 * a signal, then we need to force link up. 702 */ 703 s32 704 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 705 { 706 struct e1000_mac_info *mac = &hw->mac; 707 u32 rxcw; 708 u32 ctrl; 709 u32 status; 710 s32 ret_val = E1000_SUCCESS; 711 712 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 713 714 ctrl = E1000_READ_REG(hw, E1000_CTRL); 715 status = E1000_READ_REG(hw, E1000_STATUS); 716 rxcw = E1000_READ_REG(hw, E1000_RXCW); 717 718 /* 719 * If we don't have link (auto-negotiation failed or link partner 720 * cannot auto-negotiate), the cable is plugged in (we have signal), 721 * and our link partner is not trying to auto-negotiate with us (we 722 * are receiving idles or data), we need to force link up. We also 723 * need to give auto-negotiation time to complete, in case the cable 724 * was just plugged in. The autoneg_failed flag does this. 725 */ 726 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 727 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 728 (!(rxcw & E1000_RXCW_C))) { 729 if (mac->autoneg_failed == 0) { 730 mac->autoneg_failed = 1; 731 goto out; 732 } 733 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 734 735 /* Disable auto-negotiation in the TXCW register */ 736 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 737 738 /* Force link-up and also force full-duplex. */ 739 ctrl = E1000_READ_REG(hw, E1000_CTRL); 740 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 741 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 742 743 /* Configure Flow Control after forcing link up. */ 744 ret_val = e1000_config_fc_after_link_up_generic(hw); 745 if (ret_val) { 746 DEBUGOUT("Error configuring flow control\n"); 747 goto out; 748 } 749 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 750 /* 751 * If we are forcing link and we are receiving /C/ ordered 752 * sets, re-enable auto-negotiation in the TXCW register 753 * and disable forced link in the Device Control register 754 * in an attempt to auto-negotiate with our link partner. 755 */ 756 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 757 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 758 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 759 760 mac->serdes_has_link = true; 761 } 762 763 out: 764 return (ret_val); 765 } 766 767 /* 768 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 769 * @hw: pointer to the HW structure 770 * 771 * Checks for link up on the hardware. If link is not up and we have 772 * a signal, then we need to force link up. 773 */ 774 s32 775 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 776 { 777 struct e1000_mac_info *mac = &hw->mac; 778 u32 rxcw; 779 u32 ctrl; 780 u32 status; 781 s32 ret_val = E1000_SUCCESS; 782 783 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 784 785 ctrl = E1000_READ_REG(hw, E1000_CTRL); 786 status = E1000_READ_REG(hw, E1000_STATUS); 787 rxcw = E1000_READ_REG(hw, E1000_RXCW); 788 789 /* 790 * If we don't have link (auto-negotiation failed or link partner 791 * cannot auto-negotiate), and our link partner is not trying to 792 * auto-negotiate with us (we are receiving idles or data), 793 * we need to force link up. We also need to give auto-negotiation 794 * time to complete. 795 */ 796 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 797 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 798 if (mac->autoneg_failed == 0) { 799 mac->autoneg_failed = 1; 800 goto out; 801 } 802 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 803 804 /* Disable auto-negotiation in the TXCW register */ 805 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 806 807 /* Force link-up and also force full-duplex. */ 808 ctrl = E1000_READ_REG(hw, E1000_CTRL); 809 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 810 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 811 812 /* Configure Flow Control after forcing link up. */ 813 ret_val = e1000_config_fc_after_link_up_generic(hw); 814 if (ret_val) { 815 DEBUGOUT("Error configuring flow control\n"); 816 goto out; 817 } 818 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 819 /* 820 * If we are forcing link and we are receiving /C/ ordered 821 * sets, re-enable auto-negotiation in the TXCW register 822 * and disable forced link in the Device Control register 823 * in an attempt to auto-negotiate with our link partner. 824 */ 825 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 826 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 827 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 828 829 mac->serdes_has_link = true; 830 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 831 /* 832 * If we force link for non-auto-negotiation switch, check 833 * link status based on MAC synchronization for internal 834 * serdes media type. 835 */ 836 /* SYNCH bit and IV bit are sticky. */ 837 usec_delay(10); 838 rxcw = E1000_READ_REG(hw, E1000_RXCW); 839 if (rxcw & E1000_RXCW_SYNCH) { 840 if (!(rxcw & E1000_RXCW_IV)) { 841 mac->serdes_has_link = true; 842 DEBUGOUT("SERDES: Link up - forced.\n"); 843 } 844 } else { 845 mac->serdes_has_link = false; 846 DEBUGOUT("SERDES: Link down - force failed.\n"); 847 } 848 } 849 850 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 851 status = E1000_READ_REG(hw, E1000_STATUS); 852 if (status & E1000_STATUS_LU) { 853 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 854 usec_delay(10); 855 rxcw = E1000_READ_REG(hw, E1000_RXCW); 856 if (rxcw & E1000_RXCW_SYNCH) { 857 if (!(rxcw & E1000_RXCW_IV)) { 858 mac->serdes_has_link = true; 859 DEBUGOUT("SERDES: Link up - autoneg " 860 "completed sucessfully.\n"); 861 } else { 862 mac->serdes_has_link = false; 863 DEBUGOUT("SERDES: Link down - invalid" 864 "codewords detected in autoneg.\n"); 865 } 866 } else { 867 mac->serdes_has_link = false; 868 DEBUGOUT("SERDES: Link down - no sync.\n"); 869 } 870 } else { 871 mac->serdes_has_link = false; 872 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 873 } 874 } 875 876 out: 877 return (ret_val); 878 } 879 880 /* 881 * e1000_setup_link_generic - Setup flow control and link settings 882 * @hw: pointer to the HW structure 883 * 884 * Determines which flow control settings to use, then configures flow 885 * control. Calls the appropriate media-specific link configuration 886 * function. Assuming the adapter has a valid link partner, a valid link 887 * should be established. Assumes the hardware has previously been reset 888 * and the transmitter and receiver are not enabled. 889 */ 890 s32 891 e1000_setup_link_generic(struct e1000_hw *hw) 892 { 893 s32 ret_val = E1000_SUCCESS; 894 895 DEBUGFUNC("e1000_setup_link_generic"); 896 897 /* 898 * In the case of the phy reset being blocked, we already have a link. 899 * We do not need to set it up again. 900 */ 901 if (hw->phy.ops.check_reset_block) 902 if (hw->phy.ops.check_reset_block(hw)) 903 goto out; 904 905 /* 906 * If requested flow control is set to default, set flow control 907 * based on the EEPROM flow control settings. 908 */ 909 if (hw->fc.requested_mode == e1000_fc_default) { 910 ret_val = e1000_set_default_fc_generic(hw); 911 if (ret_val) 912 goto out; 913 } 914 915 /* 916 * Save off the requested flow control mode for use later. Depending 917 * on the link partner's capabilities, we may or may not use this mode. 918 */ 919 hw->fc.current_mode = hw->fc.requested_mode; 920 921 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 922 hw->fc.current_mode); 923 924 /* Call the necessary media_type subroutine to configure the link. */ 925 ret_val = hw->mac.ops.setup_physical_interface(hw); 926 if (ret_val) 927 goto out; 928 929 /* 930 * Initialize the flow control address, type, and PAUSE timer 931 * registers to their default values. This is done even if flow 932 * control is disabled, because it does not hurt anything to 933 * initialize these registers. 934 */ 935 DEBUGOUT("Initializing the Flow Control address,type and timer regs\n"); 936 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 937 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 938 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 939 940 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 941 942 ret_val = e1000_set_fc_watermarks_generic(hw); 943 944 out: 945 return (ret_val); 946 } 947 948 /* 949 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 950 * @hw: pointer to the HW structure 951 * 952 * Configures collision distance and flow control for fiber and serdes 953 * links. Upon successful setup, poll for link. 954 */ 955 s32 956 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 957 { 958 u32 ctrl; 959 s32 ret_val = E1000_SUCCESS; 960 961 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 962 963 ctrl = E1000_READ_REG(hw, E1000_CTRL); 964 965 /* Take the link out of reset */ 966 ctrl &= ~E1000_CTRL_LRST; 967 968 e1000_config_collision_dist_generic(hw); 969 970 ret_val = e1000_commit_fc_settings_generic(hw); 971 if (ret_val) 972 goto out; 973 974 /* 975 * Since auto-negotiation is enabled, take the link out of reset (the 976 * link will be in reset, because we previously reset the chip). This 977 * will restart auto-negotiation. If auto-negotiation is successful 978 * then the link-up status bit will be set and the flow control enable 979 * bits (RFCE and TFCE) will be set according to their negotiated value. 980 */ 981 DEBUGOUT("Auto-negotiation enabled\n"); 982 983 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 984 E1000_WRITE_FLUSH(hw); 985 msec_delay(1); 986 987 /* 988 * For these adapters, the SW definable pin 1 is set when the optics 989 * detect a signal. If we have a signal, then poll for a "Link-Up" 990 * indication. 991 */ 992 if (hw->phy.media_type == e1000_media_type_internal_serdes || 993 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 994 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 995 } else { 996 DEBUGOUT("No signal detected\n"); 997 } 998 999 out: 1000 return (ret_val); 1001 } 1002 1003 /* 1004 * e1000_config_collision_dist_generic - Configure collision distance 1005 * @hw: pointer to the HW structure 1006 * 1007 * Configures the collision distance to the default value and is used 1008 * during link setup. Currently no func pointer exists and all 1009 * implementations are handled in the generic version of this function. 1010 */ 1011 void 1012 e1000_config_collision_dist_generic(struct e1000_hw *hw) 1013 { 1014 u32 tctl; 1015 1016 DEBUGFUNC("e1000_config_collision_dist_generic"); 1017 1018 tctl = E1000_READ_REG(hw, E1000_TCTL); 1019 1020 tctl &= ~E1000_TCTL_COLD; 1021 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1022 1023 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1024 E1000_WRITE_FLUSH(hw); 1025 } 1026 1027 /* 1028 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1029 * @hw: pointer to the HW structure 1030 * 1031 * Polls for link up by reading the status register, if link fails to come 1032 * up with auto-negotiation, then the link is forced if a signal is detected. 1033 */ 1034 s32 1035 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1036 { 1037 struct e1000_mac_info *mac = &hw->mac; 1038 u32 i, status; 1039 s32 ret_val = E1000_SUCCESS; 1040 1041 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1042 1043 /* 1044 * If we have a signal (the cable is plugged in, or assumed true for 1045 * serdes media) then poll for a "Link-Up" indication in the Device 1046 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1047 * seconds (Auto-negotiation should complete in less than 500 1048 * milliseconds even if the other end is doing it in SW). 1049 */ 1050 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1051 msec_delay(10); 1052 status = E1000_READ_REG(hw, E1000_STATUS); 1053 if (status & E1000_STATUS_LU) 1054 break; 1055 } 1056 if (i == FIBER_LINK_UP_LIMIT) { 1057 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1058 mac->autoneg_failed = 1; 1059 /* 1060 * AutoNeg failed to achieve a link, so we'll call 1061 * mac->check_for_link. This routine will force the 1062 * link up if we detect a signal. This will allow us to 1063 * communicate with non-autonegotiating link partners. 1064 */ 1065 ret_val = hw->mac.ops.check_for_link(hw); 1066 if (ret_val) { 1067 DEBUGOUT("Error while checking for link\n"); 1068 goto out; 1069 } 1070 mac->autoneg_failed = 0; 1071 } else { 1072 mac->autoneg_failed = 0; 1073 DEBUGOUT("Valid Link Found\n"); 1074 } 1075 1076 out: 1077 return (ret_val); 1078 } 1079 1080 /* 1081 * e1000_commit_fc_settings_generic - Configure flow control 1082 * @hw: pointer to the HW structure 1083 * 1084 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1085 * base on the flow control settings in e1000_mac_info. 1086 */ 1087 s32 1088 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1089 { 1090 struct e1000_mac_info *mac = &hw->mac; 1091 u32 txcw; 1092 s32 ret_val = E1000_SUCCESS; 1093 1094 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1095 1096 /* 1097 * Check for a software override of the flow control settings, and 1098 * setup the device accordingly. If auto-negotiation is enabled, then 1099 * software will have to set the "PAUSE" bits to the correct value in 1100 * the Transmit Config Word Register (TXCW) and re-start auto- 1101 * negotiation. However, if auto-negotiation is disabled, then 1102 * software will have to manually configure the two flow control enable 1103 * bits in the CTRL register. 1104 * 1105 * The possible values of the "fc" parameter are: 1106 * 0: Flow control is completely disabled 1107 * 1: Rx flow control is enabled (we can receive pause frames, 1108 * but not send pause frames). 1109 * 2: Tx flow control is enabled (we can send pause frames but we 1110 * do not support receiving pause frames). 1111 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1112 */ 1113 switch (hw->fc.current_mode) { 1114 case e1000_fc_none: 1115 /* Flow control completely disabled by a software over-ride. */ 1116 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1117 break; 1118 case e1000_fc_rx_pause: 1119 /* 1120 * Rx Flow control is enabled and Tx Flow control is disabled 1121 * by a software over-ride. Since there really isn't a way to 1122 * advertise that we are capable of Rx Pause ONLY, we will 1123 * advertise that we support both symmetric and asymmetric RX 1124 * PAUSE. Later, we will disable the adapter's ability to send 1125 * PAUSE frames. 1126 */ 1127 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1128 break; 1129 case e1000_fc_tx_pause: 1130 /* 1131 * Tx Flow control is enabled, and Rx Flow control is disabled, 1132 * by a software over-ride. 1133 */ 1134 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1135 break; 1136 case e1000_fc_full: 1137 /* 1138 * Flow control (both Rx and Tx) is enabled by a software 1139 * over-ride. 1140 */ 1141 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1142 break; 1143 default: 1144 DEBUGOUT("Flow control param set incorrectly\n"); 1145 ret_val = -E1000_ERR_CONFIG; 1146 goto out; 1147 } 1148 1149 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1150 mac->txcw = txcw; 1151 1152 out: 1153 return (ret_val); 1154 } 1155 1156 /* 1157 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1158 * @hw: pointer to the HW structure 1159 * 1160 * Sets the flow control high/low threshold (watermark) registers. If 1161 * flow control XON frame transmission is enabled, then set XON frame 1162 * transmission as well. 1163 */ 1164 s32 1165 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1166 { 1167 s32 ret_val = E1000_SUCCESS; 1168 u32 fcrtl = 0, fcrth = 0; 1169 1170 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1171 1172 /* 1173 * Set the flow control receive threshold registers. Normally, 1174 * these registers will be set to a default threshold that may be 1175 * adjusted later by the driver's runtime code. However, if the 1176 * ability to transmit pause frames is not enabled, then these 1177 * registers will be set to 0. 1178 */ 1179 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1180 /* 1181 * We need to set up the Receive Threshold high and low water 1182 * marks as well as (optionally) enabling the transmission of 1183 * XON frames. 1184 */ 1185 fcrtl = hw->fc.low_water; 1186 if (hw->fc.send_xon) 1187 fcrtl |= E1000_FCRTL_XONE; 1188 1189 fcrth = hw->fc.high_water; 1190 } 1191 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1192 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1193 1194 return (ret_val); 1195 } 1196 1197 /* 1198 * e1000_set_default_fc_generic - Set flow control default values 1199 * @hw: pointer to the HW structure 1200 * 1201 * Read the EEPROM for the default values for flow control and store the 1202 * values. 1203 */ 1204 s32 1205 e1000_set_default_fc_generic(struct e1000_hw *hw) 1206 { 1207 s32 ret_val = E1000_SUCCESS; 1208 u16 nvm_data; 1209 1210 DEBUGFUNC("e1000_set_default_fc_generic"); 1211 1212 /* 1213 * Read and store word 0x0F of the EEPROM. This word contains bits 1214 * that determine the hardware's default PAUSE (flow control) mode, 1215 * a bit that determines whether the HW defaults to enabling or 1216 * disabling auto-negotiation, and the direction of the 1217 * SW defined pins. If there is no SW over-ride of the flow 1218 * control setting, then the variable hw->fc will 1219 * be initialized based on a value in the EEPROM. 1220 */ 1221 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1222 1223 if (ret_val) { 1224 DEBUGOUT("NVM Read Error\n"); 1225 goto out; 1226 } 1227 1228 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1229 hw->fc.requested_mode = e1000_fc_none; 1230 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1231 NVM_WORD0F_ASM_DIR) 1232 hw->fc.requested_mode = e1000_fc_tx_pause; 1233 else 1234 hw->fc.requested_mode = e1000_fc_full; 1235 1236 out: 1237 return (ret_val); 1238 } 1239 1240 /* 1241 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1242 * @hw: pointer to the HW structure 1243 * 1244 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1245 * device control register to reflect the adapter settings. TFCE and RFCE 1246 * need to be explicitly set by software when a copper PHY is used because 1247 * autonegotiation is managed by the PHY rather than the MAC. Software must 1248 * also configure these bits when link is forced on a fiber connection. 1249 */ 1250 s32 1251 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1252 { 1253 u32 ctrl; 1254 s32 ret_val = E1000_SUCCESS; 1255 1256 DEBUGFUNC("e1000_force_mac_fc_generic"); 1257 1258 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1259 1260 /* 1261 * Because we didn't get link via the internal auto-negotiation 1262 * mechanism (we either forced link or we got link via PHY 1263 * auto-neg), we have to manually enable/disable transmit an 1264 * receive flow control. 1265 * 1266 * The "Case" statement below enables/disable flow control 1267 * according to the "hw->fc.current_mode" parameter. 1268 * 1269 * The possible values of the "fc" parameter are: 1270 * 0: Flow control is completely disabled 1271 * 1: Rx flow control is enabled (we can receive pause 1272 * frames but not send pause frames). 1273 * 2: Tx flow control is enabled (we can send pause frames 1274 * frames but we do not receive pause frames). 1275 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1276 * other: No other values should be possible at this point. 1277 */ 1278 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1279 1280 switch (hw->fc.current_mode) { 1281 case e1000_fc_none: 1282 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1283 break; 1284 case e1000_fc_rx_pause: 1285 ctrl &= (~E1000_CTRL_TFCE); 1286 ctrl |= E1000_CTRL_RFCE; 1287 break; 1288 case e1000_fc_tx_pause: 1289 ctrl &= (~E1000_CTRL_RFCE); 1290 ctrl |= E1000_CTRL_TFCE; 1291 break; 1292 case e1000_fc_full: 1293 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1294 break; 1295 default: 1296 DEBUGOUT("Flow control param set incorrectly\n"); 1297 ret_val = -E1000_ERR_CONFIG; 1298 goto out; 1299 } 1300 1301 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1302 1303 out: 1304 return (ret_val); 1305 } 1306 1307 /* 1308 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1309 * @hw: pointer to the HW structure 1310 * 1311 * Checks the status of auto-negotiation after link up to ensure that the 1312 * speed and duplex were not forced. If the link needed to be forced, then 1313 * flow control needs to be forced also. If auto-negotiation is enabled 1314 * and did not fail, then we configure flow control based on our link 1315 * partner. 1316 */ 1317 s32 1318 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1319 { 1320 struct e1000_mac_info *mac = &hw->mac; 1321 s32 ret_val = E1000_SUCCESS; 1322 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1323 u16 speed, duplex; 1324 1325 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1326 1327 /* 1328 * Check for the case where we have fiber media and auto-neg failed 1329 * so we had to force link. In this case, we need to force the 1330 * configuration of the MAC to match the "fc" parameter. 1331 */ 1332 if (mac->autoneg_failed) { 1333 if (hw->phy.media_type == e1000_media_type_fiber || 1334 hw->phy.media_type == e1000_media_type_internal_serdes) 1335 ret_val = e1000_force_mac_fc_generic(hw); 1336 } else { 1337 if (hw->phy.media_type == e1000_media_type_copper) 1338 ret_val = e1000_force_mac_fc_generic(hw); 1339 } 1340 1341 if (ret_val) { 1342 DEBUGOUT("Error forcing flow control settings\n"); 1343 goto out; 1344 } 1345 1346 /* 1347 * Check for the case where we have copper media and auto-neg is 1348 * enabled. In this case, we need to check and see if Auto-Neg 1349 * has completed, and if so, how the PHY and link partner has 1350 * flow control configured. 1351 */ 1352 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1353 /* 1354 * Read the MII Status Register and check to see if AutoNeg 1355 * has completed. We read this twice because this reg has 1356 * some "sticky" (latched) bits. 1357 */ 1358 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1359 if (ret_val) 1360 goto out; 1361 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1362 if (ret_val) 1363 goto out; 1364 1365 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1366 DEBUGOUT("Copper PHY and Auto Neg " 1367 "has not completed.\n"); 1368 goto out; 1369 } 1370 1371 /* 1372 * The AutoNeg process has completed, so we now need to 1373 * read both the Auto Negotiation Advertisement 1374 * Register (Address 4) and the Auto_Negotiation Base 1375 * Page Ability Register (Address 5) to determine how 1376 * flow control was negotiated. 1377 */ 1378 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1379 &mii_nway_adv_reg); 1380 if (ret_val) 1381 goto out; 1382 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1383 &mii_nway_lp_ability_reg); 1384 if (ret_val) 1385 goto out; 1386 1387 /* 1388 * Two bits in the Auto Negotiation Advertisement Register 1389 * (Address 4) and two bits in the Auto Negotiation Base 1390 * Page Ability Register (Address 5) determine flow control 1391 * for both the PHY and the link partner. The following 1392 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1393 * 1999, describes these PAUSE resolution bits and how flow 1394 * control is determined based upon these settings. 1395 * NOTE: DC = Don't Care 1396 * 1397 * LOCAL DEVICE | LINK PARTNER 1398 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1399 * ------|---------|-------|---------|-------------------- 1400 * 0 | 0 | DC | DC | e1000_fc_none 1401 * 0 | 1 | 0 | DC | e1000_fc_none 1402 * 0 | 1 | 1 | 0 | e1000_fc_none 1403 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1404 * 1 | 0 | 0 | DC | e1000_fc_none 1405 * 1 | DC | 1 | DC | e1000_fc_full 1406 * 1 | 1 | 0 | 0 | e1000_fc_none 1407 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1408 * 1409 * Are both PAUSE bits set to 1? If so, this implies 1410 * Symmetric Flow Control is enabled at both ends. The 1411 * ASM_DIR bits are irrelevant per the spec. 1412 * 1413 * For Symmetric Flow Control: 1414 * 1415 * LOCAL DEVICE | LINK PARTNER 1416 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1417 * ------|---------|-------|---------|-------------------- 1418 * 1 | DC | 1 | DC | E1000_fc_full 1419 * 1420 */ 1421 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1422 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1423 /* 1424 * Now we need to check if the user selected Rx ONLY 1425 * of pause frames. In this case, we had to advertise 1426 * FULL flow control because we could not advertise RX 1427 * ONLY. Hence, we must now check to see if we need to 1428 * turn OFF the TRANSMISSION of PAUSE frames. 1429 */ 1430 if (hw->fc.requested_mode == e1000_fc_full) { 1431 hw->fc.current_mode = e1000_fc_full; 1432 DEBUGOUT("Flow Control = FULL.\r\n"); 1433 } else { 1434 hw->fc.current_mode = e1000_fc_rx_pause; 1435 DEBUGOUT("Flow Control = " 1436 "RX PAUSE frames only.\r\n"); 1437 } 1438 } 1439 /* 1440 * For receiving PAUSE frames ONLY. 1441 * 1442 * LOCAL DEVICE | LINK PARTNER 1443 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1444 * ------|---------|-------|---------|-------------------- 1445 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1446 */ 1447 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1448 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1449 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1450 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1451 hw->fc.current_mode = e1000_fc_tx_pause; 1452 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1453 } 1454 /* 1455 * For transmitting PAUSE frames ONLY. 1456 * 1457 * LOCAL DEVICE | LINK PARTNER 1458 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1459 * ------|---------|-------|---------|-------------------- 1460 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1461 */ 1462 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1463 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1464 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1465 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1466 hw->fc.current_mode = e1000_fc_rx_pause; 1467 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1468 } else { 1469 /* 1470 * Per the IEEE spec, at this point flow control 1471 * should be disabled. 1472 */ 1473 hw->fc.current_mode = e1000_fc_none; 1474 DEBUGOUT("Flow Control = NONE.\r\n"); 1475 } 1476 1477 /* 1478 * Now we need to do one last check... If we auto- 1479 * negotiated to HALF DUPLEX, flow control should not be 1480 * enabled per IEEE 802.3 spec. 1481 */ 1482 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1483 if (ret_val) { 1484 DEBUGOUT("Error getting link speed and duplex\n"); 1485 goto out; 1486 } 1487 1488 if (duplex == HALF_DUPLEX) 1489 hw->fc.current_mode = e1000_fc_none; 1490 1491 /* 1492 * Now we call a subroutine to actually force the MAC 1493 * controller to use the correct flow control settings. 1494 */ 1495 ret_val = e1000_force_mac_fc_generic(hw); 1496 if (ret_val) { 1497 DEBUGOUT("Error forcing flow control settings\n"); 1498 goto out; 1499 } 1500 } 1501 1502 out: 1503 return (ret_val); 1504 } 1505 1506 /* 1507 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1508 * @hw: pointer to the HW structure 1509 * @speed: stores the current speed 1510 * @duplex: stores the current duplex 1511 * 1512 * Read the status register for the current speed/duplex and store the current 1513 * speed and duplex for copper connections. 1514 */ 1515 s32 1516 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1517 u16 *duplex) 1518 { 1519 u32 status; 1520 1521 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1522 1523 status = E1000_READ_REG(hw, E1000_STATUS); 1524 if (status & E1000_STATUS_SPEED_1000) { 1525 *speed = SPEED_1000; 1526 DEBUGOUT("1000 Mbs, "); 1527 } else if (status & E1000_STATUS_SPEED_100) { 1528 *speed = SPEED_100; 1529 DEBUGOUT("100 Mbs, "); 1530 } else { 1531 *speed = SPEED_10; 1532 DEBUGOUT("10 Mbs, "); 1533 } 1534 1535 if (status & E1000_STATUS_FD) { 1536 *duplex = FULL_DUPLEX; 1537 DEBUGOUT("Full Duplex\n"); 1538 } else { 1539 *duplex = HALF_DUPLEX; 1540 DEBUGOUT("Half Duplex\n"); 1541 } 1542 1543 return (E1000_SUCCESS); 1544 } 1545 1546 /* 1547 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1548 * @hw: pointer to the HW structure 1549 * @speed: stores the current speed 1550 * @duplex: stores the current duplex 1551 * 1552 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1553 * for fiber/serdes links. 1554 */ 1555 s32 1556 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1557 u16 *speed, u16 *duplex) 1558 { 1559 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1560 UNREFERENCED_1PARAMETER(hw); 1561 1562 *speed = SPEED_1000; 1563 *duplex = FULL_DUPLEX; 1564 1565 return (E1000_SUCCESS); 1566 } 1567 1568 /* 1569 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1570 * @hw: pointer to the HW structure 1571 * 1572 * Acquire the HW semaphore to access the PHY or NVM 1573 */ 1574 s32 1575 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1576 { 1577 u32 swsm; 1578 s32 ret_val = E1000_SUCCESS; 1579 s32 timeout = hw->nvm.word_size + 1; 1580 s32 i = 0; 1581 1582 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1583 1584 /* Get the SW semaphore */ 1585 while (i < timeout) { 1586 swsm = E1000_READ_REG(hw, E1000_SWSM); 1587 if (!(swsm & E1000_SWSM_SMBI)) 1588 break; 1589 1590 usec_delay(50); 1591 i++; 1592 } 1593 1594 if (i == timeout) { 1595 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1596 ret_val = -E1000_ERR_NVM; 1597 goto out; 1598 } 1599 1600 /* Get the FW semaphore. */ 1601 for (i = 0; i < timeout; i++) { 1602 swsm = E1000_READ_REG(hw, E1000_SWSM); 1603 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1604 1605 /* Semaphore acquired if bit latched */ 1606 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1607 break; 1608 1609 usec_delay(50); 1610 } 1611 1612 if (i == timeout) { 1613 /* Release semaphores */ 1614 e1000_put_hw_semaphore_generic(hw); 1615 DEBUGOUT("Driver can't access the NVM\n"); 1616 ret_val = -E1000_ERR_NVM; 1617 goto out; 1618 } 1619 1620 out: 1621 return (ret_val); 1622 } 1623 1624 /* 1625 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1626 * @hw: pointer to the HW structure 1627 * 1628 * Release hardware semaphore used to access the PHY or NVM 1629 */ 1630 void 1631 e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1632 { 1633 u32 swsm; 1634 1635 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1636 1637 swsm = E1000_READ_REG(hw, E1000_SWSM); 1638 1639 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1640 1641 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1642 } 1643 1644 /* 1645 * e1000_get_auto_rd_done_generic - Check for auto read completion 1646 * @hw: pointer to the HW structure 1647 * 1648 * Check EEPROM for Auto Read done bit. 1649 */ 1650 s32 1651 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1652 { 1653 s32 i = 0; 1654 s32 ret_val = E1000_SUCCESS; 1655 1656 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1657 1658 while (i < AUTO_READ_DONE_TIMEOUT) { 1659 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1660 break; 1661 msec_delay(1); 1662 i++; 1663 } 1664 1665 if (i == AUTO_READ_DONE_TIMEOUT) { 1666 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1667 ret_val = -E1000_ERR_RESET; 1668 goto out; 1669 } 1670 1671 out: 1672 return (ret_val); 1673 } 1674 1675 /* 1676 * e1000_valid_led_default_generic - Verify a valid default LED config 1677 * @hw: pointer to the HW structure 1678 * @data: pointer to the NVM (EEPROM) 1679 * 1680 * Read the EEPROM for the current default LED configuration. If the 1681 * LED configuration is not valid, set to a valid LED configuration. 1682 */ 1683 s32 1684 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1685 { 1686 s32 ret_val; 1687 1688 DEBUGFUNC("e1000_valid_led_default_generic"); 1689 1690 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1691 if (ret_val) { 1692 DEBUGOUT("NVM Read Error\n"); 1693 goto out; 1694 } 1695 1696 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1697 *data = ID_LED_DEFAULT; 1698 1699 out: 1700 return (ret_val); 1701 } 1702 1703 /* 1704 * e1000_id_led_init_generic - 1705 * @hw: pointer to the HW structure 1706 * 1707 */ 1708 s32 1709 e1000_id_led_init_generic(struct e1000_hw *hw) 1710 { 1711 struct e1000_mac_info *mac = &hw->mac; 1712 s32 ret_val; 1713 const u32 ledctl_mask = 0x000000FF; 1714 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1715 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1716 u16 data, i, temp; 1717 const u16 led_mask = 0x0F; 1718 1719 DEBUGFUNC("e1000_id_led_init_generic"); 1720 1721 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1722 if (ret_val) 1723 goto out; 1724 1725 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1726 mac->ledctl_mode1 = mac->ledctl_default; 1727 mac->ledctl_mode2 = mac->ledctl_default; 1728 1729 for (i = 0; i < 4; i++) { 1730 temp = (data >> (i << 2)) & led_mask; 1731 switch (temp) { 1732 case ID_LED_ON1_DEF2: 1733 case ID_LED_ON1_ON2: 1734 case ID_LED_ON1_OFF2: 1735 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1736 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1737 break; 1738 case ID_LED_OFF1_DEF2: 1739 case ID_LED_OFF1_ON2: 1740 case ID_LED_OFF1_OFF2: 1741 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1742 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1743 break; 1744 default: 1745 /* Do nothing */ 1746 break; 1747 } 1748 switch (temp) { 1749 case ID_LED_DEF1_ON2: 1750 case ID_LED_ON1_ON2: 1751 case ID_LED_OFF1_ON2: 1752 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1753 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1754 break; 1755 case ID_LED_DEF1_OFF2: 1756 case ID_LED_ON1_OFF2: 1757 case ID_LED_OFF1_OFF2: 1758 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1759 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1760 break; 1761 default: 1762 /* Do nothing */ 1763 break; 1764 } 1765 } 1766 1767 out: 1768 return (ret_val); 1769 } 1770 1771 /* 1772 * e1000_setup_led_generic - Configures SW controllable LED 1773 * @hw: pointer to the HW structure 1774 * 1775 * This prepares the SW controllable LED for use and saves the current state 1776 * of the LED so it can be later restored. 1777 */ 1778 s32 1779 e1000_setup_led_generic(struct e1000_hw *hw) 1780 { 1781 u32 ledctl; 1782 s32 ret_val = E1000_SUCCESS; 1783 1784 DEBUGFUNC("e1000_setup_led_generic"); 1785 1786 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1787 ret_val = -E1000_ERR_CONFIG; 1788 goto out; 1789 } 1790 1791 if (hw->phy.media_type == e1000_media_type_fiber) { 1792 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1793 hw->mac.ledctl_default = ledctl; 1794 /* Turn off LED0 */ 1795 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1796 E1000_LEDCTL_LED0_BLINK | 1797 E1000_LEDCTL_LED0_MODE_MASK); 1798 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1799 E1000_LEDCTL_LED0_MODE_SHIFT); 1800 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1801 } else if (hw->phy.media_type == e1000_media_type_copper) { 1802 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1803 } 1804 1805 out: 1806 return (ret_val); 1807 } 1808 1809 /* 1810 * e1000_cleanup_led_generic - Set LED config to default operation 1811 * @hw: pointer to the HW structure 1812 * 1813 * Remove the current LED configuration and set the LED configuration 1814 * to the default value, saved from the EEPROM. 1815 */ 1816 s32 1817 e1000_cleanup_led_generic(struct e1000_hw *hw) 1818 { 1819 s32 ret_val = E1000_SUCCESS; 1820 1821 DEBUGFUNC("e1000_cleanup_led_generic"); 1822 1823 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1824 ret_val = -E1000_ERR_CONFIG; 1825 goto out; 1826 } 1827 1828 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1829 1830 out: 1831 return (ret_val); 1832 } 1833 1834 /* 1835 * e1000_blink_led_generic - Blink LED 1836 * @hw: pointer to the HW structure 1837 * 1838 * Blink the LEDs which are set to be on. 1839 */ 1840 s32 1841 e1000_blink_led_generic(struct e1000_hw *hw) 1842 { 1843 u32 ledctl_blink = 0; 1844 u32 i; 1845 1846 DEBUGFUNC("e1000_blink_led_generic"); 1847 1848 if (hw->phy.media_type == e1000_media_type_fiber) { 1849 /* always blink LED0 for PCI-E fiber */ 1850 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1851 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1852 } else { 1853 /* 1854 * set the blink bit for each LED that's "on" (0x0E) 1855 * in ledctl_mode2 1856 */ 1857 ledctl_blink = hw->mac.ledctl_mode2; 1858 for (i = 0; i < 4; i++) 1859 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1860 E1000_LEDCTL_MODE_LED_ON) 1861 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1862 (i * 8)); 1863 } 1864 1865 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1866 1867 return (E1000_SUCCESS); 1868 } 1869 1870 /* 1871 * e1000_led_on_generic - Turn LED on 1872 * @hw: pointer to the HW structure 1873 * 1874 * Turn LED on. 1875 */ 1876 s32 1877 e1000_led_on_generic(struct e1000_hw *hw) 1878 { 1879 u32 ctrl; 1880 1881 DEBUGFUNC("e1000_led_on_generic"); 1882 1883 switch (hw->phy.media_type) { 1884 case e1000_media_type_fiber: 1885 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1886 ctrl &= ~E1000_CTRL_SWDPIN0; 1887 ctrl |= E1000_CTRL_SWDPIO0; 1888 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1889 break; 1890 case e1000_media_type_copper: 1891 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1892 break; 1893 default: 1894 break; 1895 } 1896 1897 return (E1000_SUCCESS); 1898 } 1899 1900 /* 1901 * e1000_led_off_generic - Turn LED off 1902 * @hw: pointer to the HW structure 1903 * 1904 * Turn LED off. 1905 */ 1906 s32 1907 e1000_led_off_generic(struct e1000_hw *hw) 1908 { 1909 u32 ctrl; 1910 1911 DEBUGFUNC("e1000_led_off_generic"); 1912 1913 switch (hw->phy.media_type) { 1914 case e1000_media_type_fiber: 1915 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1916 ctrl |= E1000_CTRL_SWDPIN0; 1917 ctrl |= E1000_CTRL_SWDPIO0; 1918 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1919 break; 1920 case e1000_media_type_copper: 1921 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1922 break; 1923 default: 1924 break; 1925 } 1926 1927 return (E1000_SUCCESS); 1928 } 1929 1930 /* 1931 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1932 * @hw: pointer to the HW structure 1933 * @no_snoop: bitmap of snoop events 1934 * 1935 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1936 */ 1937 void 1938 e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1939 { 1940 u32 gcr; 1941 1942 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1943 1944 if (hw->bus.type != e1000_bus_type_pci_express) 1945 return; 1946 1947 if (no_snoop) { 1948 gcr = E1000_READ_REG(hw, E1000_GCR); 1949 gcr &= ~(PCIE_NO_SNOOP_ALL); 1950 gcr |= no_snoop; 1951 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1952 } 1953 } 1954 1955 /* 1956 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1957 * @hw: pointer to the HW structure 1958 * 1959 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1960 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1961 * the master requests to be disabled. 1962 * 1963 * Disables PCI-Express master access and verifies there are no pending 1964 * requests. 1965 */ 1966 s32 1967 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1968 { 1969 u32 ctrl; 1970 s32 timeout = MASTER_DISABLE_TIMEOUT; 1971 s32 ret_val = E1000_SUCCESS; 1972 1973 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1974 1975 if (hw->bus.type != e1000_bus_type_pci_express) 1976 goto out; 1977 1978 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1979 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1980 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1981 1982 while (timeout) { 1983 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1984 E1000_STATUS_GIO_MASTER_ENABLE)) 1985 break; 1986 usec_delay(100); 1987 timeout--; 1988 } 1989 1990 if (!timeout) { 1991 DEBUGOUT("Master requests are pending.\n"); 1992 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1993 goto out; 1994 } 1995 1996 out: 1997 return (ret_val); 1998 } 1999 2000 /* 2001 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2002 * @hw: pointer to the HW structure 2003 * 2004 * Reset the Adaptive Interframe Spacing throttle to default values. 2005 */ 2006 void 2007 e1000_reset_adaptive_generic(struct e1000_hw *hw) 2008 { 2009 struct e1000_mac_info *mac = &hw->mac; 2010 2011 DEBUGFUNC("e1000_reset_adaptive_generic"); 2012 2013 if (!mac->adaptive_ifs) { 2014 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2015 return; 2016 } 2017 2018 mac->current_ifs_val = 0; 2019 mac->ifs_min_val = IFS_MIN; 2020 mac->ifs_max_val = IFS_MAX; 2021 mac->ifs_step_size = IFS_STEP; 2022 mac->ifs_ratio = IFS_RATIO; 2023 2024 mac->in_ifs_mode = false; 2025 E1000_WRITE_REG(hw, E1000_AIT, 0); 2026 } 2027 2028 /* 2029 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2030 * @hw: pointer to the HW structure 2031 * 2032 * Update the Adaptive Interframe Spacing Throttle value based on the 2033 * time between transmitted packets and time between collisions. 2034 */ 2035 void 2036 e1000_update_adaptive_generic(struct e1000_hw *hw) 2037 { 2038 struct e1000_mac_info *mac = &hw->mac; 2039 2040 DEBUGFUNC("e1000_update_adaptive_generic"); 2041 2042 if (!mac->adaptive_ifs) { 2043 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2044 return; 2045 } 2046 2047 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2048 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2049 mac->in_ifs_mode = true; 2050 if (mac->current_ifs_val < mac->ifs_max_val) { 2051 if (!mac->current_ifs_val) 2052 mac->current_ifs_val = mac->ifs_min_val; 2053 else 2054 mac->current_ifs_val += 2055 mac->ifs_step_size; 2056 E1000_WRITE_REG(hw, E1000_AIT, 2057 mac->current_ifs_val); 2058 } 2059 } 2060 } else { 2061 if (mac->in_ifs_mode && 2062 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2063 mac->current_ifs_val = 0; 2064 mac->in_ifs_mode = false; 2065 E1000_WRITE_REG(hw, E1000_AIT, 0); 2066 } 2067 } 2068 } 2069 2070 /* 2071 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2072 * @hw: pointer to the HW structure 2073 * 2074 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2075 * set, which is forced to MDI mode only. 2076 */ 2077 s32 2078 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2079 { 2080 s32 ret_val = E1000_SUCCESS; 2081 2082 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2083 2084 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2085 DEBUGOUT("Invalid MDI setting detected\n"); 2086 hw->phy.mdix = 1; 2087 ret_val = -E1000_ERR_CONFIG; 2088 goto out; 2089 } 2090 2091 out: 2092 return (ret_val); 2093 } 2094 2095 /* 2096 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2097 * @hw: pointer to the HW structure 2098 * @reg: 32bit register offset such as E1000_SCTL 2099 * @offset: register offset to write to 2100 * @data: data to write at register offset 2101 * 2102 * Writes an address/data control type register. There are several of these 2103 * and they all have the format address << 8 | data and bit 31 is polled for 2104 * completion. 2105 */ 2106 s32 2107 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2108 u32 offset, u8 data) 2109 { 2110 u32 i, regvalue = 0; 2111 s32 ret_val = E1000_SUCCESS; 2112 2113 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2114 2115 /* Set up the address and data */ 2116 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2117 E1000_WRITE_REG(hw, reg, regvalue); 2118 2119 /* Poll the ready bit to see if the MDI read completed */ 2120 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2121 usec_delay(5); 2122 regvalue = E1000_READ_REG(hw, reg); 2123 if (regvalue & E1000_GEN_CTL_READY) 2124 break; 2125 } 2126 if (!(regvalue & E1000_GEN_CTL_READY)) { 2127 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2128 ret_val = -E1000_ERR_PHY; 2129 goto out; 2130 } 2131 2132 out: 2133 return (ret_val); 2134 } 2135