1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 */ 29 30 /* IntelVersion: 1.88.2.1 v3_3_14_3_BHSW1 */ 31 32 #ifndef _IGB_82575_H 33 #define _IGB_82575_H 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ 40 (ID_LED_DEF1_DEF2 << 8) | \ 41 (ID_LED_DEF1_DEF2 << 4) | \ 42 (ID_LED_OFF1_ON2)) 43 44 /* 45 * Receive Address Register Count 46 * Number of high/low register pairs in the RAR. The RAR (Receive Address 47 * Registers) holds the directed and multicast addresses that we monitor. 48 * These entries are also used for MAC-based filtering. 49 */ 50 /* 51 * For 82576, there are an additional set of RARs that begin at an offset 52 * separate from the first set of RARs. 53 */ 54 #define E1000_RAR_ENTRIES_82575 16 55 #define E1000_RAR_ENTRIES_82576 24 56 #define E1000_RAR_ENTRIES_82580 24 57 #define E1000_SW_SYNCH_MB 0x00000100 58 #define E1000_STAT_DEV_RST_SET 0x00100000 59 #define E1000_CTRL_DEV_RST 0x20000000 60 61 #ifdef E1000_BIT_FIELDS 62 struct e1000_adv_data_desc { 63 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 64 union { 65 u32 data; 66 struct { 67 u32 datalen :16; /* Data buffer length */ 68 u32 rsvd :4; 69 u32 dtyp :4; /* Descriptor type */ 70 u32 dcmd :8; /* Descriptor command */ 71 } config; 72 } lower; 73 union { 74 u32 data; 75 struct { 76 u32 status :4; /* Descriptor status */ 77 u32 idx :4; 78 u32 popts :6; /* Packet Options */ 79 u32 paylen :18; /* Payload length */ 80 } options; 81 } upper; 82 }; 83 84 #define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */ 85 #define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */ 86 #define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */ 87 #define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */ 88 #define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */ 89 #define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */ 90 #define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */ 91 #define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */ 92 #define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */ 93 #define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */ 94 #define E1000_ADV_DCMD_RS 0x8 /* Report Status */ 95 #define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */ 96 #define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */ 97 /* Extended Device Control */ 98 #define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */ 99 100 struct e1000_adv_context_desc { 101 union { 102 u32 ip_config; 103 struct { 104 u32 iplen :9; 105 u32 maclen :7; 106 u32 vlan_tag :16; 107 } fields; 108 } ip_setup; 109 u32 seq_num; 110 union { 111 u64 l4_config; 112 struct { 113 u32 mkrloc :9; 114 u32 tucmd :11; 115 u32 dtyp :4; 116 u32 adv :8; 117 u32 rsvd :4; 118 u32 idx :4; 119 u32 l4len :8; 120 u32 mss :16; 121 } fields; 122 } l4_setup; 123 }; 124 #endif 125 126 /* SRRCTL bit definitions */ 127 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 128 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 129 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 130 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 131 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 132 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 133 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 134 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 135 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 136 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 137 #define E1000_SRRCTL_TIMESTAMP 0x40000000 138 #define E1000_SRRCTL_DROP_EN 0x80000000 139 140 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 141 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 142 143 #define E1000_TX_HEAD_WB_ENABLE 0x1 144 #define E1000_TX_SEQNUM_WB_ENABLE 0x2 145 146 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 147 #define E1000_MRQC_ENABLE_VMDQ 0x00000003 148 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x80000000 149 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 150 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 151 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 152 #define E1000_MRQC_ENABLE_RSS_8Q 0x00000002 153 154 #define E1000_VMRCTL_MIRROR_PORT_SHIFT 8 155 #define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT) 156 #define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) 157 #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) 158 #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) 159 160 #define E1000_EICR_TX_QUEUE ( \ 161 E1000_EICR_TX_QUEUE0 | \ 162 E1000_EICR_TX_QUEUE1 | \ 163 E1000_EICR_TX_QUEUE2 | \ 164 E1000_EICR_TX_QUEUE3) 165 166 #define E1000_EICR_RX_QUEUE ( \ 167 E1000_EICR_RX_QUEUE0 | \ 168 E1000_EICR_RX_QUEUE1 | \ 169 E1000_EICR_RX_QUEUE2 | \ 170 E1000_EICR_RX_QUEUE3) 171 172 #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE 173 #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE 174 175 #define EIMS_ENABLE_MASK ( \ 176 E1000_EIMS_RX_QUEUE | \ 177 E1000_EIMS_TX_QUEUE | \ 178 E1000_EIMS_TCP_TIMER | \ 179 E1000_EIMS_OTHER) 180 181 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 182 #define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 183 #define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 184 #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 185 #define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 186 #define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 187 #define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 188 #define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 189 #define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 190 #define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 191 #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 192 193 /* Receive Descriptor - Advanced */ 194 union e1000_adv_rx_desc { 195 struct { 196 __le64 pkt_addr; /* Packet buffer address */ 197 __le64 hdr_addr; /* Header buffer address */ 198 } read; 199 struct { 200 struct { 201 union { 202 __le32 data; 203 struct { 204 /* RSS type, Packet type */ 205 __le16 pkt_info; 206 /* Split Header, header buffer length */ 207 __le16 hdr_info; 208 } hs_rss; 209 } lo_dword; 210 union { 211 __le32 rss; /* RSS Hash */ 212 struct { 213 __le16 ip_id; /* IP id */ 214 __le16 csum; /* Packet Checksum */ 215 } csum_ip; 216 } hi_dword; 217 } lower; 218 struct { 219 __le32 status_error; /* ext status/error */ 220 __le16 length; /* Packet length */ 221 __le16 vlan; /* VLAN tag */ 222 } upper; 223 } wb; /* writeback */ 224 }; 225 226 #define E1000_RXDADV_RSSTYPE_MASK 0x0000000F 227 #define E1000_RXDADV_RSSTYPE_SHIFT 12 228 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 229 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 230 #define E1000_RXDADV_SPLITHEADER_EN 0x00001000 231 #define E1000_RXDADV_SPH 0x8000 232 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 233 #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 234 #define E1000_RXDADV_ERR_HBO 0x00800000 235 236 /* RSS Hash results */ 237 #define E1000_RXDADV_RSSTYPE_NONE 0x00000000 238 #define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 239 #define E1000_RXDADV_RSSTYPE_IPV4 0x00000002 240 #define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 241 #define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 242 #define E1000_RXDADV_RSSTYPE_IPV6 0x00000005 243 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 244 #define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 245 #define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 246 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 247 248 /* RSS Packet Types as indicated in the receive descriptor */ 249 #define E1000_RXDADV_PKTTYPE_NONE 0x00000000 250 #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 251 #define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 252 #define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 253 #define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 254 #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 255 #define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 256 #define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 257 #define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 258 259 #define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 260 #define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 261 #define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 262 #define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 263 #define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 264 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 265 266 /* LinkSec results */ 267 /* Security Processing bit Indication */ 268 #define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 269 #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 270 #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 271 #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 272 #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 273 274 #define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 275 #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 276 #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 277 #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 278 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 279 280 /* Transmit Descriptor - Advanced */ 281 union e1000_adv_tx_desc { 282 struct { 283 __le64 buffer_addr; /* Address of descriptor's data buf */ 284 __le32 cmd_type_len; 285 __le32 olinfo_status; 286 } read; 287 struct { 288 __le64 rsvd; /* Reserved */ 289 __le32 nxtseq_seed; 290 __le32 status; 291 } wb; 292 }; 293 294 /* Adv Transmit Descriptor Config Masks */ 295 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 296 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 297 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 298 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 299 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 300 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 301 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 302 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 303 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 304 #define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on packet */ 305 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ 306 #define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */ 307 #define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 308 #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 309 #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 310 #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 311 /* 1st&Last TSO-full iSCSI PDU */ 312 #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 313 #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 314 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 315 316 /* Context descriptors */ 317 struct e1000_adv_tx_context_desc { 318 __le32 vlan_macip_lens; 319 __le32 seqnum_seed; 320 __le32 type_tucmd_mlhl; 321 __le32 mss_l4len_idx; 322 }; 323 324 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 325 #define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 326 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 327 #define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 328 #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 329 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 330 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 331 #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 332 /* IPSec Encrypt Enable for ESP */ 333 #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 334 /* Req requires Markers and CRC */ 335 #define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 336 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 337 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 338 /* Adv ctxt IPSec SA IDX mask */ 339 #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF 340 /* Adv ctxt IPSec ESP len mask */ 341 #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF 342 343 /* Additional Transmit Descriptor Control definitions */ 344 /* Enable specific Tx Queue */ 345 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 346 /* Tx Desc. write-back flushing */ 347 #define E1000_TXDCTL_SWFLSH 0x04000000 348 /* Tx Queue Arbitration Priority 0=low, 1=high */ 349 #define E1000_TXDCTL_PRIORITY 0x08000000 350 351 /* Additional Receive Descriptor Control definitions */ 352 /* Enable specific Rx Queue */ 353 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 354 /* Rx Desc. write-back flushing */ 355 #define E1000_RXDCTL_SWFLSH 0x04000000 356 357 /* Direct Cache Access (DCA) definitions */ 358 #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 359 #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 360 361 #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 362 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 363 364 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 365 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 366 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 367 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 368 369 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 370 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 371 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 372 373 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 374 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 375 #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */ 376 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */ 377 378 /* Additional interrupt register bit definitions */ 379 #define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */ 380 #define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 381 #define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 382 383 /* ETQF register bit definitions */ 384 #define E1000_ETQF_FILTER_ENABLE (1 << 26) 385 #define E1000_ETQF_IMM_INT (1 << 29) 386 #define E1000_ETQF_1588 (1 << 30) 387 #define E1000_ETQF_QUEUE_ENABLE (1 << 31) 388 /* 389 * ETQF filter list: one static filter per filter consumer. This is 390 * to avoid filter collisions later. Add new filters 391 * here!! 392 * 393 * Current filters: 394 * EAPOL 802.1x (0x888e): Filter 0 395 */ 396 #define E1000_ETQF_FILTER_EAPOL 0 397 398 #define E1000_FTQF_VF_BP 0x00008000 399 #define E1000_FTQF_1588_TIME_STAMP 0x08000000 400 #define E1000_FTQF_MASK 0xF0000000 401 #define E1000_FTQF_MASK_PROTO_BP 0x10000000 402 #define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 403 #define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 404 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 405 406 #define E1000_NVM_APME_82575 0x0400 407 #define MAX_NUM_VFS 8 408 409 /* Per VF MAC spoof control */ 410 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF 411 /* Per VF VLAN spoof control */ 412 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 413 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 414 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 415 #define E1000_DTXSWC_LLE_SHIFT 16 416 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN ((u32)1 << 31) /* global VF LB enable */ 417 418 /* Easy defines for setting default pool, would normally be left a zero */ 419 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 420 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 421 422 /* Other useful VMD_CTL register defines */ 423 #define E1000_VT_CTL_IGNORE_MAC (1 << 28) 424 #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) 425 #define E1000_VT_CTL_VM_REPL_EN (1 << 30) 426 427 /* Per VM Offload register setup */ 428 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 429 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ 430 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ 431 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 432 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 433 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 434 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 435 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 436 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 437 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 438 439 #define E1000_VLVF_ARRAY_SIZE 32 440 #define E1000_VLVF_VLANID_MASK 0x00000FFF 441 #define E1000_VLVF_POOLSEL_SHIFT 12 442 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) 443 #define E1000_VLVF_LVLAN 0x00100000 444 #define E1000_VLVF_VLANID_ENABLE 0x80000000 445 446 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 447 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 448 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 449 450 #define E1000_IOVCTL 0x05BBC 451 #define E1000_IOVCTL_REUSE_VFQ 0x00000001 452 453 #define E1000_RPLOLR_STRVLAN 0x40000000 454 #define E1000_RPLOLR_STRCRC 0x80000000 455 456 #define E1000_DTXCTL_8023LL 0x0004 457 #define E1000_DTXCTL_VLAN_ADDED 0x0008 458 #define E1000_DTXCTL_OOS_ENABLE 0x0010 459 #define E1000_DTXCTL_MDP_EN 0x0020 460 #define E1000_DTXCTL_SPOOF_INT 0x0040 461 462 #define ALL_QUEUES 0xFFFF 463 464 /* RX packet buffer size defines */ 465 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F 466 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable); 467 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable); 468 u16 e1000_rxpbs_adjust_82580(u32 data); 469 470 #ifdef __cplusplus 471 } 472 #endif 473 474 #endif /* _IGB_82575_H */ 475