1 /*
2 * This file is provided under a CDDLv1 license. When using or
3 * redistributing this file, you may do so under this license.
4 * In redistributing this file this license must be included
5 * and no other modification of this header file is permitted.
6 *
7 * CDDL LICENSE SUMMARY
8 *
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10 *
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
13 *
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 * http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
19 */
20
21 /*
22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 /*
26 * **********************************************************************
27 * *
28 * Module Name: *
29 * e1000g_main.c *
30 * *
31 * Abstract: *
32 * This file contains the interface routines for the solaris OS. *
33 * It has all DDI entry point routines and GLD entry point routines. *
34 * *
35 * This file also contains routines that take care of initialization *
36 * uninit routine and interrupt routine. *
37 * *
38 * **********************************************************************
39 */
40
41 #include <sys/dlpi.h>
42 #include <sys/mac.h>
43 #include "e1000g_sw.h"
44 #include "e1000g_debug.h"
45
46 static char ident[] = "Intel PRO/1000 Ethernet";
47 /* LINTED E_STATIC_UNUSED */
48 static char e1000g_version[] = "Driver Ver. 5.3.24";
49
50 /*
51 * Proto types for DDI entry points
52 */
53 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t);
54 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t);
55 static int e1000g_quiesce(dev_info_t *);
56
57 /*
58 * init and intr routines prototype
59 */
60 static int e1000g_resume(dev_info_t *);
61 static int e1000g_suspend(dev_info_t *);
62 static uint_t e1000g_intr_pciexpress(caddr_t);
63 static uint_t e1000g_intr(caddr_t);
64 static void e1000g_intr_work(struct e1000g *, uint32_t);
65 #pragma inline(e1000g_intr_work)
66 static int e1000g_init(struct e1000g *);
67 static int e1000g_start(struct e1000g *, boolean_t);
68 static void e1000g_stop(struct e1000g *, boolean_t);
69 static int e1000g_m_start(void *);
70 static void e1000g_m_stop(void *);
71 static int e1000g_m_promisc(void *, boolean_t);
72 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *);
73 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *);
74 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *);
75 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t,
76 uint_t, const void *);
77 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t,
78 uint_t, void *);
79 static void e1000g_m_propinfo(void *, const char *, mac_prop_id_t,
80 mac_prop_info_handle_t);
81 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t,
82 const void *);
83 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, void *);
84 static void e1000g_init_locks(struct e1000g *);
85 static void e1000g_destroy_locks(struct e1000g *);
86 static int e1000g_identify_hardware(struct e1000g *);
87 static int e1000g_regs_map(struct e1000g *);
88 static int e1000g_set_driver_params(struct e1000g *);
89 static void e1000g_set_bufsize(struct e1000g *);
90 static int e1000g_register_mac(struct e1000g *);
91 static boolean_t e1000g_rx_drain(struct e1000g *);
92 static boolean_t e1000g_tx_drain(struct e1000g *);
93 static void e1000g_init_unicst(struct e1000g *);
94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int);
95 static int e1000g_alloc_rx_data(struct e1000g *);
96 static void e1000g_release_multicast(struct e1000g *);
97 static void e1000g_pch_limits(struct e1000g *);
98 static uint32_t e1000g_mtu2maxframe(uint32_t);
99
100 /*
101 * Local routines
102 */
103 static boolean_t e1000g_reset_adapter(struct e1000g *);
104 static void e1000g_tx_clean(struct e1000g *);
105 static void e1000g_rx_clean(struct e1000g *);
106 static void e1000g_link_timer(void *);
107 static void e1000g_local_timer(void *);
108 static boolean_t e1000g_link_check(struct e1000g *);
109 static boolean_t e1000g_stall_check(struct e1000g *);
110 static void e1000g_smartspeed(struct e1000g *);
111 static void e1000g_get_conf(struct e1000g *);
112 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int,
113 int *);
114 static void enable_watchdog_timer(struct e1000g *);
115 static void disable_watchdog_timer(struct e1000g *);
116 static void start_watchdog_timer(struct e1000g *);
117 static void restart_watchdog_timer(struct e1000g *);
118 static void stop_watchdog_timer(struct e1000g *);
119 static void stop_link_timer(struct e1000g *);
120 static void stop_82547_timer(e1000g_tx_ring_t *);
121 static void e1000g_force_speed_duplex(struct e1000g *);
122 static void e1000g_setup_max_mtu(struct e1000g *);
123 static void e1000g_get_max_frame_size(struct e1000g *);
124 static boolean_t is_valid_mac_addr(uint8_t *);
125 static void e1000g_unattach(dev_info_t *, struct e1000g *);
126 static int e1000g_get_bar_info(dev_info_t *, int, bar_info_t *);
127 #ifdef E1000G_DEBUG
128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *);
129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *);
130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *);
131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *);
132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *,
133 struct iocblk *, mblk_t *);
134 #endif
135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *,
136 struct iocblk *, mblk_t *);
137 static boolean_t e1000g_check_loopback_support(struct e1000_hw *);
138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t);
139 static void e1000g_set_internal_loopback(struct e1000g *);
140 static void e1000g_set_external_loopback_1000(struct e1000g *);
141 static void e1000g_set_external_loopback_100(struct e1000g *);
142 static void e1000g_set_external_loopback_10(struct e1000g *);
143 static int e1000g_add_intrs(struct e1000g *);
144 static int e1000g_intr_add(struct e1000g *, int);
145 static int e1000g_rem_intrs(struct e1000g *);
146 static int e1000g_enable_intrs(struct e1000g *);
147 static int e1000g_disable_intrs(struct e1000g *);
148 static boolean_t e1000g_link_up(struct e1000g *);
149 #ifdef __sparc
150 static boolean_t e1000g_find_mac_address(struct e1000g *);
151 #endif
152 static void e1000g_get_phy_state(struct e1000g *);
153 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err,
154 const void *impl_data);
155 static void e1000g_fm_init(struct e1000g *Adapter);
156 static void e1000g_fm_fini(struct e1000g *Adapter);
157 static void e1000g_param_sync(struct e1000g *);
158 static void e1000g_get_driver_control(struct e1000_hw *);
159 static void e1000g_release_driver_control(struct e1000_hw *);
160 static void e1000g_restore_promisc(struct e1000g *Adapter);
161
162 char *e1000g_priv_props[] = {
163 "_tx_bcopy_threshold",
164 "_tx_interrupt_enable",
165 "_tx_intr_delay",
166 "_tx_intr_abs_delay",
167 "_rx_bcopy_threshold",
168 "_max_num_rcv_packets",
169 "_rx_intr_delay",
170 "_rx_intr_abs_delay",
171 "_intr_throttling_rate",
172 "_intr_adaptive",
173 "_adv_pause_cap",
174 "_adv_asym_pause_cap",
175 NULL
176 };
177
178 static struct cb_ops cb_ws_ops = {
179 nulldev, /* cb_open */
180 nulldev, /* cb_close */
181 nodev, /* cb_strategy */
182 nodev, /* cb_print */
183 nodev, /* cb_dump */
184 nodev, /* cb_read */
185 nodev, /* cb_write */
186 nodev, /* cb_ioctl */
187 nodev, /* cb_devmap */
188 nodev, /* cb_mmap */
189 nodev, /* cb_segmap */
190 nochpoll, /* cb_chpoll */
191 ddi_prop_op, /* cb_prop_op */
192 NULL, /* cb_stream */
193 D_MP | D_HOTPLUG, /* cb_flag */
194 CB_REV, /* cb_rev */
195 nodev, /* cb_aread */
196 nodev /* cb_awrite */
197 };
198
199 static struct dev_ops ws_ops = {
200 DEVO_REV, /* devo_rev */
201 0, /* devo_refcnt */
202 NULL, /* devo_getinfo */
203 nulldev, /* devo_identify */
204 nulldev, /* devo_probe */
205 e1000g_attach, /* devo_attach */
206 e1000g_detach, /* devo_detach */
207 nodev, /* devo_reset */
208 &cb_ws_ops, /* devo_cb_ops */
209 NULL, /* devo_bus_ops */
210 ddi_power, /* devo_power */
211 e1000g_quiesce /* devo_quiesce */
212 };
213
214 static struct modldrv modldrv = {
215 &mod_driverops, /* Type of module. This one is a driver */
216 ident, /* Discription string */
217 &ws_ops, /* driver ops */
218 };
219
220 static struct modlinkage modlinkage = {
221 MODREV_1, &modldrv, NULL
222 };
223
224 /* Access attributes for register mapping */
225 static ddi_device_acc_attr_t e1000g_regs_acc_attr = {
226 DDI_DEVICE_ATTR_V1,
227 DDI_STRUCTURE_LE_ACC,
228 DDI_STRICTORDER_ACC,
229 DDI_FLAGERR_ACC
230 };
231
232 #define E1000G_M_CALLBACK_FLAGS \
233 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
234
235 static mac_callbacks_t e1000g_m_callbacks = {
236 E1000G_M_CALLBACK_FLAGS,
237 e1000g_m_stat,
238 e1000g_m_start,
239 e1000g_m_stop,
240 e1000g_m_promisc,
241 e1000g_m_multicst,
242 NULL,
243 e1000g_m_tx,
244 NULL,
245 e1000g_m_ioctl,
246 e1000g_m_getcapab,
247 NULL,
248 NULL,
249 e1000g_m_setprop,
250 e1000g_m_getprop,
251 e1000g_m_propinfo
252 };
253
254 /*
255 * Global variables
256 */
257 uint32_t e1000g_jumbo_mtu = MAXIMUM_MTU_9K;
258 uint32_t e1000g_mblks_pending = 0;
259 /*
260 * Workaround for Dynamic Reconfiguration support, for x86 platform only.
261 * Here we maintain a private dev_info list if e1000g_force_detach is
262 * enabled. If we force the driver to detach while there are still some
263 * rx buffers retained in the upper layer, we have to keep a copy of the
264 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data
265 * structure will be freed after the driver is detached. However when we
266 * finally free those rx buffers released by the upper layer, we need to
267 * refer to the dev_info to free the dma buffers. So we save a copy of
268 * the dev_info for this purpose. On x86 platform, we assume this copy
269 * of dev_info is always valid, but on SPARC platform, it could be invalid
270 * after the system board level DR operation. For this reason, the global
271 * variable e1000g_force_detach must be B_FALSE on SPARC platform.
272 */
273 #ifdef __sparc
274 boolean_t e1000g_force_detach = B_FALSE;
275 #else
276 boolean_t e1000g_force_detach = B_TRUE;
277 #endif
278 private_devi_list_t *e1000g_private_devi_list = NULL;
279
280 /*
281 * The mutex e1000g_rx_detach_lock is defined to protect the processing of
282 * the private dev_info list, and to serialize the processing of rx buffer
283 * freeing and rx buffer recycling.
284 */
285 kmutex_t e1000g_rx_detach_lock;
286 /*
287 * The rwlock e1000g_dma_type_lock is defined to protect the global flag
288 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA".
289 * If there are many e1000g instances, the system may run out of DVMA
290 * resources during the initialization of the instances, then the flag will
291 * be changed to "USE_DMA". Because different e1000g instances are initialized
292 * in parallel, we need to use this lock to protect the flag.
293 */
294 krwlock_t e1000g_dma_type_lock;
295
296 /*
297 * The 82546 chipset is a dual-port device, both the ports share one eeprom.
298 * Based on the information from Intel, the 82546 chipset has some hardware
299 * problem. When one port is being reset and the other port is trying to
300 * access the eeprom, it could cause system hang or panic. To workaround this
301 * hardware problem, we use a global mutex to prevent such operations from
302 * happening simultaneously on different instances. This workaround is applied
303 * to all the devices supported by this driver.
304 */
305 kmutex_t e1000g_nvm_lock;
306
307 /*
308 * Loadable module configuration entry points for the driver
309 */
310
311 /*
312 * _init - module initialization
313 */
314 int
_init(void)315 _init(void)
316 {
317 int status;
318
319 mac_init_ops(&ws_ops, WSNAME);
320 status = mod_install(&modlinkage);
321 if (status != DDI_SUCCESS)
322 mac_fini_ops(&ws_ops);
323 else {
324 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL);
325 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL);
326 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL);
327 }
328
329 return (status);
330 }
331
332 /*
333 * _fini - module finalization
334 */
335 int
_fini(void)336 _fini(void)
337 {
338 int status;
339
340 if (e1000g_mblks_pending != 0)
341 return (EBUSY);
342
343 status = mod_remove(&modlinkage);
344 if (status == DDI_SUCCESS) {
345 mac_fini_ops(&ws_ops);
346
347 if (e1000g_force_detach) {
348 private_devi_list_t *devi_node;
349
350 mutex_enter(&e1000g_rx_detach_lock);
351 while (e1000g_private_devi_list != NULL) {
352 devi_node = e1000g_private_devi_list;
353 e1000g_private_devi_list =
354 e1000g_private_devi_list->next;
355
356 kmem_free(devi_node->priv_dip,
357 sizeof (struct dev_info));
358 kmem_free(devi_node,
359 sizeof (private_devi_list_t));
360 }
361 mutex_exit(&e1000g_rx_detach_lock);
362 }
363
364 mutex_destroy(&e1000g_rx_detach_lock);
365 rw_destroy(&e1000g_dma_type_lock);
366 mutex_destroy(&e1000g_nvm_lock);
367 }
368
369 return (status);
370 }
371
372 /*
373 * _info - module information
374 */
375 int
_info(struct modinfo * modinfop)376 _info(struct modinfo *modinfop)
377 {
378 return (mod_info(&modlinkage, modinfop));
379 }
380
381 /*
382 * e1000g_attach - driver attach
383 *
384 * This function is the device-specific initialization entry
385 * point. This entry point is required and must be written.
386 * The DDI_ATTACH command must be provided in the attach entry
387 * point. When attach() is called with cmd set to DDI_ATTACH,
388 * all normal kernel services (such as kmem_alloc(9F)) are
389 * available for use by the driver.
390 *
391 * The attach() function will be called once for each instance
392 * of the device on the system with cmd set to DDI_ATTACH.
393 * Until attach() succeeds, the only driver entry points which
394 * may be called are open(9E) and getinfo(9E).
395 */
396 static int
e1000g_attach(dev_info_t * devinfo,ddi_attach_cmd_t cmd)397 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
398 {
399 struct e1000g *Adapter;
400 struct e1000_hw *hw;
401 struct e1000g_osdep *osdep;
402 int instance;
403
404 switch (cmd) {
405 default:
406 e1000g_log(NULL, CE_WARN,
407 "Unsupported command send to e1000g_attach... ");
408 return (DDI_FAILURE);
409
410 case DDI_RESUME:
411 return (e1000g_resume(devinfo));
412
413 case DDI_ATTACH:
414 break;
415 }
416
417 /*
418 * get device instance number
419 */
420 instance = ddi_get_instance(devinfo);
421
422 /*
423 * Allocate soft data structure
424 */
425 Adapter =
426 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP);
427
428 Adapter->dip = devinfo;
429 Adapter->instance = instance;
430 Adapter->tx_ring->adapter = Adapter;
431 Adapter->rx_ring->adapter = Adapter;
432
433 hw = &Adapter->shared;
434 osdep = &Adapter->osdep;
435 hw->back = osdep;
436 osdep->adapter = Adapter;
437
438 ddi_set_driver_private(devinfo, (caddr_t)Adapter);
439
440 /*
441 * Initialize for fma support
442 */
443 (void) e1000g_get_prop(Adapter, "fm-capable",
444 0, 0x0f,
445 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
446 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE,
447 &Adapter->fm_capabilities);
448 e1000g_fm_init(Adapter);
449 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT;
450
451 /*
452 * PCI Configure
453 */
454 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) {
455 e1000g_log(Adapter, CE_WARN, "PCI configuration failed");
456 goto attach_fail;
457 }
458 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
459
460 /*
461 * Setup hardware
462 */
463 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) {
464 e1000g_log(Adapter, CE_WARN, "Identify hardware failed");
465 goto attach_fail;
466 }
467
468 /*
469 * Map in the device registers.
470 */
471 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) {
472 e1000g_log(Adapter, CE_WARN, "Mapping registers failed");
473 goto attach_fail;
474 }
475 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
476
477 /*
478 * Initialize driver parameters
479 */
480 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) {
481 goto attach_fail;
482 }
483 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP;
484
485 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) {
486 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
487 goto attach_fail;
488 }
489
490 /*
491 * Initialize interrupts
492 */
493 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) {
494 e1000g_log(Adapter, CE_WARN, "Add interrupts failed");
495 goto attach_fail;
496 }
497 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
498
499 /*
500 * Initialize mutex's for this device.
501 * Do this before enabling the interrupt handler and
502 * register the softint to avoid the condition where
503 * interrupt handler can try using uninitialized mutex
504 */
505 e1000g_init_locks(Adapter);
506 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS;
507
508 /*
509 * Initialize Driver Counters
510 */
511 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) {
512 e1000g_log(Adapter, CE_WARN, "Init stats failed");
513 goto attach_fail;
514 }
515 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS;
516
517 /*
518 * Initialize chip hardware and software structures
519 */
520 rw_enter(&Adapter->chip_lock, RW_WRITER);
521 if (e1000g_init(Adapter) != DDI_SUCCESS) {
522 rw_exit(&Adapter->chip_lock);
523 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed");
524 goto attach_fail;
525 }
526 rw_exit(&Adapter->chip_lock);
527 Adapter->attach_progress |= ATTACH_PROGRESS_INIT;
528
529 /*
530 * Register the driver to the MAC
531 */
532 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) {
533 e1000g_log(Adapter, CE_WARN, "Register MAC failed");
534 goto attach_fail;
535 }
536 Adapter->attach_progress |= ATTACH_PROGRESS_MAC;
537
538 /*
539 * Now that mutex locks are initialized, and the chip is also
540 * initialized, enable interrupts.
541 */
542 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) {
543 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed");
544 goto attach_fail;
545 }
546 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
547
548 /*
549 * If e1000g_force_detach is enabled, in global private dip list,
550 * we will create a new entry, which maintains the priv_dip for DR
551 * supports after driver detached.
552 */
553 if (e1000g_force_detach) {
554 private_devi_list_t *devi_node;
555
556 Adapter->priv_dip =
557 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP);
558 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip),
559 sizeof (struct dev_info));
560
561 devi_node =
562 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP);
563
564 mutex_enter(&e1000g_rx_detach_lock);
565 devi_node->priv_dip = Adapter->priv_dip;
566 devi_node->flag = E1000G_PRIV_DEVI_ATTACH;
567 devi_node->pending_rx_count = 0;
568
569 Adapter->priv_devi_node = devi_node;
570
571 if (e1000g_private_devi_list == NULL) {
572 devi_node->prev = NULL;
573 devi_node->next = NULL;
574 e1000g_private_devi_list = devi_node;
575 } else {
576 devi_node->prev = NULL;
577 devi_node->next = e1000g_private_devi_list;
578 e1000g_private_devi_list->prev = devi_node;
579 e1000g_private_devi_list = devi_node;
580 }
581 mutex_exit(&e1000g_rx_detach_lock);
582 }
583
584 Adapter->e1000g_state = E1000G_INITIALIZED;
585 return (DDI_SUCCESS);
586
587 attach_fail:
588 e1000g_unattach(devinfo, Adapter);
589 return (DDI_FAILURE);
590 }
591
592 static int
e1000g_register_mac(struct e1000g * Adapter)593 e1000g_register_mac(struct e1000g *Adapter)
594 {
595 struct e1000_hw *hw = &Adapter->shared;
596 mac_register_t *mac;
597 int err;
598
599 if ((mac = mac_alloc(MAC_VERSION)) == NULL)
600 return (DDI_FAILURE);
601
602 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
603 mac->m_driver = Adapter;
604 mac->m_dip = Adapter->dip;
605 mac->m_src_addr = hw->mac.addr;
606 mac->m_callbacks = &e1000g_m_callbacks;
607 mac->m_min_sdu = 0;
608 mac->m_max_sdu = Adapter->default_mtu;
609 mac->m_margin = VLAN_TAGSZ;
610 mac->m_priv_props = e1000g_priv_props;
611 mac->m_v12n = MAC_VIRT_LEVEL1;
612
613 err = mac_register(mac, &Adapter->mh);
614 mac_free(mac);
615
616 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE);
617 }
618
619 static int
e1000g_identify_hardware(struct e1000g * Adapter)620 e1000g_identify_hardware(struct e1000g *Adapter)
621 {
622 struct e1000_hw *hw = &Adapter->shared;
623 struct e1000g_osdep *osdep = &Adapter->osdep;
624
625 /* Get the device id */
626 hw->vendor_id =
627 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID);
628 hw->device_id =
629 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID);
630 hw->revision_id =
631 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID);
632 hw->subsystem_device_id =
633 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID);
634 hw->subsystem_vendor_id =
635 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID);
636
637 if (e1000_set_mac_type(hw) != E1000_SUCCESS) {
638 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL,
639 "MAC type could not be set properly.");
640 return (DDI_FAILURE);
641 }
642
643 return (DDI_SUCCESS);
644 }
645
646 static int
e1000g_regs_map(struct e1000g * Adapter)647 e1000g_regs_map(struct e1000g *Adapter)
648 {
649 dev_info_t *devinfo = Adapter->dip;
650 struct e1000_hw *hw = &Adapter->shared;
651 struct e1000g_osdep *osdep = &Adapter->osdep;
652 off_t mem_size;
653 bar_info_t bar_info;
654 int offset, rnumber;
655
656 rnumber = ADAPTER_REG_SET;
657 /* Get size of adapter register memory */
658 if (ddi_dev_regsize(devinfo, rnumber, &mem_size) !=
659 DDI_SUCCESS) {
660 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
661 "ddi_dev_regsize for registers failed");
662 return (DDI_FAILURE);
663 }
664
665 /* Map adapter register memory */
666 if ((ddi_regs_map_setup(devinfo, rnumber,
667 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr,
668 &osdep->reg_handle)) != DDI_SUCCESS) {
669 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
670 "ddi_regs_map_setup for registers failed");
671 goto regs_map_fail;
672 }
673
674 /* ICH needs to map flash memory */
675 switch (hw->mac.type) {
676 case e1000_ich8lan:
677 case e1000_ich9lan:
678 case e1000_ich10lan:
679 case e1000_pchlan:
680 rnumber = ICH_FLASH_REG_SET;
681
682 /* get flash size */
683 if (ddi_dev_regsize(devinfo, rnumber,
684 &mem_size) != DDI_SUCCESS) {
685 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
686 "ddi_dev_regsize for ICH flash failed");
687 goto regs_map_fail;
688 }
689
690 /* map flash in */
691 if (ddi_regs_map_setup(devinfo, rnumber,
692 (caddr_t *)&hw->flash_address, 0,
693 mem_size, &e1000g_regs_acc_attr,
694 &osdep->ich_flash_handle) != DDI_SUCCESS) {
695 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
696 "ddi_regs_map_setup for ICH flash failed");
697 goto regs_map_fail;
698 }
699 break;
700 default:
701 break;
702 }
703
704 /* map io space */
705 switch (hw->mac.type) {
706 case e1000_82544:
707 case e1000_82540:
708 case e1000_82545:
709 case e1000_82546:
710 case e1000_82541:
711 case e1000_82541_rev_2:
712 /* find the IO bar */
713 rnumber = -1;
714 for (offset = PCI_CONF_BASE1;
715 offset <= PCI_CONF_BASE5; offset += 4) {
716 if (e1000g_get_bar_info(devinfo, offset, &bar_info)
717 != DDI_SUCCESS)
718 continue;
719 if (bar_info.type == E1000G_BAR_IO) {
720 rnumber = bar_info.rnumber;
721 break;
722 }
723 }
724
725 if (rnumber < 0) {
726 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
727 "No io space is found");
728 goto regs_map_fail;
729 }
730
731 /* get io space size */
732 if (ddi_dev_regsize(devinfo, rnumber,
733 &mem_size) != DDI_SUCCESS) {
734 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
735 "ddi_dev_regsize for io space failed");
736 goto regs_map_fail;
737 }
738
739 /* map io space */
740 if ((ddi_regs_map_setup(devinfo, rnumber,
741 (caddr_t *)&hw->io_base, 0, mem_size,
742 &e1000g_regs_acc_attr,
743 &osdep->io_reg_handle)) != DDI_SUCCESS) {
744 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
745 "ddi_regs_map_setup for io space failed");
746 goto regs_map_fail;
747 }
748 break;
749 default:
750 hw->io_base = 0;
751 break;
752 }
753
754 return (DDI_SUCCESS);
755
756 regs_map_fail:
757 if (osdep->reg_handle != NULL)
758 ddi_regs_map_free(&osdep->reg_handle);
759 if (osdep->ich_flash_handle != NULL)
760 ddi_regs_map_free(&osdep->ich_flash_handle);
761 return (DDI_FAILURE);
762 }
763
764 static int
e1000g_set_driver_params(struct e1000g * Adapter)765 e1000g_set_driver_params(struct e1000g *Adapter)
766 {
767 struct e1000_hw *hw;
768
769 hw = &Adapter->shared;
770
771 /* Set MAC type and initialize hardware functions */
772 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
773 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
774 "Could not setup hardware functions");
775 return (DDI_FAILURE);
776 }
777
778 /* Get bus information */
779 if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
780 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
781 "Could not get bus information");
782 return (DDI_FAILURE);
783 }
784
785 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word);
786
787 hw->mac.autoneg_failed = B_TRUE;
788
789 /* Set the autoneg_wait_to_complete flag to B_FALSE */
790 hw->phy.autoneg_wait_to_complete = B_FALSE;
791
792 /* Adaptive IFS related changes */
793 hw->mac.adaptive_ifs = B_TRUE;
794
795 /* Enable phy init script for IGP phy of 82541/82547 */
796 if ((hw->mac.type == e1000_82547) ||
797 (hw->mac.type == e1000_82541) ||
798 (hw->mac.type == e1000_82547_rev_2) ||
799 (hw->mac.type == e1000_82541_rev_2))
800 e1000_init_script_state_82541(hw, B_TRUE);
801
802 /* Enable the TTL workaround for 82541/82547 */
803 e1000_set_ttl_workaround_state_82541(hw, B_TRUE);
804
805 #ifdef __sparc
806 Adapter->strip_crc = B_TRUE;
807 #else
808 Adapter->strip_crc = B_FALSE;
809 #endif
810
811 /* setup the maximum MTU size of the chip */
812 e1000g_setup_max_mtu(Adapter);
813
814 /* Get speed/duplex settings in conf file */
815 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL;
816 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
817 e1000g_force_speed_duplex(Adapter);
818
819 /* Get Jumbo Frames settings in conf file */
820 e1000g_get_max_frame_size(Adapter);
821
822 /* Get conf file properties */
823 e1000g_get_conf(Adapter);
824
825 /* enforce PCH limits */
826 e1000g_pch_limits(Adapter);
827
828 /* Set Rx/Tx buffer size */
829 e1000g_set_bufsize(Adapter);
830
831 /* Master Latency Timer */
832 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER;
833
834 /* copper options */
835 if (hw->phy.media_type == e1000_media_type_copper) {
836 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
837 hw->phy.disable_polarity_correction = B_FALSE;
838 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */
839 }
840
841 /* The initial link state should be "unknown" */
842 Adapter->link_state = LINK_STATE_UNKNOWN;
843
844 /* Initialize rx parameters */
845 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY;
846 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY;
847
848 /* Initialize tx parameters */
849 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE;
850 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD;
851 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY;
852 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY;
853
854 /* Initialize rx parameters */
855 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD;
856
857 return (DDI_SUCCESS);
858 }
859
860 static void
e1000g_setup_max_mtu(struct e1000g * Adapter)861 e1000g_setup_max_mtu(struct e1000g *Adapter)
862 {
863 struct e1000_mac_info *mac = &Adapter->shared.mac;
864 struct e1000_phy_info *phy = &Adapter->shared.phy;
865
866 switch (mac->type) {
867 /* types that do not support jumbo frames */
868 case e1000_ich8lan:
869 case e1000_82573:
870 case e1000_82583:
871 Adapter->max_mtu = ETHERMTU;
872 break;
873 /* ich9 supports jumbo frames except on one phy type */
874 case e1000_ich9lan:
875 if (phy->type == e1000_phy_ife)
876 Adapter->max_mtu = ETHERMTU;
877 else
878 Adapter->max_mtu = MAXIMUM_MTU_9K;
879 break;
880 /* pch can do jumbo frames up to 4K */
881 case e1000_pchlan:
882 Adapter->max_mtu = MAXIMUM_MTU_4K;
883 break;
884 /* types with a special limit */
885 case e1000_82571:
886 case e1000_82572:
887 case e1000_82574:
888 case e1000_80003es2lan:
889 case e1000_ich10lan:
890 if (e1000g_jumbo_mtu >= ETHERMTU &&
891 e1000g_jumbo_mtu <= MAXIMUM_MTU_9K) {
892 Adapter->max_mtu = e1000g_jumbo_mtu;
893 } else {
894 Adapter->max_mtu = MAXIMUM_MTU_9K;
895 }
896 break;
897 /* default limit is 16K */
898 default:
899 Adapter->max_mtu = FRAME_SIZE_UPTO_16K -
900 sizeof (struct ether_vlan_header) - ETHERFCSL;
901 break;
902 }
903 }
904
905 static void
e1000g_set_bufsize(struct e1000g * Adapter)906 e1000g_set_bufsize(struct e1000g *Adapter)
907 {
908 struct e1000_mac_info *mac = &Adapter->shared.mac;
909 uint64_t rx_size;
910 uint64_t tx_size;
911
912 dev_info_t *devinfo = Adapter->dip;
913 #ifdef __sparc
914 ulong_t iommu_pagesize;
915 #endif
916 /* Get the system page size */
917 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1);
918
919 #ifdef __sparc
920 iommu_pagesize = dvma_pagesize(devinfo);
921 if (iommu_pagesize != 0) {
922 if (Adapter->sys_page_sz == iommu_pagesize) {
923 if (iommu_pagesize > 0x4000)
924 Adapter->sys_page_sz = 0x4000;
925 } else {
926 if (Adapter->sys_page_sz > iommu_pagesize)
927 Adapter->sys_page_sz = iommu_pagesize;
928 }
929 }
930 if (Adapter->lso_enable) {
931 Adapter->dvma_page_num = E1000_LSO_MAXLEN /
932 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM;
933 } else {
934 Adapter->dvma_page_num = Adapter->max_frame_size /
935 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM;
936 }
937 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM);
938 #endif
939
940 Adapter->min_frame_size = ETHERMIN + ETHERFCSL;
941
942 if (Adapter->mem_workaround_82546 &&
943 ((mac->type == e1000_82545) ||
944 (mac->type == e1000_82546) ||
945 (mac->type == e1000_82546_rev_3))) {
946 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K;
947 } else {
948 rx_size = Adapter->max_frame_size;
949 if ((rx_size > FRAME_SIZE_UPTO_2K) &&
950 (rx_size <= FRAME_SIZE_UPTO_4K))
951 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K;
952 else if ((rx_size > FRAME_SIZE_UPTO_4K) &&
953 (rx_size <= FRAME_SIZE_UPTO_8K))
954 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K;
955 else if ((rx_size > FRAME_SIZE_UPTO_8K) &&
956 (rx_size <= FRAME_SIZE_UPTO_16K))
957 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K;
958 else
959 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K;
960 }
961 Adapter->rx_buffer_size += E1000G_IPALIGNROOM;
962
963 tx_size = Adapter->max_frame_size;
964 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K))
965 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K;
966 else if ((tx_size > FRAME_SIZE_UPTO_4K) &&
967 (tx_size <= FRAME_SIZE_UPTO_8K))
968 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K;
969 else if ((tx_size > FRAME_SIZE_UPTO_8K) &&
970 (tx_size <= FRAME_SIZE_UPTO_16K))
971 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K;
972 else
973 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K;
974
975 /*
976 * For Wiseman adapters we have an requirement of having receive
977 * buffers aligned at 256 byte boundary. Since Livengood does not
978 * require this and forcing it for all hardwares will have
979 * performance implications, I am making it applicable only for
980 * Wiseman and for Jumbo frames enabled mode as rest of the time,
981 * it is okay to have normal frames...but it does involve a
982 * potential risk where we may loose data if buffer is not
983 * aligned...so all wiseman boards to have 256 byte aligned
984 * buffers
985 */
986 if (mac->type < e1000_82543)
987 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE;
988 else
989 Adapter->rx_buf_align = 1;
990 }
991
992 /*
993 * e1000g_detach - driver detach
994 *
995 * The detach() function is the complement of the attach routine.
996 * If cmd is set to DDI_DETACH, detach() is used to remove the
997 * state associated with a given instance of a device node
998 * prior to the removal of that instance from the system.
999 *
1000 * The detach() function will be called once for each instance
1001 * of the device for which there has been a successful attach()
1002 * once there are no longer any opens on the device.
1003 *
1004 * Interrupts routine are disabled, All memory allocated by this
1005 * driver are freed.
1006 */
1007 static int
e1000g_detach(dev_info_t * devinfo,ddi_detach_cmd_t cmd)1008 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
1009 {
1010 struct e1000g *Adapter;
1011 boolean_t rx_drain;
1012
1013 switch (cmd) {
1014 default:
1015 return (DDI_FAILURE);
1016
1017 case DDI_SUSPEND:
1018 return (e1000g_suspend(devinfo));
1019
1020 case DDI_DETACH:
1021 break;
1022 }
1023
1024 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo);
1025 if (Adapter == NULL)
1026 return (DDI_FAILURE);
1027
1028 rx_drain = e1000g_rx_drain(Adapter);
1029 if (!rx_drain && !e1000g_force_detach)
1030 return (DDI_FAILURE);
1031
1032 if (mac_unregister(Adapter->mh) != 0) {
1033 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed");
1034 return (DDI_FAILURE);
1035 }
1036 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC;
1037
1038 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED));
1039
1040 if (!e1000g_force_detach && !rx_drain)
1041 return (DDI_FAILURE);
1042
1043 e1000g_unattach(devinfo, Adapter);
1044
1045 return (DDI_SUCCESS);
1046 }
1047
1048 /*
1049 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance
1050 */
1051 void
e1000g_free_priv_devi_node(private_devi_list_t * devi_node)1052 e1000g_free_priv_devi_node(private_devi_list_t *devi_node)
1053 {
1054 ASSERT(e1000g_private_devi_list != NULL);
1055 ASSERT(devi_node != NULL);
1056
1057 if (devi_node->prev != NULL)
1058 devi_node->prev->next = devi_node->next;
1059 if (devi_node->next != NULL)
1060 devi_node->next->prev = devi_node->prev;
1061 if (devi_node == e1000g_private_devi_list)
1062 e1000g_private_devi_list = devi_node->next;
1063
1064 kmem_free(devi_node->priv_dip,
1065 sizeof (struct dev_info));
1066 kmem_free(devi_node,
1067 sizeof (private_devi_list_t));
1068 }
1069
1070 static void
e1000g_unattach(dev_info_t * devinfo,struct e1000g * Adapter)1071 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter)
1072 {
1073 private_devi_list_t *devi_node;
1074 int result;
1075
1076 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1077 (void) e1000g_disable_intrs(Adapter);
1078 }
1079
1080 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) {
1081 (void) mac_unregister(Adapter->mh);
1082 }
1083
1084 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
1085 (void) e1000g_rem_intrs(Adapter);
1086 }
1087
1088 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) {
1089 (void) ddi_prop_remove_all(devinfo);
1090 }
1091
1092 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) {
1093 kstat_delete((kstat_t *)Adapter->e1000g_ksp);
1094 }
1095
1096 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) {
1097 stop_link_timer(Adapter);
1098
1099 mutex_enter(&e1000g_nvm_lock);
1100 result = e1000_reset_hw(&Adapter->shared);
1101 mutex_exit(&e1000g_nvm_lock);
1102
1103 if (result != E1000_SUCCESS) {
1104 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1105 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1106 }
1107 }
1108
1109 e1000g_release_multicast(Adapter);
1110
1111 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
1112 if (Adapter->osdep.reg_handle != NULL)
1113 ddi_regs_map_free(&Adapter->osdep.reg_handle);
1114 if (Adapter->osdep.ich_flash_handle != NULL)
1115 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle);
1116 if (Adapter->osdep.io_reg_handle != NULL)
1117 ddi_regs_map_free(&Adapter->osdep.io_reg_handle);
1118 }
1119
1120 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
1121 if (Adapter->osdep.cfg_handle != NULL)
1122 pci_config_teardown(&Adapter->osdep.cfg_handle);
1123 }
1124
1125 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) {
1126 e1000g_destroy_locks(Adapter);
1127 }
1128
1129 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) {
1130 e1000g_fm_fini(Adapter);
1131 }
1132
1133 mutex_enter(&e1000g_rx_detach_lock);
1134 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) {
1135 devi_node = Adapter->priv_devi_node;
1136 devi_node->flag |= E1000G_PRIV_DEVI_DETACH;
1137
1138 if (devi_node->pending_rx_count == 0) {
1139 e1000g_free_priv_devi_node(devi_node);
1140 }
1141 }
1142 mutex_exit(&e1000g_rx_detach_lock);
1143
1144 kmem_free((caddr_t)Adapter, sizeof (struct e1000g));
1145
1146 /*
1147 * Another hotplug spec requirement,
1148 * run ddi_set_driver_private(devinfo, null);
1149 */
1150 ddi_set_driver_private(devinfo, NULL);
1151 }
1152
1153 /*
1154 * Get the BAR type and rnumber for a given PCI BAR offset
1155 */
1156 static int
e1000g_get_bar_info(dev_info_t * dip,int bar_offset,bar_info_t * bar_info)1157 e1000g_get_bar_info(dev_info_t *dip, int bar_offset, bar_info_t *bar_info)
1158 {
1159 pci_regspec_t *regs;
1160 uint_t regs_length;
1161 int type, rnumber, rcount;
1162
1163 ASSERT((bar_offset >= PCI_CONF_BASE0) &&
1164 (bar_offset <= PCI_CONF_BASE5));
1165
1166 /*
1167 * Get the DDI "reg" property
1168 */
1169 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip,
1170 DDI_PROP_DONTPASS, "reg", (int **)®s,
1171 ®s_length) != DDI_PROP_SUCCESS) {
1172 return (DDI_FAILURE);
1173 }
1174
1175 rcount = regs_length * sizeof (int) / sizeof (pci_regspec_t);
1176 /*
1177 * Check the BAR offset
1178 */
1179 for (rnumber = 0; rnumber < rcount; ++rnumber) {
1180 if (PCI_REG_REG_G(regs[rnumber].pci_phys_hi) == bar_offset) {
1181 type = regs[rnumber].pci_phys_hi & PCI_ADDR_MASK;
1182 break;
1183 }
1184 }
1185
1186 ddi_prop_free(regs);
1187
1188 if (rnumber >= rcount)
1189 return (DDI_FAILURE);
1190
1191 switch (type) {
1192 case PCI_ADDR_CONFIG:
1193 bar_info->type = E1000G_BAR_CONFIG;
1194 break;
1195 case PCI_ADDR_IO:
1196 bar_info->type = E1000G_BAR_IO;
1197 break;
1198 case PCI_ADDR_MEM32:
1199 bar_info->type = E1000G_BAR_MEM32;
1200 break;
1201 case PCI_ADDR_MEM64:
1202 bar_info->type = E1000G_BAR_MEM64;
1203 break;
1204 default:
1205 return (DDI_FAILURE);
1206 }
1207 bar_info->rnumber = rnumber;
1208 return (DDI_SUCCESS);
1209 }
1210
1211 static void
e1000g_init_locks(struct e1000g * Adapter)1212 e1000g_init_locks(struct e1000g *Adapter)
1213 {
1214 e1000g_tx_ring_t *tx_ring;
1215 e1000g_rx_ring_t *rx_ring;
1216
1217 rw_init(&Adapter->chip_lock, NULL,
1218 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1219 mutex_init(&Adapter->link_lock, NULL,
1220 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1221 mutex_init(&Adapter->watchdog_lock, NULL,
1222 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1223
1224 tx_ring = Adapter->tx_ring;
1225
1226 mutex_init(&tx_ring->tx_lock, NULL,
1227 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1228 mutex_init(&tx_ring->usedlist_lock, NULL,
1229 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1230 mutex_init(&tx_ring->freelist_lock, NULL,
1231 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1232
1233 rx_ring = Adapter->rx_ring;
1234
1235 mutex_init(&rx_ring->rx_lock, NULL,
1236 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1237 }
1238
1239 static void
e1000g_destroy_locks(struct e1000g * Adapter)1240 e1000g_destroy_locks(struct e1000g *Adapter)
1241 {
1242 e1000g_tx_ring_t *tx_ring;
1243 e1000g_rx_ring_t *rx_ring;
1244
1245 tx_ring = Adapter->tx_ring;
1246 mutex_destroy(&tx_ring->tx_lock);
1247 mutex_destroy(&tx_ring->usedlist_lock);
1248 mutex_destroy(&tx_ring->freelist_lock);
1249
1250 rx_ring = Adapter->rx_ring;
1251 mutex_destroy(&rx_ring->rx_lock);
1252
1253 mutex_destroy(&Adapter->link_lock);
1254 mutex_destroy(&Adapter->watchdog_lock);
1255 rw_destroy(&Adapter->chip_lock);
1256
1257 /* destory mutex initialized in shared code */
1258 e1000_destroy_hw_mutex(&Adapter->shared);
1259 }
1260
1261 static int
e1000g_resume(dev_info_t * devinfo)1262 e1000g_resume(dev_info_t *devinfo)
1263 {
1264 struct e1000g *Adapter;
1265
1266 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo);
1267 if (Adapter == NULL)
1268 e1000g_log(Adapter, CE_PANIC,
1269 "Instance pointer is null\n");
1270
1271 if (Adapter->dip != devinfo)
1272 e1000g_log(Adapter, CE_PANIC,
1273 "Devinfo is not the same as saved devinfo\n");
1274
1275 rw_enter(&Adapter->chip_lock, RW_WRITER);
1276
1277 if (Adapter->e1000g_state & E1000G_STARTED) {
1278 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) {
1279 rw_exit(&Adapter->chip_lock);
1280 /*
1281 * We note the failure, but return success, as the
1282 * system is still usable without this controller.
1283 */
1284 e1000g_log(Adapter, CE_WARN,
1285 "e1000g_resume: failed to restart controller\n");
1286 return (DDI_SUCCESS);
1287 }
1288 /* Enable and start the watchdog timer */
1289 enable_watchdog_timer(Adapter);
1290 }
1291
1292 Adapter->e1000g_state &= ~E1000G_SUSPENDED;
1293
1294 rw_exit(&Adapter->chip_lock);
1295
1296 return (DDI_SUCCESS);
1297 }
1298
1299 static int
e1000g_suspend(dev_info_t * devinfo)1300 e1000g_suspend(dev_info_t *devinfo)
1301 {
1302 struct e1000g *Adapter;
1303
1304 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo);
1305 if (Adapter == NULL)
1306 return (DDI_FAILURE);
1307
1308 rw_enter(&Adapter->chip_lock, RW_WRITER);
1309
1310 Adapter->e1000g_state |= E1000G_SUSPENDED;
1311
1312 /* if the port isn't plumbed, we can simply return */
1313 if (!(Adapter->e1000g_state & E1000G_STARTED)) {
1314 rw_exit(&Adapter->chip_lock);
1315 return (DDI_SUCCESS);
1316 }
1317
1318 e1000g_stop(Adapter, B_FALSE);
1319
1320 rw_exit(&Adapter->chip_lock);
1321
1322 /* Disable and stop all the timers */
1323 disable_watchdog_timer(Adapter);
1324 stop_link_timer(Adapter);
1325 stop_82547_timer(Adapter->tx_ring);
1326
1327 return (DDI_SUCCESS);
1328 }
1329
1330 static int
e1000g_init(struct e1000g * Adapter)1331 e1000g_init(struct e1000g *Adapter)
1332 {
1333 uint32_t pba;
1334 uint32_t high_water;
1335 struct e1000_hw *hw;
1336 clock_t link_timeout;
1337 int result;
1338
1339 hw = &Adapter->shared;
1340
1341 /*
1342 * reset to put the hardware in a known state
1343 * before we try to do anything with the eeprom
1344 */
1345 mutex_enter(&e1000g_nvm_lock);
1346 result = e1000_reset_hw(hw);
1347 mutex_exit(&e1000g_nvm_lock);
1348
1349 if (result != E1000_SUCCESS) {
1350 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1351 goto init_fail;
1352 }
1353
1354 mutex_enter(&e1000g_nvm_lock);
1355 result = e1000_validate_nvm_checksum(hw);
1356 if (result < E1000_SUCCESS) {
1357 /*
1358 * Some PCI-E parts fail the first check due to
1359 * the link being in sleep state. Call it again,
1360 * if it fails a second time its a real issue.
1361 */
1362 result = e1000_validate_nvm_checksum(hw);
1363 }
1364 mutex_exit(&e1000g_nvm_lock);
1365
1366 if (result < E1000_SUCCESS) {
1367 e1000g_log(Adapter, CE_WARN,
1368 "Invalid NVM checksum. Please contact "
1369 "the vendor to update the NVM.");
1370 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1371 goto init_fail;
1372 }
1373
1374 result = 0;
1375 #ifdef __sparc
1376 /*
1377 * First, we try to get the local ethernet address from OBP. If
1378 * failed, then we get it from the EEPROM of NIC card.
1379 */
1380 result = e1000g_find_mac_address(Adapter);
1381 #endif
1382 /* Get the local ethernet address. */
1383 if (!result) {
1384 mutex_enter(&e1000g_nvm_lock);
1385 result = e1000_read_mac_addr(hw);
1386 mutex_exit(&e1000g_nvm_lock);
1387 }
1388
1389 if (result < E1000_SUCCESS) {
1390 e1000g_log(Adapter, CE_WARN, "Read mac addr failed");
1391 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1392 goto init_fail;
1393 }
1394
1395 /* check for valid mac address */
1396 if (!is_valid_mac_addr(hw->mac.addr)) {
1397 e1000g_log(Adapter, CE_WARN, "Invalid mac addr");
1398 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1399 goto init_fail;
1400 }
1401
1402 /* Set LAA state for 82571 chipset */
1403 e1000_set_laa_state_82571(hw, B_TRUE);
1404
1405 /* Master Latency Timer implementation */
1406 if (Adapter->master_latency_timer) {
1407 pci_config_put8(Adapter->osdep.cfg_handle,
1408 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer);
1409 }
1410
1411 if (hw->mac.type < e1000_82547) {
1412 /*
1413 * Total FIFO is 64K
1414 */
1415 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K)
1416 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1417 else
1418 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1419 } else if ((hw->mac.type == e1000_82571) ||
1420 (hw->mac.type == e1000_82572) ||
1421 (hw->mac.type == e1000_80003es2lan)) {
1422 /*
1423 * Total FIFO is 48K
1424 */
1425 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K)
1426 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */
1427 else
1428 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */
1429 } else if (hw->mac.type == e1000_82573) {
1430 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */
1431 } else if (hw->mac.type == e1000_82574) {
1432 /* Keep adapter default: 20K for Rx, 20K for Tx */
1433 pba = E1000_READ_REG(hw, E1000_PBA);
1434 } else if (hw->mac.type == e1000_ich8lan) {
1435 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */
1436 } else if (hw->mac.type == e1000_ich9lan) {
1437 pba = E1000_PBA_10K;
1438 } else if (hw->mac.type == e1000_ich10lan) {
1439 pba = E1000_PBA_10K;
1440 } else if (hw->mac.type == e1000_pchlan) {
1441 pba = E1000_PBA_26K;
1442 } else {
1443 /*
1444 * Total FIFO is 40K
1445 */
1446 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K)
1447 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
1448 else
1449 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
1450 }
1451 E1000_WRITE_REG(hw, E1000_PBA, pba);
1452
1453 /*
1454 * These parameters set thresholds for the adapter's generation(Tx)
1455 * and response(Rx) to Ethernet PAUSE frames. These are just threshold
1456 * settings. Flow control is enabled or disabled in the configuration
1457 * file.
1458 * High-water mark is set down from the top of the rx fifo (not
1459 * sensitive to max_frame_size) and low-water is set just below
1460 * high-water mark.
1461 * The high water mark must be low enough to fit one full frame above
1462 * it in the rx FIFO. Should be the lower of:
1463 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early
1464 * receive size (assuming ERT set to E1000_ERT_2048), or the full
1465 * Rx FIFO size minus one full frame.
1466 */
1467 high_water = min(((pba << 10) * 9 / 10),
1468 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 ||
1469 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ?
1470 ((pba << 10) - (E1000_ERT_2048 << 3)) :
1471 ((pba << 10) - Adapter->max_frame_size)));
1472
1473 hw->fc.high_water = high_water & 0xFFF8;
1474 hw->fc.low_water = hw->fc.high_water - 8;
1475
1476 if (hw->mac.type == e1000_80003es2lan)
1477 hw->fc.pause_time = 0xFFFF;
1478 else
1479 hw->fc.pause_time = E1000_FC_PAUSE_TIME;
1480 hw->fc.send_xon = B_TRUE;
1481
1482 /*
1483 * Reset the adapter hardware the second time.
1484 */
1485 mutex_enter(&e1000g_nvm_lock);
1486 result = e1000_reset_hw(hw);
1487 mutex_exit(&e1000g_nvm_lock);
1488
1489 if (result != E1000_SUCCESS) {
1490 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1491 goto init_fail;
1492 }
1493
1494 /* disable wakeup control by default */
1495 if (hw->mac.type >= e1000_82544)
1496 E1000_WRITE_REG(hw, E1000_WUC, 0);
1497
1498 /*
1499 * MWI should be disabled on 82546.
1500 */
1501 if (hw->mac.type == e1000_82546)
1502 e1000_pci_clear_mwi(hw);
1503 else
1504 e1000_pci_set_mwi(hw);
1505
1506 /*
1507 * Configure/Initialize hardware
1508 */
1509 mutex_enter(&e1000g_nvm_lock);
1510 result = e1000_init_hw(hw);
1511 mutex_exit(&e1000g_nvm_lock);
1512
1513 if (result < E1000_SUCCESS) {
1514 e1000g_log(Adapter, CE_WARN, "Initialize hw failed");
1515 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1516 goto init_fail;
1517 }
1518
1519 /*
1520 * Restore LED settings to the default from EEPROM
1521 * to meet the standard for Sun platforms.
1522 */
1523 (void) e1000_cleanup_led(hw);
1524
1525 /* Disable Smart Power Down */
1526 phy_spd_state(hw, B_FALSE);
1527
1528 /* Make sure driver has control */
1529 e1000g_get_driver_control(hw);
1530
1531 /*
1532 * Initialize unicast addresses.
1533 */
1534 e1000g_init_unicst(Adapter);
1535
1536 /*
1537 * Setup and initialize the mctable structures. After this routine
1538 * completes Multicast table will be set
1539 */
1540 e1000_update_mc_addr_list(hw,
1541 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count);
1542 msec_delay(5);
1543
1544 /*
1545 * Implement Adaptive IFS
1546 */
1547 e1000_reset_adaptive(hw);
1548
1549 /* Setup Interrupt Throttling Register */
1550 if (hw->mac.type >= e1000_82540) {
1551 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate);
1552 } else
1553 Adapter->intr_adaptive = B_FALSE;
1554
1555 /* Start the timer for link setup */
1556 if (hw->mac.autoneg)
1557 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000);
1558 else
1559 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000);
1560
1561 mutex_enter(&Adapter->link_lock);
1562 if (hw->phy.autoneg_wait_to_complete) {
1563 Adapter->link_complete = B_TRUE;
1564 } else {
1565 Adapter->link_complete = B_FALSE;
1566 Adapter->link_tid = timeout(e1000g_link_timer,
1567 (void *)Adapter, link_timeout);
1568 }
1569 mutex_exit(&Adapter->link_lock);
1570
1571 /* Save the state of the phy */
1572 e1000g_get_phy_state(Adapter);
1573
1574 e1000g_param_sync(Adapter);
1575
1576 Adapter->init_count++;
1577
1578 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) {
1579 goto init_fail;
1580 }
1581 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
1582 goto init_fail;
1583 }
1584
1585 Adapter->poll_mode = e1000g_poll_mode;
1586
1587 return (DDI_SUCCESS);
1588
1589 init_fail:
1590 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1591 return (DDI_FAILURE);
1592 }
1593
1594 static int
e1000g_alloc_rx_data(struct e1000g * Adapter)1595 e1000g_alloc_rx_data(struct e1000g *Adapter)
1596 {
1597 e1000g_rx_ring_t *rx_ring;
1598 e1000g_rx_data_t *rx_data;
1599
1600 rx_ring = Adapter->rx_ring;
1601
1602 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP);
1603
1604 if (rx_data == NULL)
1605 return (DDI_FAILURE);
1606
1607 rx_data->priv_devi_node = Adapter->priv_devi_node;
1608 rx_data->rx_ring = rx_ring;
1609
1610 mutex_init(&rx_data->freelist_lock, NULL,
1611 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1612 mutex_init(&rx_data->recycle_lock, NULL,
1613 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1614
1615 rx_ring->rx_data = rx_data;
1616
1617 return (DDI_SUCCESS);
1618 }
1619
1620 void
e1000g_free_rx_pending_buffers(e1000g_rx_data_t * rx_data)1621 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data)
1622 {
1623 rx_sw_packet_t *packet, *next_packet;
1624
1625 if (rx_data == NULL)
1626 return;
1627
1628 packet = rx_data->packet_area;
1629 while (packet != NULL) {
1630 next_packet = packet->next;
1631 e1000g_free_rx_sw_packet(packet, B_TRUE);
1632 packet = next_packet;
1633 }
1634 rx_data->packet_area = NULL;
1635 }
1636
1637 void
e1000g_free_rx_data(e1000g_rx_data_t * rx_data)1638 e1000g_free_rx_data(e1000g_rx_data_t *rx_data)
1639 {
1640 if (rx_data == NULL)
1641 return;
1642
1643 mutex_destroy(&rx_data->freelist_lock);
1644 mutex_destroy(&rx_data->recycle_lock);
1645
1646 kmem_free(rx_data, sizeof (e1000g_rx_data_t));
1647 }
1648
1649 /*
1650 * Check if the link is up
1651 */
1652 static boolean_t
e1000g_link_up(struct e1000g * Adapter)1653 e1000g_link_up(struct e1000g *Adapter)
1654 {
1655 struct e1000_hw *hw = &Adapter->shared;
1656 boolean_t link_up = B_FALSE;
1657
1658 /*
1659 * get_link_status is set in the interrupt handler on link-status-change
1660 * or rx sequence error interrupt. get_link_status will stay
1661 * false until the e1000_check_for_link establishes link only
1662 * for copper adapters.
1663 */
1664 switch (hw->phy.media_type) {
1665 case e1000_media_type_copper:
1666 if (hw->mac.get_link_status) {
1667 (void) e1000_check_for_link(hw);
1668 if ((E1000_READ_REG(hw, E1000_STATUS) &
1669 E1000_STATUS_LU)) {
1670 link_up = B_TRUE;
1671 } else {
1672 link_up = !hw->mac.get_link_status;
1673 }
1674 } else {
1675 link_up = B_TRUE;
1676 }
1677 break;
1678 case e1000_media_type_fiber:
1679 (void) e1000_check_for_link(hw);
1680 link_up = (E1000_READ_REG(hw, E1000_STATUS) &
1681 E1000_STATUS_LU);
1682 break;
1683 case e1000_media_type_internal_serdes:
1684 (void) e1000_check_for_link(hw);
1685 link_up = hw->mac.serdes_has_link;
1686 break;
1687 }
1688
1689 return (link_up);
1690 }
1691
1692 static void
e1000g_m_ioctl(void * arg,queue_t * q,mblk_t * mp)1693 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp)
1694 {
1695 struct iocblk *iocp;
1696 struct e1000g *e1000gp;
1697 enum ioc_reply status;
1698
1699 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr;
1700 iocp->ioc_error = 0;
1701 e1000gp = (struct e1000g *)arg;
1702
1703 ASSERT(e1000gp);
1704 if (e1000gp == NULL) {
1705 miocnak(q, mp, 0, EINVAL);
1706 return;
1707 }
1708
1709 rw_enter(&e1000gp->chip_lock, RW_READER);
1710 if (e1000gp->e1000g_state & E1000G_SUSPENDED) {
1711 rw_exit(&e1000gp->chip_lock);
1712 miocnak(q, mp, 0, EINVAL);
1713 return;
1714 }
1715 rw_exit(&e1000gp->chip_lock);
1716
1717 switch (iocp->ioc_cmd) {
1718
1719 case LB_GET_INFO_SIZE:
1720 case LB_GET_INFO:
1721 case LB_GET_MODE:
1722 case LB_SET_MODE:
1723 status = e1000g_loopback_ioctl(e1000gp, iocp, mp);
1724 break;
1725
1726
1727 #ifdef E1000G_DEBUG
1728 case E1000G_IOC_REG_PEEK:
1729 case E1000G_IOC_REG_POKE:
1730 status = e1000g_pp_ioctl(e1000gp, iocp, mp);
1731 break;
1732 case E1000G_IOC_CHIP_RESET:
1733 e1000gp->reset_count++;
1734 if (e1000g_reset_adapter(e1000gp))
1735 status = IOC_ACK;
1736 else
1737 status = IOC_INVAL;
1738 break;
1739 #endif
1740 default:
1741 status = IOC_INVAL;
1742 break;
1743 }
1744
1745 /*
1746 * Decide how to reply
1747 */
1748 switch (status) {
1749 default:
1750 case IOC_INVAL:
1751 /*
1752 * Error, reply with a NAK and EINVAL or the specified error
1753 */
1754 miocnak(q, mp, 0, iocp->ioc_error == 0 ?
1755 EINVAL : iocp->ioc_error);
1756 break;
1757
1758 case IOC_DONE:
1759 /*
1760 * OK, reply already sent
1761 */
1762 break;
1763
1764 case IOC_ACK:
1765 /*
1766 * OK, reply with an ACK
1767 */
1768 miocack(q, mp, 0, 0);
1769 break;
1770
1771 case IOC_REPLY:
1772 /*
1773 * OK, send prepared reply as ACK or NAK
1774 */
1775 mp->b_datap->db_type = iocp->ioc_error == 0 ?
1776 M_IOCACK : M_IOCNAK;
1777 qreply(q, mp);
1778 break;
1779 }
1780 }
1781
1782 /*
1783 * The default value of e1000g_poll_mode == 0 assumes that the NIC is
1784 * capable of supporting only one interrupt and we shouldn't disable
1785 * the physical interrupt. In this case we let the interrupt come and
1786 * we queue the packets in the rx ring itself in case we are in polling
1787 * mode (better latency but slightly lower performance and a very
1788 * high intrrupt count in mpstat which is harmless).
1789 *
1790 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt
1791 * which can be disabled in poll mode. This gives better overall
1792 * throughput (compared to the mode above), shows very low interrupt
1793 * count but has slightly higher latency since we pick the packets when
1794 * the poll thread does polling.
1795 *
1796 * Currently, this flag should be enabled only while doing performance
1797 * measurement or when it can be guaranteed that entire NIC going
1798 * in poll mode will not harm any traffic like cluster heartbeat etc.
1799 */
1800 int e1000g_poll_mode = 0;
1801
1802 /*
1803 * Called from the upper layers when driver is in polling mode to
1804 * pick up any queued packets. Care should be taken to not block
1805 * this thread.
1806 */
e1000g_poll_ring(void * arg,int bytes_to_pickup)1807 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup)
1808 {
1809 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg;
1810 mblk_t *mp = NULL;
1811 mblk_t *tail;
1812 struct e1000g *adapter;
1813
1814 adapter = rx_ring->adapter;
1815
1816 rw_enter(&adapter->chip_lock, RW_READER);
1817
1818 if (adapter->e1000g_state & E1000G_SUSPENDED) {
1819 rw_exit(&adapter->chip_lock);
1820 return (NULL);
1821 }
1822
1823 mutex_enter(&rx_ring->rx_lock);
1824 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup);
1825 mutex_exit(&rx_ring->rx_lock);
1826 rw_exit(&adapter->chip_lock);
1827 return (mp);
1828 }
1829
1830 static int
e1000g_m_start(void * arg)1831 e1000g_m_start(void *arg)
1832 {
1833 struct e1000g *Adapter = (struct e1000g *)arg;
1834
1835 rw_enter(&Adapter->chip_lock, RW_WRITER);
1836
1837 if (Adapter->e1000g_state & E1000G_SUSPENDED) {
1838 rw_exit(&Adapter->chip_lock);
1839 return (ECANCELED);
1840 }
1841
1842 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) {
1843 rw_exit(&Adapter->chip_lock);
1844 return (ENOTACTIVE);
1845 }
1846
1847 Adapter->e1000g_state |= E1000G_STARTED;
1848
1849 rw_exit(&Adapter->chip_lock);
1850
1851 /* Enable and start the watchdog timer */
1852 enable_watchdog_timer(Adapter);
1853
1854 return (0);
1855 }
1856
1857 static int
e1000g_start(struct e1000g * Adapter,boolean_t global)1858 e1000g_start(struct e1000g *Adapter, boolean_t global)
1859 {
1860 e1000g_rx_data_t *rx_data;
1861
1862 if (global) {
1863 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) {
1864 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed");
1865 goto start_fail;
1866 }
1867
1868 /* Allocate dma resources for descriptors and buffers */
1869 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) {
1870 e1000g_log(Adapter, CE_WARN,
1871 "Alloc DMA resources failed");
1872 goto start_fail;
1873 }
1874 Adapter->rx_buffer_setup = B_FALSE;
1875 }
1876
1877 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) {
1878 if (e1000g_init(Adapter) != DDI_SUCCESS) {
1879 e1000g_log(Adapter, CE_WARN,
1880 "Adapter initialization failed");
1881 goto start_fail;
1882 }
1883 }
1884
1885 /* Setup and initialize the transmit structures */
1886 e1000g_tx_setup(Adapter);
1887 msec_delay(5);
1888
1889 /* Setup and initialize the receive structures */
1890 e1000g_rx_setup(Adapter);
1891 msec_delay(5);
1892
1893 /* Restore the e1000g promiscuous mode */
1894 e1000g_restore_promisc(Adapter);
1895
1896 e1000g_mask_interrupt(Adapter);
1897
1898 Adapter->attach_progress |= ATTACH_PROGRESS_INIT;
1899
1900 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
1901 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1902 goto start_fail;
1903 }
1904
1905 return (DDI_SUCCESS);
1906
1907 start_fail:
1908 rx_data = Adapter->rx_ring->rx_data;
1909
1910 if (global) {
1911 e1000g_release_dma_resources(Adapter);
1912 e1000g_free_rx_pending_buffers(rx_data);
1913 e1000g_free_rx_data(rx_data);
1914 }
1915
1916 mutex_enter(&e1000g_nvm_lock);
1917 (void) e1000_reset_hw(&Adapter->shared);
1918 mutex_exit(&e1000g_nvm_lock);
1919
1920 return (DDI_FAILURE);
1921 }
1922
1923 static void
e1000g_m_stop(void * arg)1924 e1000g_m_stop(void *arg)
1925 {
1926 struct e1000g *Adapter = (struct e1000g *)arg;
1927
1928 /* Drain tx sessions */
1929 (void) e1000g_tx_drain(Adapter);
1930
1931 rw_enter(&Adapter->chip_lock, RW_WRITER);
1932
1933 if (Adapter->e1000g_state & E1000G_SUSPENDED) {
1934 rw_exit(&Adapter->chip_lock);
1935 return;
1936 }
1937 Adapter->e1000g_state &= ~E1000G_STARTED;
1938 e1000g_stop(Adapter, B_TRUE);
1939
1940 rw_exit(&Adapter->chip_lock);
1941
1942 /* Disable and stop all the timers */
1943 disable_watchdog_timer(Adapter);
1944 stop_link_timer(Adapter);
1945 stop_82547_timer(Adapter->tx_ring);
1946 }
1947
1948 static void
e1000g_stop(struct e1000g * Adapter,boolean_t global)1949 e1000g_stop(struct e1000g *Adapter, boolean_t global)
1950 {
1951 private_devi_list_t *devi_node;
1952 e1000g_rx_data_t *rx_data;
1953 int result;
1954
1955 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT;
1956
1957 /* Stop the chip and release pending resources */
1958
1959 /* Tell firmware driver is no longer in control */
1960 e1000g_release_driver_control(&Adapter->shared);
1961
1962 e1000g_clear_all_interrupts(Adapter);
1963
1964 mutex_enter(&e1000g_nvm_lock);
1965 result = e1000_reset_hw(&Adapter->shared);
1966 mutex_exit(&e1000g_nvm_lock);
1967
1968 if (result != E1000_SUCCESS) {
1969 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1970 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1971 }
1972
1973 mutex_enter(&Adapter->link_lock);
1974 Adapter->link_complete = B_FALSE;
1975 mutex_exit(&Adapter->link_lock);
1976
1977 /* Release resources still held by the TX descriptors */
1978 e1000g_tx_clean(Adapter);
1979
1980 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
1981 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1982
1983 /* Clean the pending rx jumbo packet fragment */
1984 e1000g_rx_clean(Adapter);
1985
1986 if (global) {
1987 e1000g_release_dma_resources(Adapter);
1988
1989 mutex_enter(&e1000g_rx_detach_lock);
1990 rx_data = Adapter->rx_ring->rx_data;
1991 rx_data->flag |= E1000G_RX_STOPPED;
1992
1993 if (rx_data->pending_count == 0) {
1994 e1000g_free_rx_pending_buffers(rx_data);
1995 e1000g_free_rx_data(rx_data);
1996 } else {
1997 devi_node = rx_data->priv_devi_node;
1998 if (devi_node != NULL)
1999 atomic_inc_32(&devi_node->pending_rx_count);
2000 else
2001 atomic_inc_32(&Adapter->pending_rx_count);
2002 }
2003 mutex_exit(&e1000g_rx_detach_lock);
2004 }
2005
2006 if (Adapter->link_state != LINK_STATE_UNKNOWN) {
2007 Adapter->link_state = LINK_STATE_UNKNOWN;
2008 if (!Adapter->reset_flag)
2009 mac_link_update(Adapter->mh, Adapter->link_state);
2010 }
2011 }
2012
2013 static void
e1000g_rx_clean(struct e1000g * Adapter)2014 e1000g_rx_clean(struct e1000g *Adapter)
2015 {
2016 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data;
2017
2018 if (rx_data == NULL)
2019 return;
2020
2021 if (rx_data->rx_mblk != NULL) {
2022 freemsg(rx_data->rx_mblk);
2023 rx_data->rx_mblk = NULL;
2024 rx_data->rx_mblk_tail = NULL;
2025 rx_data->rx_mblk_len = 0;
2026 }
2027 }
2028
2029 static void
e1000g_tx_clean(struct e1000g * Adapter)2030 e1000g_tx_clean(struct e1000g *Adapter)
2031 {
2032 e1000g_tx_ring_t *tx_ring;
2033 p_tx_sw_packet_t packet;
2034 mblk_t *mp;
2035 mblk_t *nmp;
2036 uint32_t packet_count;
2037
2038 tx_ring = Adapter->tx_ring;
2039
2040 /*
2041 * Here we don't need to protect the lists using
2042 * the usedlist_lock and freelist_lock, for they
2043 * have been protected by the chip_lock.
2044 */
2045 mp = NULL;
2046 nmp = NULL;
2047 packet_count = 0;
2048 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list);
2049 while (packet != NULL) {
2050 if (packet->mp != NULL) {
2051 /* Assemble the message chain */
2052 if (mp == NULL) {
2053 mp = packet->mp;
2054 nmp = packet->mp;
2055 } else {
2056 nmp->b_next = packet->mp;
2057 nmp = packet->mp;
2058 }
2059 /* Disconnect the message from the sw packet */
2060 packet->mp = NULL;
2061 }
2062
2063 e1000g_free_tx_swpkt(packet);
2064 packet_count++;
2065
2066 packet = (p_tx_sw_packet_t)
2067 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link);
2068 }
2069
2070 if (mp != NULL)
2071 freemsgchain(mp);
2072
2073 if (packet_count > 0) {
2074 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list);
2075 QUEUE_INIT_LIST(&tx_ring->used_list);
2076
2077 /* Setup TX descriptor pointers */
2078 tx_ring->tbd_next = tx_ring->tbd_first;
2079 tx_ring->tbd_oldest = tx_ring->tbd_first;
2080
2081 /* Setup our HW Tx Head & Tail descriptor pointers */
2082 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0);
2083 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0);
2084 }
2085 }
2086
2087 static boolean_t
e1000g_tx_drain(struct e1000g * Adapter)2088 e1000g_tx_drain(struct e1000g *Adapter)
2089 {
2090 int i;
2091 boolean_t done;
2092 e1000g_tx_ring_t *tx_ring;
2093
2094 tx_ring = Adapter->tx_ring;
2095
2096 /* Allow up to 'wsdraintime' for pending xmit's to complete. */
2097 for (i = 0; i < TX_DRAIN_TIME; i++) {
2098 mutex_enter(&tx_ring->usedlist_lock);
2099 done = IS_QUEUE_EMPTY(&tx_ring->used_list);
2100 mutex_exit(&tx_ring->usedlist_lock);
2101
2102 if (done)
2103 break;
2104
2105 msec_delay(1);
2106 }
2107
2108 return (done);
2109 }
2110
2111 static boolean_t
e1000g_rx_drain(struct e1000g * Adapter)2112 e1000g_rx_drain(struct e1000g *Adapter)
2113 {
2114 int i;
2115 boolean_t done;
2116
2117 /*
2118 * Allow up to RX_DRAIN_TIME for pending received packets to complete.
2119 */
2120 for (i = 0; i < RX_DRAIN_TIME; i++) {
2121 done = (Adapter->pending_rx_count == 0);
2122
2123 if (done)
2124 break;
2125
2126 msec_delay(1);
2127 }
2128
2129 return (done);
2130 }
2131
2132 static boolean_t
e1000g_reset_adapter(struct e1000g * Adapter)2133 e1000g_reset_adapter(struct e1000g *Adapter)
2134 {
2135 /* Disable and stop all the timers */
2136 disable_watchdog_timer(Adapter);
2137 stop_link_timer(Adapter);
2138 stop_82547_timer(Adapter->tx_ring);
2139
2140 rw_enter(&Adapter->chip_lock, RW_WRITER);
2141
2142 if (Adapter->stall_flag) {
2143 Adapter->stall_flag = B_FALSE;
2144 Adapter->reset_flag = B_TRUE;
2145 }
2146
2147 if (!(Adapter->e1000g_state & E1000G_STARTED)) {
2148 rw_exit(&Adapter->chip_lock);
2149 return (B_TRUE);
2150 }
2151
2152 e1000g_stop(Adapter, B_FALSE);
2153
2154 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) {
2155 rw_exit(&Adapter->chip_lock);
2156 e1000g_log(Adapter, CE_WARN, "Reset failed");
2157 return (B_FALSE);
2158 }
2159
2160 rw_exit(&Adapter->chip_lock);
2161
2162 /* Enable and start the watchdog timer */
2163 enable_watchdog_timer(Adapter);
2164
2165 return (B_TRUE);
2166 }
2167
2168 boolean_t
e1000g_global_reset(struct e1000g * Adapter)2169 e1000g_global_reset(struct e1000g *Adapter)
2170 {
2171 /* Disable and stop all the timers */
2172 disable_watchdog_timer(Adapter);
2173 stop_link_timer(Adapter);
2174 stop_82547_timer(Adapter->tx_ring);
2175
2176 rw_enter(&Adapter->chip_lock, RW_WRITER);
2177
2178 e1000g_stop(Adapter, B_TRUE);
2179
2180 Adapter->init_count = 0;
2181
2182 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) {
2183 rw_exit(&Adapter->chip_lock);
2184 e1000g_log(Adapter, CE_WARN, "Reset failed");
2185 return (B_FALSE);
2186 }
2187
2188 rw_exit(&Adapter->chip_lock);
2189
2190 /* Enable and start the watchdog timer */
2191 enable_watchdog_timer(Adapter);
2192
2193 return (B_TRUE);
2194 }
2195
2196 /*
2197 * e1000g_intr_pciexpress - ISR for PCI Express chipsets
2198 *
2199 * This interrupt service routine is for PCI-Express adapters.
2200 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED
2201 * bit is set.
2202 */
2203 static uint_t
e1000g_intr_pciexpress(caddr_t arg)2204 e1000g_intr_pciexpress(caddr_t arg)
2205 {
2206 struct e1000g *Adapter;
2207 uint32_t icr;
2208
2209 Adapter = (struct e1000g *)(uintptr_t)arg;
2210 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR);
2211
2212 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2213 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2214 return (DDI_INTR_CLAIMED);
2215 }
2216
2217 if (icr & E1000_ICR_INT_ASSERTED) {
2218 /*
2219 * E1000_ICR_INT_ASSERTED bit was set:
2220 * Read(Clear) the ICR, claim this interrupt,
2221 * look for work to do.
2222 */
2223 e1000g_intr_work(Adapter, icr);
2224 return (DDI_INTR_CLAIMED);
2225 } else {
2226 /*
2227 * E1000_ICR_INT_ASSERTED bit was not set:
2228 * Don't claim this interrupt, return immediately.
2229 */
2230 return (DDI_INTR_UNCLAIMED);
2231 }
2232 }
2233
2234 /*
2235 * e1000g_intr - ISR for PCI/PCI-X chipsets
2236 *
2237 * This interrupt service routine is for PCI/PCI-X adapters.
2238 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED
2239 * bit is set or not.
2240 */
2241 static uint_t
e1000g_intr(caddr_t arg)2242 e1000g_intr(caddr_t arg)
2243 {
2244 struct e1000g *Adapter;
2245 uint32_t icr;
2246
2247 Adapter = (struct e1000g *)(uintptr_t)arg;
2248 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR);
2249
2250 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2251 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2252 return (DDI_INTR_CLAIMED);
2253 }
2254
2255 if (icr) {
2256 /*
2257 * Any bit was set in ICR:
2258 * Read(Clear) the ICR, claim this interrupt,
2259 * look for work to do.
2260 */
2261 e1000g_intr_work(Adapter, icr);
2262 return (DDI_INTR_CLAIMED);
2263 } else {
2264 /*
2265 * No bit was set in ICR:
2266 * Don't claim this interrupt, return immediately.
2267 */
2268 return (DDI_INTR_UNCLAIMED);
2269 }
2270 }
2271
2272 /*
2273 * e1000g_intr_work - actual processing of ISR
2274 *
2275 * Read(clear) the ICR contents and call appropriate interrupt
2276 * processing routines.
2277 */
2278 static void
e1000g_intr_work(struct e1000g * Adapter,uint32_t icr)2279 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr)
2280 {
2281 struct e1000_hw *hw;
2282 hw = &Adapter->shared;
2283 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring;
2284
2285 Adapter->rx_pkt_cnt = 0;
2286 Adapter->tx_pkt_cnt = 0;
2287
2288 rw_enter(&Adapter->chip_lock, RW_READER);
2289
2290 if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2291 rw_exit(&Adapter->chip_lock);
2292 return;
2293 }
2294 /*
2295 * Here we need to check the "e1000g_state" flag within the chip_lock to
2296 * ensure the receive routine will not execute when the adapter is
2297 * being reset.
2298 */
2299 if (!(Adapter->e1000g_state & E1000G_STARTED)) {
2300 rw_exit(&Adapter->chip_lock);
2301 return;
2302 }
2303
2304 if (icr & E1000_ICR_RXT0) {
2305 mblk_t *mp = NULL;
2306 mblk_t *tail = NULL;
2307 e1000g_rx_ring_t *rx_ring;
2308
2309 rx_ring = Adapter->rx_ring;
2310 mutex_enter(&rx_ring->rx_lock);
2311 /*
2312 * Sometimes with legacy interrupts, it possible that
2313 * there is a single interrupt for Rx/Tx. In which
2314 * case, if poll flag is set, we shouldn't really
2315 * be doing Rx processing.
2316 */
2317 if (!rx_ring->poll_flag)
2318 mp = e1000g_receive(rx_ring, &tail,
2319 E1000G_CHAIN_NO_LIMIT);
2320 mutex_exit(&rx_ring->rx_lock);
2321 rw_exit(&Adapter->chip_lock);
2322 if (mp != NULL)
2323 mac_rx_ring(Adapter->mh, rx_ring->mrh,
2324 mp, rx_ring->ring_gen_num);
2325 } else
2326 rw_exit(&Adapter->chip_lock);
2327
2328 if (icr & E1000_ICR_TXDW) {
2329 if (!Adapter->tx_intr_enable)
2330 e1000g_clear_tx_interrupt(Adapter);
2331
2332 /* Recycle the tx descriptors */
2333 rw_enter(&Adapter->chip_lock, RW_READER);
2334 (void) e1000g_recycle(tx_ring);
2335 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr);
2336 rw_exit(&Adapter->chip_lock);
2337
2338 if (tx_ring->resched_needed &&
2339 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) {
2340 tx_ring->resched_needed = B_FALSE;
2341 mac_tx_update(Adapter->mh);
2342 E1000G_STAT(tx_ring->stat_reschedule);
2343 }
2344 }
2345
2346 /*
2347 * The Receive Sequence errors RXSEQ and the link status change LSC
2348 * are checked to detect that the cable has been pulled out. For
2349 * the Wiseman 2.0 silicon, the receive sequence errors interrupt
2350 * are an indication that cable is not connected.
2351 */
2352 if ((icr & E1000_ICR_RXSEQ) ||
2353 (icr & E1000_ICR_LSC) ||
2354 (icr & E1000_ICR_GPI_EN1)) {
2355 boolean_t link_changed;
2356 timeout_id_t tid = 0;
2357
2358 stop_watchdog_timer(Adapter);
2359
2360 rw_enter(&Adapter->chip_lock, RW_WRITER);
2361
2362 /*
2363 * Because we got a link-status-change interrupt, force
2364 * e1000_check_for_link() to look at phy
2365 */
2366 Adapter->shared.mac.get_link_status = B_TRUE;
2367
2368 /* e1000g_link_check takes care of link status change */
2369 link_changed = e1000g_link_check(Adapter);
2370
2371 /* Get new phy state */
2372 e1000g_get_phy_state(Adapter);
2373
2374 /*
2375 * If the link timer has not timed out, we'll not notify
2376 * the upper layer with any link state until the link is up.
2377 */
2378 if (link_changed && !Adapter->link_complete) {
2379 if (Adapter->link_state == LINK_STATE_UP) {
2380 mutex_enter(&Adapter->link_lock);
2381 Adapter->link_complete = B_TRUE;
2382 tid = Adapter->link_tid;
2383 Adapter->link_tid = 0;
2384 mutex_exit(&Adapter->link_lock);
2385 } else {
2386 link_changed = B_FALSE;
2387 }
2388 }
2389 rw_exit(&Adapter->chip_lock);
2390
2391 if (link_changed) {
2392 if (tid != 0)
2393 (void) untimeout(tid);
2394
2395 /*
2396 * Workaround for esb2. Data stuck in fifo on a link
2397 * down event. Stop receiver here and reset in watchdog.
2398 */
2399 if ((Adapter->link_state == LINK_STATE_DOWN) &&
2400 (Adapter->shared.mac.type == e1000_80003es2lan)) {
2401 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
2402 E1000_WRITE_REG(hw, E1000_RCTL,
2403 rctl & ~E1000_RCTL_EN);
2404 e1000g_log(Adapter, CE_WARN,
2405 "ESB2 receiver disabled");
2406 Adapter->esb2_workaround = B_TRUE;
2407 }
2408 if (!Adapter->reset_flag)
2409 mac_link_update(Adapter->mh,
2410 Adapter->link_state);
2411 if (Adapter->link_state == LINK_STATE_UP)
2412 Adapter->reset_flag = B_FALSE;
2413 }
2414
2415 start_watchdog_timer(Adapter);
2416 }
2417 }
2418
2419 static void
e1000g_init_unicst(struct e1000g * Adapter)2420 e1000g_init_unicst(struct e1000g *Adapter)
2421 {
2422 struct e1000_hw *hw;
2423 int slot;
2424
2425 hw = &Adapter->shared;
2426
2427 if (Adapter->init_count == 0) {
2428 /* Initialize the multiple unicast addresses */
2429 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES;
2430
2431 /* Workaround for an erratum of 82571 chipst */
2432 if ((hw->mac.type == e1000_82571) &&
2433 (e1000_get_laa_state_82571(hw) == B_TRUE))
2434 Adapter->unicst_total--;
2435
2436 Adapter->unicst_avail = Adapter->unicst_total;
2437
2438 for (slot = 0; slot < Adapter->unicst_total; slot++) {
2439 /* Clear both the flag and MAC address */
2440 Adapter->unicst_addr[slot].reg.high = 0;
2441 Adapter->unicst_addr[slot].reg.low = 0;
2442 }
2443 } else {
2444 /* Workaround for an erratum of 82571 chipst */
2445 if ((hw->mac.type == e1000_82571) &&
2446 (e1000_get_laa_state_82571(hw) == B_TRUE))
2447 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY);
2448
2449 /* Re-configure the RAR registers */
2450 for (slot = 0; slot < Adapter->unicst_total; slot++)
2451 if (Adapter->unicst_addr[slot].mac.set == 1)
2452 e1000_rar_set(hw,
2453 Adapter->unicst_addr[slot].mac.addr, slot);
2454 }
2455
2456 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
2457 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2458 }
2459
2460 static int
e1000g_unicst_set(struct e1000g * Adapter,const uint8_t * mac_addr,int slot)2461 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr,
2462 int slot)
2463 {
2464 struct e1000_hw *hw;
2465
2466 hw = &Adapter->shared;
2467
2468 /*
2469 * The first revision of Wiseman silicon (rev 2.0) has an errata
2470 * that requires the receiver to be in reset when any of the
2471 * receive address registers (RAR regs) are accessed. The first
2472 * rev of Wiseman silicon also requires MWI to be disabled when
2473 * a global reset or a receive reset is issued. So before we
2474 * initialize the RARs, we check the rev of the Wiseman controller
2475 * and work around any necessary HW errata.
2476 */
2477 if ((hw->mac.type == e1000_82542) &&
2478 (hw->revision_id == E1000_REVISION_2)) {
2479 e1000_pci_clear_mwi(hw);
2480 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
2481 msec_delay(5);
2482 }
2483 if (mac_addr == NULL) {
2484 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0);
2485 E1000_WRITE_FLUSH(hw);
2486 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0);
2487 E1000_WRITE_FLUSH(hw);
2488 /* Clear both the flag and MAC address */
2489 Adapter->unicst_addr[slot].reg.high = 0;
2490 Adapter->unicst_addr[slot].reg.low = 0;
2491 } else {
2492 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr,
2493 ETHERADDRL);
2494 e1000_rar_set(hw, (uint8_t *)mac_addr, slot);
2495 Adapter->unicst_addr[slot].mac.set = 1;
2496 }
2497
2498 /* Workaround for an erratum of 82571 chipst */
2499 if (slot == 0) {
2500 if ((hw->mac.type == e1000_82571) &&
2501 (e1000_get_laa_state_82571(hw) == B_TRUE))
2502 if (mac_addr == NULL) {
2503 E1000_WRITE_REG_ARRAY(hw, E1000_RA,
2504 slot << 1, 0);
2505 E1000_WRITE_FLUSH(hw);
2506 E1000_WRITE_REG_ARRAY(hw, E1000_RA,
2507 (slot << 1) + 1, 0);
2508 E1000_WRITE_FLUSH(hw);
2509 } else {
2510 e1000_rar_set(hw, (uint8_t *)mac_addr,
2511 LAST_RAR_ENTRY);
2512 }
2513 }
2514
2515 /*
2516 * If we are using Wiseman rev 2.0 silicon, we will have previously
2517 * put the receive in reset, and disabled MWI, to work around some
2518 * HW errata. Now we should take the receiver out of reset, and
2519 * re-enabled if MWI if it was previously enabled by the PCI BIOS.
2520 */
2521 if ((hw->mac.type == e1000_82542) &&
2522 (hw->revision_id == E1000_REVISION_2)) {
2523 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2524 msec_delay(1);
2525 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2526 e1000_pci_set_mwi(hw);
2527 e1000g_rx_setup(Adapter);
2528 }
2529
2530 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2531 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2532 return (EIO);
2533 }
2534
2535 return (0);
2536 }
2537
2538 static int
multicst_add(struct e1000g * Adapter,const uint8_t * multiaddr)2539 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr)
2540 {
2541 struct e1000_hw *hw = &Adapter->shared;
2542 struct ether_addr *newtable;
2543 size_t new_len;
2544 size_t old_len;
2545 int res = 0;
2546
2547 if ((multiaddr[0] & 01) == 0) {
2548 res = EINVAL;
2549 e1000g_log(Adapter, CE_WARN, "Illegal multicast address");
2550 goto done;
2551 }
2552
2553 if (Adapter->mcast_count >= Adapter->mcast_max_num) {
2554 res = ENOENT;
2555 e1000g_log(Adapter, CE_WARN,
2556 "Adapter requested more than %d mcast addresses",
2557 Adapter->mcast_max_num);
2558 goto done;
2559 }
2560
2561
2562 if (Adapter->mcast_count == Adapter->mcast_alloc_count) {
2563 old_len = Adapter->mcast_alloc_count *
2564 sizeof (struct ether_addr);
2565 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) *
2566 sizeof (struct ether_addr);
2567
2568 newtable = kmem_alloc(new_len, KM_NOSLEEP);
2569 if (newtable == NULL) {
2570 res = ENOMEM;
2571 e1000g_log(Adapter, CE_WARN,
2572 "Not enough memory to alloc mcast table");
2573 goto done;
2574 }
2575
2576 if (Adapter->mcast_table != NULL) {
2577 bcopy(Adapter->mcast_table, newtable, old_len);
2578 kmem_free(Adapter->mcast_table, old_len);
2579 }
2580 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE;
2581 Adapter->mcast_table = newtable;
2582 }
2583
2584 bcopy(multiaddr,
2585 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL);
2586 Adapter->mcast_count++;
2587
2588 /*
2589 * Update the MC table in the hardware
2590 */
2591 e1000g_clear_interrupt(Adapter);
2592
2593 e1000_update_mc_addr_list(hw,
2594 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count);
2595
2596 e1000g_mask_interrupt(Adapter);
2597
2598 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2599 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2600 res = EIO;
2601 }
2602
2603 done:
2604 return (res);
2605 }
2606
2607 static int
multicst_remove(struct e1000g * Adapter,const uint8_t * multiaddr)2608 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr)
2609 {
2610 struct e1000_hw *hw = &Adapter->shared;
2611 struct ether_addr *newtable;
2612 size_t new_len;
2613 size_t old_len;
2614 unsigned i;
2615
2616 for (i = 0; i < Adapter->mcast_count; i++) {
2617 if (bcmp(multiaddr, &Adapter->mcast_table[i],
2618 ETHERADDRL) == 0) {
2619 for (i++; i < Adapter->mcast_count; i++) {
2620 Adapter->mcast_table[i - 1] =
2621 Adapter->mcast_table[i];
2622 }
2623 Adapter->mcast_count--;
2624 break;
2625 }
2626 }
2627
2628 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) >
2629 MCAST_ALLOC_SIZE) {
2630 old_len = Adapter->mcast_alloc_count *
2631 sizeof (struct ether_addr);
2632 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) *
2633 sizeof (struct ether_addr);
2634
2635 newtable = kmem_alloc(new_len, KM_NOSLEEP);
2636 if (newtable != NULL) {
2637 bcopy(Adapter->mcast_table, newtable, new_len);
2638 kmem_free(Adapter->mcast_table, old_len);
2639
2640 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE;
2641 Adapter->mcast_table = newtable;
2642 }
2643 }
2644
2645 /*
2646 * Update the MC table in the hardware
2647 */
2648 e1000g_clear_interrupt(Adapter);
2649
2650 e1000_update_mc_addr_list(hw,
2651 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count);
2652
2653 e1000g_mask_interrupt(Adapter);
2654
2655 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2656 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2657 return (EIO);
2658 }
2659
2660 return (0);
2661 }
2662
2663 static void
e1000g_release_multicast(struct e1000g * Adapter)2664 e1000g_release_multicast(struct e1000g *Adapter)
2665 {
2666 if (Adapter->mcast_table != NULL) {
2667 kmem_free(Adapter->mcast_table,
2668 Adapter->mcast_alloc_count * sizeof (struct ether_addr));
2669 Adapter->mcast_table = NULL;
2670 }
2671 }
2672
2673 int
e1000g_m_multicst(void * arg,boolean_t add,const uint8_t * addr)2674 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr)
2675 {
2676 struct e1000g *Adapter = (struct e1000g *)arg;
2677 int result;
2678
2679 rw_enter(&Adapter->chip_lock, RW_WRITER);
2680
2681 if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2682 result = ECANCELED;
2683 goto done;
2684 }
2685
2686 result = (add) ? multicst_add(Adapter, addr)
2687 : multicst_remove(Adapter, addr);
2688
2689 done:
2690 rw_exit(&Adapter->chip_lock);
2691 return (result);
2692
2693 }
2694
2695 int
e1000g_m_promisc(void * arg,boolean_t on)2696 e1000g_m_promisc(void *arg, boolean_t on)
2697 {
2698 struct e1000g *Adapter = (struct e1000g *)arg;
2699 uint32_t rctl;
2700
2701 rw_enter(&Adapter->chip_lock, RW_WRITER);
2702
2703 if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2704 rw_exit(&Adapter->chip_lock);
2705 return (ECANCELED);
2706 }
2707
2708 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL);
2709
2710 if (on)
2711 rctl |=
2712 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM);
2713 else
2714 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE));
2715
2716 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl);
2717
2718 Adapter->e1000g_promisc = on;
2719
2720 rw_exit(&Adapter->chip_lock);
2721
2722 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2723 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2724 return (EIO);
2725 }
2726
2727 return (0);
2728 }
2729
2730 /*
2731 * Entry points to enable and disable interrupts at the granularity of
2732 * a group.
2733 * Turns the poll_mode for the whole adapter on and off to enable or
2734 * override the ring level polling control over the hardware interrupts.
2735 */
2736 static int
e1000g_rx_group_intr_enable(mac_intr_handle_t arg)2737 e1000g_rx_group_intr_enable(mac_intr_handle_t arg)
2738 {
2739 struct e1000g *adapter = (struct e1000g *)arg;
2740 e1000g_rx_ring_t *rx_ring = adapter->rx_ring;
2741
2742 /*
2743 * Later interrupts at the granularity of the this ring will
2744 * invoke mac_rx() with NULL, indicating the need for another
2745 * software classification.
2746 * We have a single ring usable per adapter now, so we only need to
2747 * reset the rx handle for that one.
2748 * When more RX rings can be used, we should update each one of them.
2749 */
2750 mutex_enter(&rx_ring->rx_lock);
2751 rx_ring->mrh = NULL;
2752 adapter->poll_mode = B_FALSE;
2753 mutex_exit(&rx_ring->rx_lock);
2754 return (0);
2755 }
2756
2757 static int
e1000g_rx_group_intr_disable(mac_intr_handle_t arg)2758 e1000g_rx_group_intr_disable(mac_intr_handle_t arg)
2759 {
2760 struct e1000g *adapter = (struct e1000g *)arg;
2761 e1000g_rx_ring_t *rx_ring = adapter->rx_ring;
2762
2763 mutex_enter(&rx_ring->rx_lock);
2764
2765 /*
2766 * Later interrupts at the granularity of the this ring will
2767 * invoke mac_rx() with the handle for this ring;
2768 */
2769 adapter->poll_mode = B_TRUE;
2770 rx_ring->mrh = rx_ring->mrh_init;
2771 mutex_exit(&rx_ring->rx_lock);
2772 return (0);
2773 }
2774
2775 /*
2776 * Entry points to enable and disable interrupts at the granularity of
2777 * a ring.
2778 * adapter poll_mode controls whether we actually proceed with hardware
2779 * interrupt toggling.
2780 */
2781 static int
e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh)2782 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh)
2783 {
2784 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh;
2785 struct e1000g *adapter = rx_ring->adapter;
2786 struct e1000_hw *hw = &adapter->shared;
2787 uint32_t intr_mask;
2788
2789 rw_enter(&adapter->chip_lock, RW_READER);
2790
2791 if (adapter->e1000g_state & E1000G_SUSPENDED) {
2792 rw_exit(&adapter->chip_lock);
2793 return (0);
2794 }
2795
2796 mutex_enter(&rx_ring->rx_lock);
2797 rx_ring->poll_flag = 0;
2798 mutex_exit(&rx_ring->rx_lock);
2799
2800 /* Rx interrupt enabling for MSI and legacy */
2801 intr_mask = E1000_READ_REG(hw, E1000_IMS);
2802 intr_mask |= E1000_IMS_RXT0;
2803 E1000_WRITE_REG(hw, E1000_IMS, intr_mask);
2804 E1000_WRITE_FLUSH(hw);
2805
2806 /* Trigger a Rx interrupt to check Rx ring */
2807 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0);
2808 E1000_WRITE_FLUSH(hw);
2809
2810 rw_exit(&adapter->chip_lock);
2811 return (0);
2812 }
2813
2814 static int
e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh)2815 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh)
2816 {
2817 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh;
2818 struct e1000g *adapter = rx_ring->adapter;
2819 struct e1000_hw *hw = &adapter->shared;
2820
2821 rw_enter(&adapter->chip_lock, RW_READER);
2822
2823 if (adapter->e1000g_state & E1000G_SUSPENDED) {
2824 rw_exit(&adapter->chip_lock);
2825 return (0);
2826 }
2827 mutex_enter(&rx_ring->rx_lock);
2828 rx_ring->poll_flag = 1;
2829 mutex_exit(&rx_ring->rx_lock);
2830
2831 /* Rx interrupt disabling for MSI and legacy */
2832 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
2833 E1000_WRITE_FLUSH(hw);
2834
2835 rw_exit(&adapter->chip_lock);
2836 return (0);
2837 }
2838
2839 /*
2840 * e1000g_unicst_find - Find the slot for the specified unicast address
2841 */
2842 static int
e1000g_unicst_find(struct e1000g * Adapter,const uint8_t * mac_addr)2843 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr)
2844 {
2845 int slot;
2846
2847 for (slot = 0; slot < Adapter->unicst_total; slot++) {
2848 if ((Adapter->unicst_addr[slot].mac.set == 1) &&
2849 (bcmp(Adapter->unicst_addr[slot].mac.addr,
2850 mac_addr, ETHERADDRL) == 0))
2851 return (slot);
2852 }
2853
2854 return (-1);
2855 }
2856
2857 /*
2858 * Entry points to add and remove a MAC address to a ring group.
2859 * The caller takes care of adding and removing the MAC addresses
2860 * to the filter via these two routines.
2861 */
2862
2863 static int
e1000g_addmac(void * arg,const uint8_t * mac_addr)2864 e1000g_addmac(void *arg, const uint8_t *mac_addr)
2865 {
2866 struct e1000g *Adapter = (struct e1000g *)arg;
2867 int slot, err;
2868
2869 rw_enter(&Adapter->chip_lock, RW_WRITER);
2870
2871 if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2872 rw_exit(&Adapter->chip_lock);
2873 return (ECANCELED);
2874 }
2875
2876 if (e1000g_unicst_find(Adapter, mac_addr) != -1) {
2877 /* The same address is already in slot */
2878 rw_exit(&Adapter->chip_lock);
2879 return (0);
2880 }
2881
2882 if (Adapter->unicst_avail == 0) {
2883 /* no slots available */
2884 rw_exit(&Adapter->chip_lock);
2885 return (ENOSPC);
2886 }
2887
2888 /* Search for a free slot */
2889 for (slot = 0; slot < Adapter->unicst_total; slot++) {
2890 if (Adapter->unicst_addr[slot].mac.set == 0)
2891 break;
2892 }
2893 ASSERT(slot < Adapter->unicst_total);
2894
2895 err = e1000g_unicst_set(Adapter, mac_addr, slot);
2896 if (err == 0)
2897 Adapter->unicst_avail--;
2898
2899 rw_exit(&Adapter->chip_lock);
2900
2901 return (err);
2902 }
2903
2904 static int
e1000g_remmac(void * arg,const uint8_t * mac_addr)2905 e1000g_remmac(void *arg, const uint8_t *mac_addr)
2906 {
2907 struct e1000g *Adapter = (struct e1000g *)arg;
2908 int slot, err;
2909
2910 rw_enter(&Adapter->chip_lock, RW_WRITER);
2911
2912 if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2913 rw_exit(&Adapter->chip_lock);
2914 return (ECANCELED);
2915 }
2916
2917 slot = e1000g_unicst_find(Adapter, mac_addr);
2918 if (slot == -1) {
2919 rw_exit(&Adapter->chip_lock);
2920 return (EINVAL);
2921 }
2922
2923 ASSERT(Adapter->unicst_addr[slot].mac.set);
2924
2925 /* Clear this slot */
2926 err = e1000g_unicst_set(Adapter, NULL, slot);
2927 if (err == 0)
2928 Adapter->unicst_avail++;
2929
2930 rw_exit(&Adapter->chip_lock);
2931
2932 return (err);
2933 }
2934
2935 static int
e1000g_ring_start(mac_ring_driver_t rh,uint64_t mr_gen_num)2936 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num)
2937 {
2938 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh;
2939
2940 mutex_enter(&rx_ring->rx_lock);
2941 rx_ring->ring_gen_num = mr_gen_num;
2942 mutex_exit(&rx_ring->rx_lock);
2943 return (0);
2944 }
2945
2946 /*
2947 * Callback funtion for MAC layer to register all rings.
2948 *
2949 * The hardware supports a single group with currently only one ring
2950 * available.
2951 * Though not offering virtualization ability per se, exposing the
2952 * group/ring still enables the polling and interrupt toggling.
2953 */
2954 /* ARGSUSED */
2955 void
e1000g_fill_ring(void * arg,mac_ring_type_t rtype,const int grp_index,const int ring_index,mac_ring_info_t * infop,mac_ring_handle_t rh)2956 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index,
2957 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh)
2958 {
2959 struct e1000g *Adapter = (struct e1000g *)arg;
2960 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring;
2961 mac_intr_t *mintr;
2962
2963 /*
2964 * We advertised only RX group/rings, so the MAC framework shouldn't
2965 * ask for any thing else.
2966 */
2967 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0);
2968
2969 rx_ring->mrh = rx_ring->mrh_init = rh;
2970 infop->mri_driver = (mac_ring_driver_t)rx_ring;
2971 infop->mri_start = e1000g_ring_start;
2972 infop->mri_stop = NULL;
2973 infop->mri_poll = e1000g_poll_ring;
2974 infop->mri_stat = e1000g_rx_ring_stat;
2975
2976 /* Ring level interrupts */
2977 mintr = &infop->mri_intr;
2978 mintr->mi_handle = (mac_intr_handle_t)rx_ring;
2979 mintr->mi_enable = e1000g_rx_ring_intr_enable;
2980 mintr->mi_disable = e1000g_rx_ring_intr_disable;
2981 if (Adapter->msi_enable)
2982 mintr->mi_ddi_handle = Adapter->htable[0];
2983 }
2984
2985 /* ARGSUSED */
2986 static void
e1000g_fill_group(void * arg,mac_ring_type_t rtype,const int grp_index,mac_group_info_t * infop,mac_group_handle_t gh)2987 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index,
2988 mac_group_info_t *infop, mac_group_handle_t gh)
2989 {
2990 struct e1000g *Adapter = (struct e1000g *)arg;
2991 mac_intr_t *mintr;
2992
2993 /*
2994 * We advertised a single RX ring. Getting a request for anything else
2995 * signifies a bug in the MAC framework.
2996 */
2997 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0);
2998
2999 Adapter->rx_group = gh;
3000
3001 infop->mgi_driver = (mac_group_driver_t)Adapter;
3002 infop->mgi_start = NULL;
3003 infop->mgi_stop = NULL;
3004 infop->mgi_addmac = e1000g_addmac;
3005 infop->mgi_remmac = e1000g_remmac;
3006 infop->mgi_count = 1;
3007
3008 /* Group level interrupts */
3009 mintr = &infop->mgi_intr;
3010 mintr->mi_handle = (mac_intr_handle_t)Adapter;
3011 mintr->mi_enable = e1000g_rx_group_intr_enable;
3012 mintr->mi_disable = e1000g_rx_group_intr_disable;
3013 }
3014
3015 static boolean_t
e1000g_m_getcapab(void * arg,mac_capab_t cap,void * cap_data)3016 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
3017 {
3018 struct e1000g *Adapter = (struct e1000g *)arg;
3019
3020 switch (cap) {
3021 case MAC_CAPAB_HCKSUM: {
3022 uint32_t *txflags = cap_data;
3023
3024 if (Adapter->tx_hcksum_enable)
3025 *txflags = HCKSUM_IPHDRCKSUM |
3026 HCKSUM_INET_PARTIAL;
3027 else
3028 return (B_FALSE);
3029 break;
3030 }
3031
3032 case MAC_CAPAB_LSO: {
3033 mac_capab_lso_t *cap_lso = cap_data;
3034
3035 if (Adapter->lso_enable) {
3036 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4;
3037 cap_lso->lso_basic_tcp_ipv4.lso_max =
3038 E1000_LSO_MAXLEN;
3039 } else
3040 return (B_FALSE);
3041 break;
3042 }
3043 case MAC_CAPAB_RINGS: {
3044 mac_capab_rings_t *cap_rings = cap_data;
3045
3046 /* No TX rings exposed yet */
3047 if (cap_rings->mr_type != MAC_RING_TYPE_RX)
3048 return (B_FALSE);
3049
3050 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
3051 cap_rings->mr_rnum = 1;
3052 cap_rings->mr_gnum = 1;
3053 cap_rings->mr_rget = e1000g_fill_ring;
3054 cap_rings->mr_gget = e1000g_fill_group;
3055 break;
3056 }
3057 default:
3058 return (B_FALSE);
3059 }
3060 return (B_TRUE);
3061 }
3062
3063 static boolean_t
e1000g_param_locked(mac_prop_id_t pr_num)3064 e1000g_param_locked(mac_prop_id_t pr_num)
3065 {
3066 /*
3067 * All en_* parameters are locked (read-only) while
3068 * the device is in any sort of loopback mode ...
3069 */
3070 switch (pr_num) {
3071 case MAC_PROP_EN_1000FDX_CAP:
3072 case MAC_PROP_EN_1000HDX_CAP:
3073 case MAC_PROP_EN_100FDX_CAP:
3074 case MAC_PROP_EN_100HDX_CAP:
3075 case MAC_PROP_EN_10FDX_CAP:
3076 case MAC_PROP_EN_10HDX_CAP:
3077 case MAC_PROP_AUTONEG:
3078 case MAC_PROP_FLOWCTRL:
3079 return (B_TRUE);
3080 }
3081 return (B_FALSE);
3082 }
3083
3084 /*
3085 * callback function for set/get of properties
3086 */
3087 static int
e1000g_m_setprop(void * arg,const char * pr_name,mac_prop_id_t pr_num,uint_t pr_valsize,const void * pr_val)3088 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num,
3089 uint_t pr_valsize, const void *pr_val)
3090 {
3091 struct e1000g *Adapter = arg;
3092 struct e1000_hw *hw = &Adapter->shared;
3093 struct e1000_fc_info *fc = &Adapter->shared.fc;
3094 int err = 0;
3095 link_flowctrl_t flowctrl;
3096 uint32_t cur_mtu, new_mtu;
3097
3098 rw_enter(&Adapter->chip_lock, RW_WRITER);
3099
3100 if (Adapter->e1000g_state & E1000G_SUSPENDED) {
3101 rw_exit(&Adapter->chip_lock);
3102 return (ECANCELED);
3103 }
3104
3105 if (Adapter->loopback_mode != E1000G_LB_NONE &&
3106 e1000g_param_locked(pr_num)) {
3107 /*
3108 * All en_* parameters are locked (read-only)
3109 * while the device is in any sort of loopback mode.
3110 */
3111 rw_exit(&Adapter->chip_lock);
3112 return (EBUSY);
3113 }
3114
3115 switch (pr_num) {
3116 case MAC_PROP_EN_1000FDX_CAP:
3117 if (hw->phy.media_type != e1000_media_type_copper) {
3118 err = ENOTSUP;
3119 break;
3120 }
3121 Adapter->param_en_1000fdx = *(uint8_t *)pr_val;
3122 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val;
3123 goto reset;
3124 case MAC_PROP_EN_100FDX_CAP:
3125 if (hw->phy.media_type != e1000_media_type_copper) {
3126 err = ENOTSUP;
3127 break;
3128 }
3129 Adapter->param_en_100fdx = *(uint8_t *)pr_val;
3130 Adapter->param_adv_100fdx = *(uint8_t *)pr_val;
3131 goto reset;
3132 case MAC_PROP_EN_100HDX_CAP:
3133 if (hw->phy.media_type != e1000_media_type_copper) {
3134 err = ENOTSUP;
3135 break;
3136 }
3137 Adapter->param_en_100hdx = *(uint8_t *)pr_val;
3138 Adapter->param_adv_100hdx = *(uint8_t *)pr_val;
3139 goto reset;
3140 case MAC_PROP_EN_10FDX_CAP:
3141 if (hw->phy.media_type != e1000_media_type_copper) {
3142 err = ENOTSUP;
3143 break;
3144 }
3145 Adapter->param_en_10fdx = *(uint8_t *)pr_val;
3146 Adapter->param_adv_10fdx = *(uint8_t *)pr_val;
3147 goto reset;
3148 case MAC_PROP_EN_10HDX_CAP:
3149 if (hw->phy.media_type != e1000_media_type_copper) {
3150 err = ENOTSUP;
3151 break;
3152 }
3153 Adapter->param_en_10hdx = *(uint8_t *)pr_val;
3154 Adapter->param_adv_10hdx = *(uint8_t *)pr_val;
3155 goto reset;
3156 case MAC_PROP_AUTONEG:
3157 if (hw->phy.media_type != e1000_media_type_copper) {
3158 err = ENOTSUP;
3159 break;
3160 }
3161 Adapter->param_adv_autoneg = *(uint8_t *)pr_val;
3162 goto reset;
3163 case MAC_PROP_FLOWCTRL:
3164 fc->send_xon = B_TRUE;
3165 bcopy(pr_val, &flowctrl, sizeof (flowctrl));
3166
3167 switch (flowctrl) {
3168 default:
3169 err = EINVAL;
3170 break;
3171 case LINK_FLOWCTRL_NONE:
3172 fc->requested_mode = e1000_fc_none;
3173 break;
3174 case LINK_FLOWCTRL_RX:
3175 fc->requested_mode = e1000_fc_rx_pause;
3176 break;
3177 case LINK_FLOWCTRL_TX:
3178 fc->requested_mode = e1000_fc_tx_pause;
3179 break;
3180 case LINK_FLOWCTRL_BI:
3181 fc->requested_mode = e1000_fc_full;
3182 break;
3183 }
3184 reset:
3185 if (err == 0) {
3186 /* check PCH limits & reset the link */
3187 e1000g_pch_limits(Adapter);
3188 if (e1000g_reset_link(Adapter) != DDI_SUCCESS)
3189 err = EINVAL;
3190 }
3191 break;
3192 case MAC_PROP_ADV_1000FDX_CAP:
3193 case MAC_PROP_ADV_1000HDX_CAP:
3194 case MAC_PROP_ADV_100FDX_CAP:
3195 case MAC_PROP_ADV_100HDX_CAP:
3196 case MAC_PROP_ADV_10FDX_CAP:
3197 case MAC_PROP_ADV_10HDX_CAP:
3198 case MAC_PROP_EN_1000HDX_CAP:
3199 case MAC_PROP_STATUS:
3200 case MAC_PROP_SPEED:
3201 case MAC_PROP_DUPLEX:
3202 err = ENOTSUP; /* read-only prop. Can't set this. */
3203 break;
3204 case MAC_PROP_MTU:
3205 /* adapter must be stopped for an MTU change */
3206 if (Adapter->e1000g_state & E1000G_STARTED) {
3207 err = EBUSY;
3208 break;
3209 }
3210
3211 cur_mtu = Adapter->default_mtu;
3212
3213 /* get new requested MTU */
3214 bcopy(pr_val, &new_mtu, sizeof (new_mtu));
3215 if (new_mtu == cur_mtu) {
3216 err = 0;
3217 break;
3218 }
3219
3220 if ((new_mtu < DEFAULT_MTU) ||
3221 (new_mtu > Adapter->max_mtu)) {
3222 err = EINVAL;
3223 break;
3224 }
3225
3226 /* inform MAC framework of new MTU */
3227 err = mac_maxsdu_update(Adapter->mh, new_mtu);
3228
3229 if (err == 0) {
3230 Adapter->default_mtu = new_mtu;
3231 Adapter->max_frame_size =
3232 e1000g_mtu2maxframe(new_mtu);
3233
3234 /*
3235 * check PCH limits & set buffer sizes to
3236 * match new MTU
3237 */
3238 e1000g_pch_limits(Adapter);
3239 e1000g_set_bufsize(Adapter);
3240
3241 /*
3242 * decrease the number of descriptors and free
3243 * packets for jumbo frames to reduce tx/rx
3244 * resource consumption
3245 */
3246 if (Adapter->max_frame_size >=
3247 (FRAME_SIZE_UPTO_4K)) {
3248 if (Adapter->tx_desc_num_flag == 0)
3249 Adapter->tx_desc_num =
3250 DEFAULT_JUMBO_NUM_TX_DESC;
3251
3252 if (Adapter->rx_desc_num_flag == 0)
3253 Adapter->rx_desc_num =
3254 DEFAULT_JUMBO_NUM_RX_DESC;
3255
3256 if (Adapter->tx_buf_num_flag == 0)
3257 Adapter->tx_freelist_num =
3258 DEFAULT_JUMBO_NUM_TX_BUF;
3259
3260 if (Adapter->rx_buf_num_flag == 0)
3261 Adapter->rx_freelist_limit =
3262 DEFAULT_JUMBO_NUM_RX_BUF;
3263 } else {
3264 if (Adapter->tx_desc_num_flag == 0)
3265 Adapter->tx_desc_num =
3266 DEFAULT_NUM_TX_DESCRIPTOR;
3267
3268 if (Adapter->rx_desc_num_flag == 0)
3269 Adapter->rx_desc_num =
3270 DEFAULT_NUM_RX_DESCRIPTOR;
3271
3272 if (Adapter->tx_buf_num_flag == 0)
3273 Adapter->tx_freelist_num =
3274 DEFAULT_NUM_TX_FREELIST;
3275
3276 if (Adapter->rx_buf_num_flag == 0)
3277 Adapter->rx_freelist_limit =
3278 DEFAULT_NUM_RX_FREELIST;
3279 }
3280 }
3281 break;
3282 case MAC_PROP_PRIVATE:
3283 err = e1000g_set_priv_prop(Adapter, pr_name,
3284 pr_valsize, pr_val);
3285 break;
3286 default:
3287 err = ENOTSUP;
3288 break;
3289 }
3290 rw_exit(&Adapter->chip_lock);
3291 return (err);
3292 }
3293
3294 static int
e1000g_m_getprop(void * arg,const char * pr_name,mac_prop_id_t pr_num,uint_t pr_valsize,void * pr_val)3295 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num,
3296 uint_t pr_valsize, void *pr_val)
3297 {
3298 struct e1000g *Adapter = arg;
3299 struct e1000_fc_info *fc = &Adapter->shared.fc;
3300 int err = 0;
3301 link_flowctrl_t flowctrl;
3302 uint64_t tmp = 0;
3303
3304 switch (pr_num) {
3305 case MAC_PROP_DUPLEX:
3306 ASSERT(pr_valsize >= sizeof (link_duplex_t));
3307 bcopy(&Adapter->link_duplex, pr_val,
3308 sizeof (link_duplex_t));
3309 break;
3310 case MAC_PROP_SPEED:
3311 ASSERT(pr_valsize >= sizeof (uint64_t));
3312 tmp = Adapter->link_speed * 1000000ull;
3313 bcopy(&tmp, pr_val, sizeof (tmp));
3314 break;
3315 case MAC_PROP_AUTONEG:
3316 *(uint8_t *)pr_val = Adapter->param_adv_autoneg;
3317 break;
3318 case MAC_PROP_FLOWCTRL:
3319 ASSERT(pr_valsize >= sizeof (link_flowctrl_t));
3320 switch (fc->current_mode) {
3321 case e1000_fc_none:
3322 flowctrl = LINK_FLOWCTRL_NONE;
3323 break;
3324 case e1000_fc_rx_pause:
3325 flowctrl = LINK_FLOWCTRL_RX;
3326 break;
3327 case e1000_fc_tx_pause:
3328 flowctrl = LINK_FLOWCTRL_TX;
3329 break;
3330 case e1000_fc_full:
3331 flowctrl = LINK_FLOWCTRL_BI;
3332 break;
3333 }
3334 bcopy(&flowctrl, pr_val, sizeof (flowctrl));
3335 break;
3336 case MAC_PROP_ADV_1000FDX_CAP:
3337 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx;
3338 break;
3339 case MAC_PROP_EN_1000FDX_CAP:
3340 *(uint8_t *)pr_val = Adapter->param_en_1000fdx;
3341 break;
3342 case MAC_PROP_ADV_1000HDX_CAP:
3343 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx;
3344 break;
3345 case MAC_PROP_EN_1000HDX_CAP:
3346 *(uint8_t *)pr_val = Adapter->param_en_1000hdx;
3347 break;
3348 case MAC_PROP_ADV_100FDX_CAP:
3349 *(uint8_t *)pr_val = Adapter->param_adv_100fdx;
3350 break;
3351 case MAC_PROP_EN_100FDX_CAP:
3352 *(uint8_t *)pr_val = Adapter->param_en_100fdx;
3353 break;
3354 case MAC_PROP_ADV_100HDX_CAP:
3355 *(uint8_t *)pr_val = Adapter->param_adv_100hdx;
3356 break;
3357 case MAC_PROP_EN_100HDX_CAP:
3358 *(uint8_t *)pr_val = Adapter->param_en_100hdx;
3359 break;
3360 case MAC_PROP_ADV_10FDX_CAP:
3361 *(uint8_t *)pr_val = Adapter->param_adv_10fdx;
3362 break;
3363 case MAC_PROP_EN_10FDX_CAP:
3364 *(uint8_t *)pr_val = Adapter->param_en_10fdx;
3365 break;
3366 case MAC_PROP_ADV_10HDX_CAP:
3367 *(uint8_t *)pr_val = Adapter->param_adv_10hdx;
3368 break;
3369 case MAC_PROP_EN_10HDX_CAP:
3370 *(uint8_t *)pr_val = Adapter->param_en_10hdx;
3371 break;
3372 case MAC_PROP_ADV_100T4_CAP:
3373 case MAC_PROP_EN_100T4_CAP:
3374 *(uint8_t *)pr_val = Adapter->param_adv_100t4;
3375 break;
3376 case MAC_PROP_PRIVATE:
3377 err = e1000g_get_priv_prop(Adapter, pr_name,
3378 pr_valsize, pr_val);
3379 break;
3380 default:
3381 err = ENOTSUP;
3382 break;
3383 }
3384
3385 return (err);
3386 }
3387
3388 static void
e1000g_m_propinfo(void * arg,const char * pr_name,mac_prop_id_t pr_num,mac_prop_info_handle_t prh)3389 e1000g_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num,
3390 mac_prop_info_handle_t prh)
3391 {
3392 struct e1000g *Adapter = arg;
3393 struct e1000_hw *hw = &Adapter->shared;
3394
3395 switch (pr_num) {
3396 case MAC_PROP_DUPLEX:
3397 case MAC_PROP_SPEED:
3398 case MAC_PROP_ADV_1000FDX_CAP:
3399 case MAC_PROP_ADV_1000HDX_CAP:
3400 case MAC_PROP_ADV_100FDX_CAP:
3401 case MAC_PROP_ADV_100HDX_CAP:
3402 case MAC_PROP_ADV_10FDX_CAP:
3403 case MAC_PROP_ADV_10HDX_CAP:
3404 case MAC_PROP_ADV_100T4_CAP:
3405 case MAC_PROP_EN_100T4_CAP:
3406 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
3407 break;
3408
3409 case MAC_PROP_EN_1000FDX_CAP:
3410 if (hw->phy.media_type != e1000_media_type_copper) {
3411 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
3412 } else {
3413 mac_prop_info_set_default_uint8(prh,
3414 ((Adapter->phy_ext_status &
3415 IEEE_ESR_1000T_FD_CAPS) ||
3416 (Adapter->phy_ext_status &
3417 IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0);
3418 }
3419 break;
3420
3421 case MAC_PROP_EN_100FDX_CAP:
3422 if (hw->phy.media_type != e1000_media_type_copper) {
3423 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
3424 } else {
3425 mac_prop_info_set_default_uint8(prh,
3426 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
3427 (Adapter->phy_status & MII_SR_100T2_FD_CAPS))
3428 ? 1 : 0);
3429 }
3430 break;
3431
3432 case MAC_PROP_EN_100HDX_CAP:
3433 if (hw->phy.media_type != e1000_media_type_copper) {
3434 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
3435 } else {
3436 mac_prop_info_set_default_uint8(prh,
3437 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) ||
3438 (Adapter->phy_status & MII_SR_100T2_HD_CAPS))
3439 ? 1 : 0);
3440 }
3441 break;
3442
3443 case MAC_PROP_EN_10FDX_CAP:
3444 if (hw->phy.media_type != e1000_media_type_copper) {
3445 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
3446 } else {
3447 mac_prop_info_set_default_uint8(prh,
3448 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0);
3449 }
3450 break;
3451
3452 case MAC_PROP_EN_10HDX_CAP:
3453 if (hw->phy.media_type != e1000_media_type_copper) {
3454 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
3455 } else {
3456 mac_prop_info_set_default_uint8(prh,
3457 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0);
3458 }
3459 break;
3460
3461 case MAC_PROP_EN_1000HDX_CAP:
3462 if (hw->phy.media_type != e1000_media_type_copper)
3463 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
3464 break;
3465
3466 case MAC_PROP_AUTONEG:
3467 if (hw->phy.media_type != e1000_media_type_copper) {
3468 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
3469 } else {
3470 mac_prop_info_set_default_uint8(prh,
3471 (Adapter->phy_status & MII_SR_AUTONEG_CAPS)
3472 ? 1 : 0);
3473 }
3474 break;
3475
3476 case MAC_PROP_FLOWCTRL:
3477 mac_prop_info_set_default_link_flowctrl(prh, LINK_FLOWCTRL_BI);
3478 break;
3479
3480 case MAC_PROP_MTU: {
3481 struct e1000_mac_info *mac = &Adapter->shared.mac;
3482 struct e1000_phy_info *phy = &Adapter->shared.phy;
3483 uint32_t max;
3484
3485 /* some MAC types do not support jumbo frames */
3486 if ((mac->type == e1000_ich8lan) ||
3487 ((mac->type == e1000_ich9lan) && (phy->type ==
3488 e1000_phy_ife))) {
3489 max = DEFAULT_MTU;
3490 } else {
3491 max = Adapter->max_mtu;
3492 }
3493
3494 mac_prop_info_set_range_uint32(prh, DEFAULT_MTU, max);
3495 break;
3496 }
3497 case MAC_PROP_PRIVATE: {
3498 char valstr[64];
3499 int value;
3500
3501 if (strcmp(pr_name, "_adv_pause_cap") == 0 ||
3502 strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
3503 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
3504 return;
3505 } else if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) {
3506 value = DEFAULT_TX_BCOPY_THRESHOLD;
3507 } else if (strcmp(pr_name, "_tx_interrupt_enable") == 0) {
3508 value = DEFAULT_TX_INTR_ENABLE;
3509 } else if (strcmp(pr_name, "_tx_intr_delay") == 0) {
3510 value = DEFAULT_TX_INTR_DELAY;
3511 } else if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) {
3512 value = DEFAULT_TX_INTR_ABS_DELAY;
3513 } else if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) {
3514 value = DEFAULT_RX_BCOPY_THRESHOLD;
3515 } else if (strcmp(pr_name, "_max_num_rcv_packets") == 0) {
3516 value = DEFAULT_RX_LIMIT_ON_INTR;
3517 } else if (strcmp(pr_name, "_rx_intr_delay") == 0) {
3518 value = DEFAULT_RX_INTR_DELAY;
3519 } else if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) {
3520 value = DEFAULT_RX_INTR_ABS_DELAY;
3521 } else if (strcmp(pr_name, "_intr_throttling_rate") == 0) {
3522 value = DEFAULT_INTR_THROTTLING;
3523 } else if (strcmp(pr_name, "_intr_adaptive") == 0) {
3524 value = 1;
3525 } else {
3526 return;
3527 }
3528
3529 (void) snprintf(valstr, sizeof (valstr), "%d", value);
3530 mac_prop_info_set_default_str(prh, valstr);
3531 break;
3532 }
3533 }
3534 }
3535
3536 /* ARGSUSED2 */
3537 static int
e1000g_set_priv_prop(struct e1000g * Adapter,const char * pr_name,uint_t pr_valsize,const void * pr_val)3538 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name,
3539 uint_t pr_valsize, const void *pr_val)
3540 {
3541 int err = 0;
3542 long result;
3543 struct e1000_hw *hw = &Adapter->shared;
3544
3545 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) {
3546 if (pr_val == NULL) {
3547 err = EINVAL;
3548 return (err);
3549 }
3550 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3551 if (result < MIN_TX_BCOPY_THRESHOLD ||
3552 result > MAX_TX_BCOPY_THRESHOLD)
3553 err = EINVAL;
3554 else {
3555 Adapter->tx_bcopy_thresh = (uint32_t)result;
3556 }
3557 return (err);
3558 }
3559 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) {
3560 if (pr_val == NULL) {
3561 err = EINVAL;
3562 return (err);
3563 }
3564 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3565 if (result < 0 || result > 1)
3566 err = EINVAL;
3567 else {
3568 Adapter->tx_intr_enable = (result == 1) ?
3569 B_TRUE: B_FALSE;
3570 if (Adapter->tx_intr_enable)
3571 e1000g_mask_tx_interrupt(Adapter);
3572 else
3573 e1000g_clear_tx_interrupt(Adapter);
3574 if (e1000g_check_acc_handle(
3575 Adapter->osdep.reg_handle) != DDI_FM_OK) {
3576 ddi_fm_service_impact(Adapter->dip,
3577 DDI_SERVICE_DEGRADED);
3578 err = EIO;
3579 }
3580 }
3581 return (err);
3582 }
3583 if (strcmp(pr_name, "_tx_intr_delay") == 0) {
3584 if (pr_val == NULL) {
3585 err = EINVAL;
3586 return (err);
3587 }
3588 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3589 if (result < MIN_TX_INTR_DELAY ||
3590 result > MAX_TX_INTR_DELAY)
3591 err = EINVAL;
3592 else {
3593 Adapter->tx_intr_delay = (uint32_t)result;
3594 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay);
3595 if (e1000g_check_acc_handle(
3596 Adapter->osdep.reg_handle) != DDI_FM_OK) {
3597 ddi_fm_service_impact(Adapter->dip,
3598 DDI_SERVICE_DEGRADED);
3599 err = EIO;
3600 }
3601 }
3602 return (err);
3603 }
3604 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) {
3605 if (pr_val == NULL) {
3606 err = EINVAL;
3607 return (err);
3608 }
3609 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3610 if (result < MIN_TX_INTR_ABS_DELAY ||
3611 result > MAX_TX_INTR_ABS_DELAY)
3612 err = EINVAL;
3613 else {
3614 Adapter->tx_intr_abs_delay = (uint32_t)result;
3615 E1000_WRITE_REG(hw, E1000_TADV,
3616 Adapter->tx_intr_abs_delay);
3617 if (e1000g_check_acc_handle(
3618 Adapter->osdep.reg_handle) != DDI_FM_OK) {
3619 ddi_fm_service_impact(Adapter->dip,
3620 DDI_SERVICE_DEGRADED);
3621 err = EIO;
3622 }
3623 }
3624 return (err);
3625 }
3626 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) {
3627 if (pr_val == NULL) {
3628 err = EINVAL;
3629 return (err);
3630 }
3631 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3632 if (result < MIN_RX_BCOPY_THRESHOLD ||
3633 result > MAX_RX_BCOPY_THRESHOLD)
3634 err = EINVAL;
3635 else
3636 Adapter->rx_bcopy_thresh = (uint32_t)result;
3637 return (err);
3638 }
3639 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) {
3640 if (pr_val == NULL) {
3641 err = EINVAL;
3642 return (err);
3643 }
3644 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3645 if (result < MIN_RX_LIMIT_ON_INTR ||
3646 result > MAX_RX_LIMIT_ON_INTR)
3647 err = EINVAL;
3648 else
3649 Adapter->rx_limit_onintr = (uint32_t)result;
3650 return (err);
3651 }
3652 if (strcmp(pr_name, "_rx_intr_delay") == 0) {
3653 if (pr_val == NULL) {
3654 err = EINVAL;
3655 return (err);
3656 }
3657 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3658 if (result < MIN_RX_INTR_DELAY ||
3659 result > MAX_RX_INTR_DELAY)
3660 err = EINVAL;
3661 else {
3662 Adapter->rx_intr_delay = (uint32_t)result;
3663 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay);
3664 if (e1000g_check_acc_handle(
3665 Adapter->osdep.reg_handle) != DDI_FM_OK) {
3666 ddi_fm_service_impact(Adapter->dip,
3667 DDI_SERVICE_DEGRADED);
3668 err = EIO;
3669 }
3670 }
3671 return (err);
3672 }
3673 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) {
3674 if (pr_val == NULL) {
3675 err = EINVAL;
3676 return (err);
3677 }
3678 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3679 if (result < MIN_RX_INTR_ABS_DELAY ||
3680 result > MAX_RX_INTR_ABS_DELAY)
3681 err = EINVAL;
3682 else {
3683 Adapter->rx_intr_abs_delay = (uint32_t)result;
3684 E1000_WRITE_REG(hw, E1000_RADV,
3685 Adapter->rx_intr_abs_delay);
3686 if (e1000g_check_acc_handle(
3687 Adapter->osdep.reg_handle) != DDI_FM_OK) {
3688 ddi_fm_service_impact(Adapter->dip,
3689 DDI_SERVICE_DEGRADED);
3690 err = EIO;
3691 }
3692 }
3693 return (err);
3694 }
3695 if (strcmp(pr_name, "_intr_throttling_rate") == 0) {
3696 if (pr_val == NULL) {
3697 err = EINVAL;
3698 return (err);
3699 }
3700 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3701 if (result < MIN_INTR_THROTTLING ||
3702 result > MAX_INTR_THROTTLING)
3703 err = EINVAL;
3704 else {
3705 if (hw->mac.type >= e1000_82540) {
3706 Adapter->intr_throttling_rate =
3707 (uint32_t)result;
3708 E1000_WRITE_REG(hw, E1000_ITR,
3709 Adapter->intr_throttling_rate);
3710 if (e1000g_check_acc_handle(
3711 Adapter->osdep.reg_handle) != DDI_FM_OK) {
3712 ddi_fm_service_impact(Adapter->dip,
3713 DDI_SERVICE_DEGRADED);
3714 err = EIO;
3715 }
3716 } else
3717 err = EINVAL;
3718 }
3719 return (err);
3720 }
3721 if (strcmp(pr_name, "_intr_adaptive") == 0) {
3722 if (pr_val == NULL) {
3723 err = EINVAL;
3724 return (err);
3725 }
3726 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3727 if (result < 0 || result > 1)
3728 err = EINVAL;
3729 else {
3730 if (hw->mac.type >= e1000_82540) {
3731 Adapter->intr_adaptive = (result == 1) ?
3732 B_TRUE : B_FALSE;
3733 } else {
3734 err = EINVAL;
3735 }
3736 }
3737 return (err);
3738 }
3739 return (ENOTSUP);
3740 }
3741
3742 static int
e1000g_get_priv_prop(struct e1000g * Adapter,const char * pr_name,uint_t pr_valsize,void * pr_val)3743 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name,
3744 uint_t pr_valsize, void *pr_val)
3745 {
3746 int err = ENOTSUP;
3747 int value;
3748
3749 if (strcmp(pr_name, "_adv_pause_cap") == 0) {
3750 value = Adapter->param_adv_pause;
3751 err = 0;
3752 goto done;
3753 }
3754 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
3755 value = Adapter->param_adv_asym_pause;
3756 err = 0;
3757 goto done;
3758 }
3759 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) {
3760 value = Adapter->tx_bcopy_thresh;
3761 err = 0;
3762 goto done;
3763 }
3764 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) {
3765 value = Adapter->tx_intr_enable;
3766 err = 0;
3767 goto done;
3768 }
3769 if (strcmp(pr_name, "_tx_intr_delay") == 0) {
3770 value = Adapter->tx_intr_delay;
3771 err = 0;
3772 goto done;
3773 }
3774 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) {
3775 value = Adapter->tx_intr_abs_delay;
3776 err = 0;
3777 goto done;
3778 }
3779 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) {
3780 value = Adapter->rx_bcopy_thresh;
3781 err = 0;
3782 goto done;
3783 }
3784 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) {
3785 value = Adapter->rx_limit_onintr;
3786 err = 0;
3787 goto done;
3788 }
3789 if (strcmp(pr_name, "_rx_intr_delay") == 0) {
3790 value = Adapter->rx_intr_delay;
3791 err = 0;
3792 goto done;
3793 }
3794 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) {
3795 value = Adapter->rx_intr_abs_delay;
3796 err = 0;
3797 goto done;
3798 }
3799 if (strcmp(pr_name, "_intr_throttling_rate") == 0) {
3800 value = Adapter->intr_throttling_rate;
3801 err = 0;
3802 goto done;
3803 }
3804 if (strcmp(pr_name, "_intr_adaptive") == 0) {
3805 value = Adapter->intr_adaptive;
3806 err = 0;
3807 goto done;
3808 }
3809 done:
3810 if (err == 0) {
3811 (void) snprintf(pr_val, pr_valsize, "%d", value);
3812 }
3813 return (err);
3814 }
3815
3816 /*
3817 * e1000g_get_conf - get configurations set in e1000g.conf
3818 * This routine gets user-configured values out of the configuration
3819 * file e1000g.conf.
3820 *
3821 * For each configurable value, there is a minimum, a maximum, and a
3822 * default.
3823 * If user does not configure a value, use the default.
3824 * If user configures below the minimum, use the minumum.
3825 * If user configures above the maximum, use the maxumum.
3826 */
3827 static void
e1000g_get_conf(struct e1000g * Adapter)3828 e1000g_get_conf(struct e1000g *Adapter)
3829 {
3830 struct e1000_hw *hw = &Adapter->shared;
3831 boolean_t tbi_compatibility = B_FALSE;
3832 boolean_t is_jumbo = B_FALSE;
3833 int propval;
3834 /*
3835 * decrease the number of descriptors and free packets
3836 * for jumbo frames to reduce tx/rx resource consumption
3837 */
3838 if (Adapter->max_frame_size >= FRAME_SIZE_UPTO_4K) {
3839 is_jumbo = B_TRUE;
3840 }
3841
3842 /*
3843 * get each configurable property from e1000g.conf
3844 */
3845
3846 /*
3847 * NumTxDescriptors
3848 */
3849 Adapter->tx_desc_num_flag =
3850 e1000g_get_prop(Adapter, "NumTxDescriptors",
3851 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR,
3852 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC
3853 : DEFAULT_NUM_TX_DESCRIPTOR, &propval);
3854 Adapter->tx_desc_num = propval;
3855
3856 /*
3857 * NumRxDescriptors
3858 */
3859 Adapter->rx_desc_num_flag =
3860 e1000g_get_prop(Adapter, "NumRxDescriptors",
3861 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR,
3862 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC
3863 : DEFAULT_NUM_RX_DESCRIPTOR, &propval);
3864 Adapter->rx_desc_num = propval;
3865
3866 /*
3867 * NumRxFreeList
3868 */
3869 Adapter->rx_buf_num_flag =
3870 e1000g_get_prop(Adapter, "NumRxFreeList",
3871 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST,
3872 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF
3873 : DEFAULT_NUM_RX_FREELIST, &propval);
3874 Adapter->rx_freelist_limit = propval;
3875
3876 /*
3877 * NumTxPacketList
3878 */
3879 Adapter->tx_buf_num_flag =
3880 e1000g_get_prop(Adapter, "NumTxPacketList",
3881 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST,
3882 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF
3883 : DEFAULT_NUM_TX_FREELIST, &propval);
3884 Adapter->tx_freelist_num = propval;
3885
3886 /*
3887 * FlowControl
3888 */
3889 hw->fc.send_xon = B_TRUE;
3890 (void) e1000g_get_prop(Adapter, "FlowControl",
3891 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval);
3892 hw->fc.requested_mode = propval;
3893 /* 4 is the setting that says "let the eeprom decide" */
3894 if (hw->fc.requested_mode == 4)
3895 hw->fc.requested_mode = e1000_fc_default;
3896
3897 /*
3898 * Max Num Receive Packets on Interrupt
3899 */
3900 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets",
3901 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR,
3902 DEFAULT_RX_LIMIT_ON_INTR, &propval);
3903 Adapter->rx_limit_onintr = propval;
3904
3905 /*
3906 * PHY master slave setting
3907 */
3908 (void) e1000g_get_prop(Adapter, "SetMasterSlave",
3909 e1000_ms_hw_default, e1000_ms_auto,
3910 e1000_ms_hw_default, &propval);
3911 hw->phy.ms_type = propval;
3912
3913 /*
3914 * Parameter which controls TBI mode workaround, which is only
3915 * needed on certain switches such as Cisco 6500/Foundry
3916 */
3917 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable",
3918 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval);
3919 tbi_compatibility = (propval == 1);
3920 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility);
3921
3922 /*
3923 * MSI Enable
3924 */
3925 (void) e1000g_get_prop(Adapter, "MSIEnable",
3926 0, 1, DEFAULT_MSI_ENABLE, &propval);
3927 Adapter->msi_enable = (propval == 1);
3928
3929 /*
3930 * Interrupt Throttling Rate
3931 */
3932 (void) e1000g_get_prop(Adapter, "intr_throttling_rate",
3933 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING,
3934 DEFAULT_INTR_THROTTLING, &propval);
3935 Adapter->intr_throttling_rate = propval;
3936
3937 /*
3938 * Adaptive Interrupt Blanking Enable/Disable
3939 * It is enabled by default
3940 */
3941 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1,
3942 &propval);
3943 Adapter->intr_adaptive = (propval == 1);
3944
3945 /*
3946 * Hardware checksum enable/disable parameter
3947 */
3948 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable",
3949 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval);
3950 Adapter->tx_hcksum_enable = (propval == 1);
3951 /*
3952 * Checksum on/off selection via global parameters.
3953 *
3954 * If the chip is flagged as not capable of (correctly)
3955 * handling checksumming, we don't enable it on either
3956 * Rx or Tx side. Otherwise, we take this chip's settings
3957 * from the patchable global defaults.
3958 *
3959 * We advertise our capabilities only if TX offload is
3960 * enabled. On receive, the stack will accept checksummed
3961 * packets anyway, even if we haven't said we can deliver
3962 * them.
3963 */
3964 switch (hw->mac.type) {
3965 case e1000_82540:
3966 case e1000_82544:
3967 case e1000_82545:
3968 case e1000_82545_rev_3:
3969 case e1000_82546:
3970 case e1000_82546_rev_3:
3971 case e1000_82571:
3972 case e1000_82572:
3973 case e1000_82573:
3974 case e1000_80003es2lan:
3975 break;
3976 /*
3977 * For the following Intel PRO/1000 chipsets, we have not
3978 * tested the hardware checksum offload capability, so we
3979 * disable the capability for them.
3980 * e1000_82542,
3981 * e1000_82543,
3982 * e1000_82541,
3983 * e1000_82541_rev_2,
3984 * e1000_82547,
3985 * e1000_82547_rev_2,
3986 */
3987 default:
3988 Adapter->tx_hcksum_enable = B_FALSE;
3989 }
3990
3991 /*
3992 * Large Send Offloading(LSO) Enable/Disable
3993 * If the tx hardware checksum is not enabled, LSO should be
3994 * disabled.
3995 */
3996 (void) e1000g_get_prop(Adapter, "lso_enable",
3997 0, 1, DEFAULT_LSO_ENABLE, &propval);
3998 Adapter->lso_enable = (propval == 1);
3999
4000 switch (hw->mac.type) {
4001 case e1000_82546:
4002 case e1000_82546_rev_3:
4003 if (Adapter->lso_enable)
4004 Adapter->lso_premature_issue = B_TRUE;
4005 /* FALLTHRU */
4006 case e1000_82571:
4007 case e1000_82572:
4008 case e1000_82573:
4009 case e1000_80003es2lan:
4010 break;
4011 default:
4012 Adapter->lso_enable = B_FALSE;
4013 }
4014
4015 if (!Adapter->tx_hcksum_enable) {
4016 Adapter->lso_premature_issue = B_FALSE;
4017 Adapter->lso_enable = B_FALSE;
4018 }
4019
4020 /*
4021 * If mem_workaround_82546 is enabled, the rx buffer allocated by
4022 * e1000_82545, e1000_82546 and e1000_82546_rev_3
4023 * will not cross 64k boundary.
4024 */
4025 (void) e1000g_get_prop(Adapter, "mem_workaround_82546",
4026 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval);
4027 Adapter->mem_workaround_82546 = (propval == 1);
4028
4029 /*
4030 * Max number of multicast addresses
4031 */
4032 (void) e1000g_get_prop(Adapter, "mcast_max_num",
4033 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32,
4034 &propval);
4035 Adapter->mcast_max_num = propval;
4036 }
4037
4038 /*
4039 * e1000g_get_prop - routine to read properties
4040 *
4041 * Get a user-configure property value out of the configuration
4042 * file e1000g.conf.
4043 *
4044 * Caller provides name of the property, a default value, a minimum
4045 * value, a maximum value and a pointer to the returned property
4046 * value.
4047 *
4048 * Return B_TRUE if the configured value of the property is not a default
4049 * value, otherwise return B_FALSE.
4050 */
4051 static boolean_t
e1000g_get_prop(struct e1000g * Adapter,char * propname,int minval,int maxval,int defval,int * propvalue)4052 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */
4053 char *propname, /* name of the property */
4054 int minval, /* minimum acceptable value */
4055 int maxval, /* maximim acceptable value */
4056 int defval, /* default value */
4057 int *propvalue) /* property value return to caller */
4058 {
4059 int propval; /* value returned for requested property */
4060 int *props; /* point to array of properties returned */
4061 uint_t nprops; /* number of property value returned */
4062 boolean_t ret = B_TRUE;
4063
4064 /*
4065 * get the array of properties from the config file
4066 */
4067 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip,
4068 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) {
4069 /* got some properties, test if we got enough */
4070 if (Adapter->instance < nprops) {
4071 propval = props[Adapter->instance];
4072 } else {
4073 /* not enough properties configured */
4074 propval = defval;
4075 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL,
4076 "Not Enough %s values found in e1000g.conf"
4077 " - set to %d\n",
4078 propname, propval);
4079 ret = B_FALSE;
4080 }
4081
4082 /* free memory allocated for properties */
4083 ddi_prop_free(props);
4084
4085 } else {
4086 propval = defval;
4087 ret = B_FALSE;
4088 }
4089
4090 /*
4091 * enforce limits
4092 */
4093 if (propval > maxval) {
4094 propval = maxval;
4095 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL,
4096 "Too High %s value in e1000g.conf - set to %d\n",
4097 propname, propval);
4098 }
4099
4100 if (propval < minval) {
4101 propval = minval;
4102 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL,
4103 "Too Low %s value in e1000g.conf - set to %d\n",
4104 propname, propval);
4105 }
4106
4107 *propvalue = propval;
4108 return (ret);
4109 }
4110
4111 static boolean_t
e1000g_link_check(struct e1000g * Adapter)4112 e1000g_link_check(struct e1000g *Adapter)
4113 {
4114 uint16_t speed, duplex, phydata;
4115 boolean_t link_changed = B_FALSE;
4116 struct e1000_hw *hw;
4117 uint32_t reg_tarc;
4118
4119 hw = &Adapter->shared;
4120
4121 if (e1000g_link_up(Adapter)) {
4122 /*
4123 * The Link is up, check whether it was marked as down earlier
4124 */
4125 if (Adapter->link_state != LINK_STATE_UP) {
4126 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex);
4127 Adapter->link_speed = speed;
4128 Adapter->link_duplex = duplex;
4129 Adapter->link_state = LINK_STATE_UP;
4130 link_changed = B_TRUE;
4131
4132 if (Adapter->link_speed == SPEED_1000)
4133 Adapter->stall_threshold = TX_STALL_TIME_2S;
4134 else
4135 Adapter->stall_threshold = TX_STALL_TIME_8S;
4136
4137 Adapter->tx_link_down_timeout = 0;
4138
4139 if ((hw->mac.type == e1000_82571) ||
4140 (hw->mac.type == e1000_82572)) {
4141 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0));
4142 if (speed == SPEED_1000)
4143 reg_tarc |= (1 << 21);
4144 else
4145 reg_tarc &= ~(1 << 21);
4146 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc);
4147 }
4148 }
4149 Adapter->smartspeed = 0;
4150 } else {
4151 if (Adapter->link_state != LINK_STATE_DOWN) {
4152 Adapter->link_speed = 0;
4153 Adapter->link_duplex = 0;
4154 Adapter->link_state = LINK_STATE_DOWN;
4155 link_changed = B_TRUE;
4156
4157 /*
4158 * SmartSpeed workaround for Tabor/TanaX, When the
4159 * driver loses link disable auto master/slave
4160 * resolution.
4161 */
4162 if (hw->phy.type == e1000_phy_igp) {
4163 (void) e1000_read_phy_reg(hw,
4164 PHY_1000T_CTRL, &phydata);
4165 phydata |= CR_1000T_MS_ENABLE;
4166 (void) e1000_write_phy_reg(hw,
4167 PHY_1000T_CTRL, phydata);
4168 }
4169 } else {
4170 e1000g_smartspeed(Adapter);
4171 }
4172
4173 if (Adapter->e1000g_state & E1000G_STARTED) {
4174 if (Adapter->tx_link_down_timeout <
4175 MAX_TX_LINK_DOWN_TIMEOUT) {
4176 Adapter->tx_link_down_timeout++;
4177 } else if (Adapter->tx_link_down_timeout ==
4178 MAX_TX_LINK_DOWN_TIMEOUT) {
4179 e1000g_tx_clean(Adapter);
4180 Adapter->tx_link_down_timeout++;
4181 }
4182 }
4183 }
4184
4185 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
4186 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
4187
4188 return (link_changed);
4189 }
4190
4191 /*
4192 * e1000g_reset_link - Using the link properties to setup the link
4193 */
4194 int
e1000g_reset_link(struct e1000g * Adapter)4195 e1000g_reset_link(struct e1000g *Adapter)
4196 {
4197 struct e1000_mac_info *mac;
4198 struct e1000_phy_info *phy;
4199 struct e1000_hw *hw;
4200 boolean_t invalid;
4201
4202 mac = &Adapter->shared.mac;
4203 phy = &Adapter->shared.phy;
4204 hw = &Adapter->shared;
4205 invalid = B_FALSE;
4206
4207 if (hw->phy.media_type != e1000_media_type_copper)
4208 goto out;
4209
4210 if (Adapter->param_adv_autoneg == 1) {
4211 mac->autoneg = B_TRUE;
4212 phy->autoneg_advertised = 0;
4213
4214 /*
4215 * 1000hdx is not supported for autonegotiation
4216 */
4217 if (Adapter->param_adv_1000fdx == 1)
4218 phy->autoneg_advertised |= ADVERTISE_1000_FULL;
4219
4220 if (Adapter->param_adv_100fdx == 1)
4221 phy->autoneg_advertised |= ADVERTISE_100_FULL;
4222
4223 if (Adapter->param_adv_100hdx == 1)
4224 phy->autoneg_advertised |= ADVERTISE_100_HALF;
4225
4226 if (Adapter->param_adv_10fdx == 1)
4227 phy->autoneg_advertised |= ADVERTISE_10_FULL;
4228
4229 if (Adapter->param_adv_10hdx == 1)
4230 phy->autoneg_advertised |= ADVERTISE_10_HALF;
4231
4232 if (phy->autoneg_advertised == 0)
4233 invalid = B_TRUE;
4234 } else {
4235 mac->autoneg = B_FALSE;
4236
4237 /*
4238 * For Intel copper cards, 1000fdx and 1000hdx are not
4239 * supported for forced link
4240 */
4241 if (Adapter->param_adv_100fdx == 1)
4242 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4243 else if (Adapter->param_adv_100hdx == 1)
4244 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4245 else if (Adapter->param_adv_10fdx == 1)
4246 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4247 else if (Adapter->param_adv_10hdx == 1)
4248 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4249 else
4250 invalid = B_TRUE;
4251
4252 }
4253
4254 if (invalid) {
4255 e1000g_log(Adapter, CE_WARN,
4256 "Invalid link settings. Setup link to "
4257 "support autonegotiation with all link capabilities.");
4258 mac->autoneg = B_TRUE;
4259 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
4260 }
4261
4262 out:
4263 return (e1000_setup_link(&Adapter->shared));
4264 }
4265
4266 static void
e1000g_timer_tx_resched(struct e1000g * Adapter)4267 e1000g_timer_tx_resched(struct e1000g *Adapter)
4268 {
4269 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring;
4270
4271 rw_enter(&Adapter->chip_lock, RW_READER);
4272
4273 if (tx_ring->resched_needed &&
4274 ((ddi_get_lbolt() - tx_ring->resched_timestamp) >
4275 drv_usectohz(1000000)) &&
4276 (Adapter->e1000g_state & E1000G_STARTED) &&
4277 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) {
4278 tx_ring->resched_needed = B_FALSE;
4279 mac_tx_update(Adapter->mh);
4280 E1000G_STAT(tx_ring->stat_reschedule);
4281 E1000G_STAT(tx_ring->stat_timer_reschedule);
4282 }
4283
4284 rw_exit(&Adapter->chip_lock);
4285 }
4286
4287 static void
e1000g_local_timer(void * ws)4288 e1000g_local_timer(void *ws)
4289 {
4290 struct e1000g *Adapter = (struct e1000g *)ws;
4291 struct e1000_hw *hw;
4292 e1000g_ether_addr_t ether_addr;
4293 boolean_t link_changed;
4294
4295 hw = &Adapter->shared;
4296
4297 if (Adapter->e1000g_state & E1000G_ERROR) {
4298 rw_enter(&Adapter->chip_lock, RW_WRITER);
4299 Adapter->e1000g_state &= ~E1000G_ERROR;
4300 rw_exit(&Adapter->chip_lock);
4301
4302 Adapter->reset_count++;
4303 if (e1000g_global_reset(Adapter)) {
4304 ddi_fm_service_impact(Adapter->dip,
4305 DDI_SERVICE_RESTORED);
4306 e1000g_timer_tx_resched(Adapter);
4307 } else
4308 ddi_fm_service_impact(Adapter->dip,
4309 DDI_SERVICE_LOST);
4310 return;
4311 }
4312
4313 if (e1000g_stall_check(Adapter)) {
4314 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL,
4315 "Tx stall detected. Activate automatic recovery.\n");
4316 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL);
4317 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
4318 Adapter->reset_count++;
4319 if (e1000g_reset_adapter(Adapter)) {
4320 ddi_fm_service_impact(Adapter->dip,
4321 DDI_SERVICE_RESTORED);
4322 e1000g_timer_tx_resched(Adapter);
4323 }
4324 return;
4325 }
4326
4327 link_changed = B_FALSE;
4328 rw_enter(&Adapter->chip_lock, RW_READER);
4329 if (Adapter->link_complete)
4330 link_changed = e1000g_link_check(Adapter);
4331 rw_exit(&Adapter->chip_lock);
4332
4333 if (link_changed) {
4334 if (!Adapter->reset_flag &&
4335 (Adapter->e1000g_state & E1000G_STARTED) &&
4336 !(Adapter->e1000g_state & E1000G_SUSPENDED))
4337 mac_link_update(Adapter->mh, Adapter->link_state);
4338 if (Adapter->link_state == LINK_STATE_UP)
4339 Adapter->reset_flag = B_FALSE;
4340 }
4341 /*
4342 * Workaround for esb2. Data stuck in fifo on a link
4343 * down event. Reset the adapter to recover it.
4344 */
4345 if (Adapter->esb2_workaround) {
4346 Adapter->esb2_workaround = B_FALSE;
4347 (void) e1000g_reset_adapter(Adapter);
4348 return;
4349 }
4350
4351 /*
4352 * With 82571 controllers, any locally administered address will
4353 * be overwritten when there is a reset on the other port.
4354 * Detect this circumstance and correct it.
4355 */
4356 if ((hw->mac.type == e1000_82571) &&
4357 (e1000_get_laa_state_82571(hw) == B_TRUE)) {
4358 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0);
4359 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1);
4360
4361 ether_addr.reg.low = ntohl(ether_addr.reg.low);
4362 ether_addr.reg.high = ntohl(ether_addr.reg.high);
4363
4364 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) ||
4365 (ether_addr.mac.addr[4] != hw->mac.addr[1]) ||
4366 (ether_addr.mac.addr[3] != hw->mac.addr[2]) ||
4367 (ether_addr.mac.addr[2] != hw->mac.addr[3]) ||
4368 (ether_addr.mac.addr[1] != hw->mac.addr[4]) ||
4369 (ether_addr.mac.addr[0] != hw->mac.addr[5])) {
4370 e1000_rar_set(hw, hw->mac.addr, 0);
4371 }
4372 }
4373
4374 /*
4375 * Long TTL workaround for 82541/82547
4376 */
4377 (void) e1000_igp_ttl_workaround_82547(hw);
4378
4379 /*
4380 * Check for Adaptive IFS settings If there are lots of collisions
4381 * change the value in steps...
4382 * These properties should only be set for 10/100
4383 */
4384 if ((hw->phy.media_type == e1000_media_type_copper) &&
4385 ((Adapter->link_speed == SPEED_100) ||
4386 (Adapter->link_speed == SPEED_10))) {
4387 e1000_update_adaptive(hw);
4388 }
4389 /*
4390 * Set Timer Interrupts
4391 */
4392 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0);
4393
4394 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
4395 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
4396 else
4397 e1000g_timer_tx_resched(Adapter);
4398
4399 restart_watchdog_timer(Adapter);
4400 }
4401
4402 /*
4403 * The function e1000g_link_timer() is called when the timer for link setup
4404 * is expired, which indicates the completion of the link setup. The link
4405 * state will not be updated until the link setup is completed. And the
4406 * link state will not be sent to the upper layer through mac_link_update()
4407 * in this function. It will be updated in the local timer routine or the
4408 * interrupt service routine after the interface is started (plumbed).
4409 */
4410 static void
e1000g_link_timer(void * arg)4411 e1000g_link_timer(void *arg)
4412 {
4413 struct e1000g *Adapter = (struct e1000g *)arg;
4414
4415 mutex_enter(&Adapter->link_lock);
4416 Adapter->link_complete = B_TRUE;
4417 Adapter->link_tid = 0;
4418 mutex_exit(&Adapter->link_lock);
4419 }
4420
4421 /*
4422 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf
4423 *
4424 * This function read the forced speed and duplex for 10/100 Mbps speeds
4425 * and also for 1000 Mbps speeds from the e1000g.conf file
4426 */
4427 static void
e1000g_force_speed_duplex(struct e1000g * Adapter)4428 e1000g_force_speed_duplex(struct e1000g *Adapter)
4429 {
4430 int forced;
4431 int propval;
4432 struct e1000_mac_info *mac = &Adapter->shared.mac;
4433 struct e1000_phy_info *phy = &Adapter->shared.phy;
4434
4435 /*
4436 * get value out of config file
4437 */
4438 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex",
4439 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced);
4440
4441 switch (forced) {
4442 case GDIAG_10_HALF:
4443 /*
4444 * Disable Auto Negotiation
4445 */
4446 mac->autoneg = B_FALSE;
4447 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4448 break;
4449 case GDIAG_10_FULL:
4450 /*
4451 * Disable Auto Negotiation
4452 */
4453 mac->autoneg = B_FALSE;
4454 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4455 break;
4456 case GDIAG_100_HALF:
4457 /*
4458 * Disable Auto Negotiation
4459 */
4460 mac->autoneg = B_FALSE;
4461 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4462 break;
4463 case GDIAG_100_FULL:
4464 /*
4465 * Disable Auto Negotiation
4466 */
4467 mac->autoneg = B_FALSE;
4468 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4469 break;
4470 case GDIAG_1000_FULL:
4471 /*
4472 * The gigabit spec requires autonegotiation. Therefore,
4473 * when the user wants to force the speed to 1000Mbps, we
4474 * enable AutoNeg, but only allow the harware to advertise
4475 * 1000Mbps. This is different from 10/100 operation, where
4476 * we are allowed to link without any negotiation.
4477 */
4478 mac->autoneg = B_TRUE;
4479 phy->autoneg_advertised = ADVERTISE_1000_FULL;
4480 break;
4481 default: /* obey the setting of AutoNegAdvertised */
4482 mac->autoneg = B_TRUE;
4483 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised",
4484 0, AUTONEG_ADVERTISE_SPEED_DEFAULT,
4485 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval);
4486 phy->autoneg_advertised = (uint16_t)propval;
4487 break;
4488 } /* switch */
4489 }
4490
4491 /*
4492 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf
4493 *
4494 * This function reads MaxFrameSize from e1000g.conf
4495 */
4496 static void
e1000g_get_max_frame_size(struct e1000g * Adapter)4497 e1000g_get_max_frame_size(struct e1000g *Adapter)
4498 {
4499 int max_frame;
4500
4501 /*
4502 * get value out of config file
4503 */
4504 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0,
4505 &max_frame);
4506
4507 switch (max_frame) {
4508 case 0:
4509 Adapter->default_mtu = ETHERMTU;
4510 break;
4511 case 1:
4512 Adapter->default_mtu = FRAME_SIZE_UPTO_4K -
4513 sizeof (struct ether_vlan_header) - ETHERFCSL;
4514 break;
4515 case 2:
4516 Adapter->default_mtu = FRAME_SIZE_UPTO_8K -
4517 sizeof (struct ether_vlan_header) - ETHERFCSL;
4518 break;
4519 case 3:
4520 Adapter->default_mtu = FRAME_SIZE_UPTO_16K -
4521 sizeof (struct ether_vlan_header) - ETHERFCSL;
4522 break;
4523 default:
4524 Adapter->default_mtu = ETHERMTU;
4525 break;
4526 } /* switch */
4527
4528 /*
4529 * If the user configed MTU is larger than the deivce's maximum MTU,
4530 * the MTU is set to the deivce's maximum value.
4531 */
4532 if (Adapter->default_mtu > Adapter->max_mtu)
4533 Adapter->default_mtu = Adapter->max_mtu;
4534
4535 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu);
4536 }
4537
4538 /*
4539 * e1000g_pch_limits - Apply limits of the PCH silicon type
4540 *
4541 * At any frame size larger than the ethernet default,
4542 * prevent linking at 10/100 speeds.
4543 */
4544 static void
e1000g_pch_limits(struct e1000g * Adapter)4545 e1000g_pch_limits(struct e1000g *Adapter)
4546 {
4547 struct e1000_hw *hw = &Adapter->shared;
4548
4549 /* only applies to PCH silicon type */
4550 if (hw->mac.type != e1000_pchlan)
4551 return;
4552
4553 /* only applies to frames larger than ethernet default */
4554 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) {
4555 hw->mac.autoneg = B_TRUE;
4556 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
4557
4558 Adapter->param_adv_autoneg = 1;
4559 Adapter->param_adv_1000fdx = 1;
4560
4561 Adapter->param_adv_100fdx = 0;
4562 Adapter->param_adv_100hdx = 0;
4563 Adapter->param_adv_10fdx = 0;
4564 Adapter->param_adv_10hdx = 0;
4565
4566 e1000g_param_sync(Adapter);
4567 }
4568 }
4569
4570 /*
4571 * e1000g_mtu2maxframe - convert given MTU to maximum frame size
4572 */
4573 static uint32_t
e1000g_mtu2maxframe(uint32_t mtu)4574 e1000g_mtu2maxframe(uint32_t mtu)
4575 {
4576 uint32_t maxframe;
4577
4578 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL;
4579
4580 return (maxframe);
4581 }
4582
4583 static void
arm_watchdog_timer(struct e1000g * Adapter)4584 arm_watchdog_timer(struct e1000g *Adapter)
4585 {
4586 Adapter->watchdog_tid =
4587 timeout(e1000g_local_timer,
4588 (void *)Adapter, 1 * drv_usectohz(1000000));
4589 }
4590 #pragma inline(arm_watchdog_timer)
4591
4592 static void
enable_watchdog_timer(struct e1000g * Adapter)4593 enable_watchdog_timer(struct e1000g *Adapter)
4594 {
4595 mutex_enter(&Adapter->watchdog_lock);
4596
4597 if (!Adapter->watchdog_timer_enabled) {
4598 Adapter->watchdog_timer_enabled = B_TRUE;
4599 Adapter->watchdog_timer_started = B_TRUE;
4600 arm_watchdog_timer(Adapter);
4601 }
4602
4603 mutex_exit(&Adapter->watchdog_lock);
4604 }
4605
4606 static void
disable_watchdog_timer(struct e1000g * Adapter)4607 disable_watchdog_timer(struct e1000g *Adapter)
4608 {
4609 timeout_id_t tid;
4610
4611 mutex_enter(&Adapter->watchdog_lock);
4612
4613 Adapter->watchdog_timer_enabled = B_FALSE;
4614 Adapter->watchdog_timer_started = B_FALSE;
4615 tid = Adapter->watchdog_tid;
4616 Adapter->watchdog_tid = 0;
4617
4618 mutex_exit(&Adapter->watchdog_lock);
4619
4620 if (tid != 0)
4621 (void) untimeout(tid);
4622 }
4623
4624 static void
start_watchdog_timer(struct e1000g * Adapter)4625 start_watchdog_timer(struct e1000g *Adapter)
4626 {
4627 mutex_enter(&Adapter->watchdog_lock);
4628
4629 if (Adapter->watchdog_timer_enabled) {
4630 if (!Adapter->watchdog_timer_started) {
4631 Adapter->watchdog_timer_started = B_TRUE;
4632 arm_watchdog_timer(Adapter);
4633 }
4634 }
4635
4636 mutex_exit(&Adapter->watchdog_lock);
4637 }
4638
4639 static void
restart_watchdog_timer(struct e1000g * Adapter)4640 restart_watchdog_timer(struct e1000g *Adapter)
4641 {
4642 mutex_enter(&Adapter->watchdog_lock);
4643
4644 if (Adapter->watchdog_timer_started)
4645 arm_watchdog_timer(Adapter);
4646
4647 mutex_exit(&Adapter->watchdog_lock);
4648 }
4649
4650 static void
stop_watchdog_timer(struct e1000g * Adapter)4651 stop_watchdog_timer(struct e1000g *Adapter)
4652 {
4653 timeout_id_t tid;
4654
4655 mutex_enter(&Adapter->watchdog_lock);
4656
4657 Adapter->watchdog_timer_started = B_FALSE;
4658 tid = Adapter->watchdog_tid;
4659 Adapter->watchdog_tid = 0;
4660
4661 mutex_exit(&Adapter->watchdog_lock);
4662
4663 if (tid != 0)
4664 (void) untimeout(tid);
4665 }
4666
4667 static void
stop_link_timer(struct e1000g * Adapter)4668 stop_link_timer(struct e1000g *Adapter)
4669 {
4670 timeout_id_t tid;
4671
4672 /* Disable the link timer */
4673 mutex_enter(&Adapter->link_lock);
4674
4675 tid = Adapter->link_tid;
4676 Adapter->link_tid = 0;
4677
4678 mutex_exit(&Adapter->link_lock);
4679
4680 if (tid != 0)
4681 (void) untimeout(tid);
4682 }
4683
4684 static void
stop_82547_timer(e1000g_tx_ring_t * tx_ring)4685 stop_82547_timer(e1000g_tx_ring_t *tx_ring)
4686 {
4687 timeout_id_t tid;
4688
4689 /* Disable the tx timer for 82547 chipset */
4690 mutex_enter(&tx_ring->tx_lock);
4691
4692 tx_ring->timer_enable_82547 = B_FALSE;
4693 tid = tx_ring->timer_id_82547;
4694 tx_ring->timer_id_82547 = 0;
4695
4696 mutex_exit(&tx_ring->tx_lock);
4697
4698 if (tid != 0)
4699 (void) untimeout(tid);
4700 }
4701
4702 void
e1000g_clear_interrupt(struct e1000g * Adapter)4703 e1000g_clear_interrupt(struct e1000g *Adapter)
4704 {
4705 E1000_WRITE_REG(&Adapter->shared, E1000_IMC,
4706 0xffffffff & ~E1000_IMS_RXSEQ);
4707 }
4708
4709 void
e1000g_mask_interrupt(struct e1000g * Adapter)4710 e1000g_mask_interrupt(struct e1000g *Adapter)
4711 {
4712 E1000_WRITE_REG(&Adapter->shared, E1000_IMS,
4713 IMS_ENABLE_MASK & ~E1000_IMS_TXDW);
4714
4715 if (Adapter->tx_intr_enable)
4716 e1000g_mask_tx_interrupt(Adapter);
4717 }
4718
4719 /*
4720 * This routine is called by e1000g_quiesce(), therefore must not block.
4721 */
4722 void
e1000g_clear_all_interrupts(struct e1000g * Adapter)4723 e1000g_clear_all_interrupts(struct e1000g *Adapter)
4724 {
4725 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff);
4726 }
4727
4728 void
e1000g_mask_tx_interrupt(struct e1000g * Adapter)4729 e1000g_mask_tx_interrupt(struct e1000g *Adapter)
4730 {
4731 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW);
4732 }
4733
4734 void
e1000g_clear_tx_interrupt(struct e1000g * Adapter)4735 e1000g_clear_tx_interrupt(struct e1000g *Adapter)
4736 {
4737 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW);
4738 }
4739
4740 static void
e1000g_smartspeed(struct e1000g * Adapter)4741 e1000g_smartspeed(struct e1000g *Adapter)
4742 {
4743 struct e1000_hw *hw = &Adapter->shared;
4744 uint16_t phy_status;
4745 uint16_t phy_ctrl;
4746
4747 /*
4748 * If we're not T-or-T, or we're not autoneg'ing, or we're not
4749 * advertising 1000Full, we don't even use the workaround
4750 */
4751 if ((hw->phy.type != e1000_phy_igp) ||
4752 !hw->mac.autoneg ||
4753 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL))
4754 return;
4755
4756 /*
4757 * True if this is the first call of this function or after every
4758 * 30 seconds of not having link
4759 */
4760 if (Adapter->smartspeed == 0) {
4761 /*
4762 * If Master/Slave config fault is asserted twice, we
4763 * assume back-to-back
4764 */
4765 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
4766 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT))
4767 return;
4768
4769 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
4770 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT))
4771 return;
4772 /*
4773 * We're assuming back-2-back because our status register
4774 * insists! there's a fault in the master/slave
4775 * relationship that was "negotiated"
4776 */
4777 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl);
4778 /*
4779 * Is the phy configured for manual configuration of
4780 * master/slave?
4781 */
4782 if (phy_ctrl & CR_1000T_MS_ENABLE) {
4783 /*
4784 * Yes. Then disable manual configuration (enable
4785 * auto configuration) of master/slave
4786 */
4787 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4788 (void) e1000_write_phy_reg(hw,
4789 PHY_1000T_CTRL, phy_ctrl);
4790 /*
4791 * Effectively starting the clock
4792 */
4793 Adapter->smartspeed++;
4794 /*
4795 * Restart autonegotiation
4796 */
4797 if (!e1000_phy_setup_autoneg(hw) &&
4798 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) {
4799 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4800 MII_CR_RESTART_AUTO_NEG);
4801 (void) e1000_write_phy_reg(hw,
4802 PHY_CONTROL, phy_ctrl);
4803 }
4804 }
4805 return;
4806 /*
4807 * Has 6 seconds transpired still without link? Remember,
4808 * you should reset the smartspeed counter once you obtain
4809 * link
4810 */
4811 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
4812 /*
4813 * Yes. Remember, we did at the start determine that
4814 * there's a master/slave configuration fault, so we're
4815 * still assuming there's someone on the other end, but we
4816 * just haven't yet been able to talk to it. We then
4817 * re-enable auto configuration of master/slave to see if
4818 * we're running 2/3 pair cables.
4819 */
4820 /*
4821 * If still no link, perhaps using 2/3 pair cable
4822 */
4823 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl);
4824 phy_ctrl |= CR_1000T_MS_ENABLE;
4825 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl);
4826 /*
4827 * Restart autoneg with phy enabled for manual
4828 * configuration of master/slave
4829 */
4830 if (!e1000_phy_setup_autoneg(hw) &&
4831 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) {
4832 phy_ctrl |=
4833 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
4834 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
4835 }
4836 /*
4837 * Hopefully, there are no more faults and we've obtained
4838 * link as a result.
4839 */
4840 }
4841 /*
4842 * Restart process after E1000_SMARTSPEED_MAX iterations (30
4843 * seconds)
4844 */
4845 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
4846 Adapter->smartspeed = 0;
4847 }
4848
4849 static boolean_t
is_valid_mac_addr(uint8_t * mac_addr)4850 is_valid_mac_addr(uint8_t *mac_addr)
4851 {
4852 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 };
4853 const uint8_t addr_test2[6] =
4854 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
4855
4856 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) ||
4857 !(bcmp(addr_test2, mac_addr, ETHERADDRL)))
4858 return (B_FALSE);
4859
4860 return (B_TRUE);
4861 }
4862
4863 /*
4864 * e1000g_stall_check - check for tx stall
4865 *
4866 * This function checks if the adapter is stalled (in transmit).
4867 *
4868 * It is called each time the watchdog timeout is invoked.
4869 * If the transmit descriptor reclaim continuously fails,
4870 * the watchdog value will increment by 1. If the watchdog
4871 * value exceeds the threshold, the adapter is assumed to
4872 * have stalled and need to be reset.
4873 */
4874 static boolean_t
e1000g_stall_check(struct e1000g * Adapter)4875 e1000g_stall_check(struct e1000g *Adapter)
4876 {
4877 e1000g_tx_ring_t *tx_ring;
4878
4879 tx_ring = Adapter->tx_ring;
4880
4881 if (Adapter->link_state != LINK_STATE_UP)
4882 return (B_FALSE);
4883
4884 (void) e1000g_recycle(tx_ring);
4885
4886 if (Adapter->stall_flag)
4887 return (B_TRUE);
4888
4889 return (B_FALSE);
4890 }
4891
4892 #ifdef E1000G_DEBUG
4893 static enum ioc_reply
e1000g_pp_ioctl(struct e1000g * e1000gp,struct iocblk * iocp,mblk_t * mp)4894 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp)
4895 {
4896 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd);
4897 e1000g_peekpoke_t *ppd;
4898 uint64_t mem_va;
4899 uint64_t maxoff;
4900 boolean_t peek;
4901
4902 switch (iocp->ioc_cmd) {
4903
4904 case E1000G_IOC_REG_PEEK:
4905 peek = B_TRUE;
4906 break;
4907
4908 case E1000G_IOC_REG_POKE:
4909 peek = B_FALSE;
4910 break;
4911
4912 deault:
4913 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL,
4914 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n",
4915 iocp->ioc_cmd);
4916 return (IOC_INVAL);
4917 }
4918
4919 /*
4920 * Validate format of ioctl
4921 */
4922 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t))
4923 return (IOC_INVAL);
4924 if (mp->b_cont == NULL)
4925 return (IOC_INVAL);
4926
4927 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr;
4928
4929 /*
4930 * Validate request parameters
4931 */
4932 switch (ppd->pp_acc_space) {
4933
4934 default:
4935 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL,
4936 "e1000g_diag_ioctl: invalid access space 0x%X\n",
4937 ppd->pp_acc_space);
4938 return (IOC_INVAL);
4939
4940 case E1000G_PP_SPACE_REG:
4941 /*
4942 * Memory-mapped I/O space
4943 */
4944 ASSERT(ppd->pp_acc_size == 4);
4945 if (ppd->pp_acc_size != 4)
4946 return (IOC_INVAL);
4947
4948 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
4949 return (IOC_INVAL);
4950
4951 mem_va = 0;
4952 maxoff = 0x10000;
4953 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg;
4954 break;
4955
4956 case E1000G_PP_SPACE_E1000G:
4957 /*
4958 * E1000g data structure!
4959 */
4960 mem_va = (uintptr_t)e1000gp;
4961 maxoff = sizeof (struct e1000g);
4962 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem;
4963 break;
4964
4965 }
4966
4967 if (ppd->pp_acc_offset >= maxoff)
4968 return (IOC_INVAL);
4969
4970 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff)
4971 return (IOC_INVAL);
4972
4973 /*
4974 * All OK - go!
4975 */
4976 ppd->pp_acc_offset += mem_va;
4977 (*ppfn)(e1000gp, ppd);
4978 return (peek ? IOC_REPLY : IOC_ACK);
4979 }
4980
4981 static void
e1000g_ioc_peek_reg(struct e1000g * e1000gp,e1000g_peekpoke_t * ppd)4982 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd)
4983 {
4984 ddi_acc_handle_t handle;
4985 uint32_t *regaddr;
4986
4987 handle = e1000gp->osdep.reg_handle;
4988 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr +
4989 (uintptr_t)ppd->pp_acc_offset);
4990
4991 ppd->pp_acc_data = ddi_get32(handle, regaddr);
4992 }
4993
4994 static void
e1000g_ioc_poke_reg(struct e1000g * e1000gp,e1000g_peekpoke_t * ppd)4995 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd)
4996 {
4997 ddi_acc_handle_t handle;
4998 uint32_t *regaddr;
4999 uint32_t value;
5000
5001 handle = e1000gp->osdep.reg_handle;
5002 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr +
5003 (uintptr_t)ppd->pp_acc_offset);
5004 value = (uint32_t)ppd->pp_acc_data;
5005
5006 ddi_put32(handle, regaddr, value);
5007 }
5008
5009 static void
e1000g_ioc_peek_mem(struct e1000g * e1000gp,e1000g_peekpoke_t * ppd)5010 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd)
5011 {
5012 uint64_t value;
5013 void *vaddr;
5014
5015 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5016
5017 switch (ppd->pp_acc_size) {
5018 case 1:
5019 value = *(uint8_t *)vaddr;
5020 break;
5021
5022 case 2:
5023 value = *(uint16_t *)vaddr;
5024 break;
5025
5026 case 4:
5027 value = *(uint32_t *)vaddr;
5028 break;
5029
5030 case 8:
5031 value = *(uint64_t *)vaddr;
5032 break;
5033 }
5034
5035 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL,
5036 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n",
5037 (void *)e1000gp, (void *)ppd, value, vaddr);
5038
5039 ppd->pp_acc_data = value;
5040 }
5041
5042 static void
e1000g_ioc_poke_mem(struct e1000g * e1000gp,e1000g_peekpoke_t * ppd)5043 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd)
5044 {
5045 uint64_t value;
5046 void *vaddr;
5047
5048 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5049 value = ppd->pp_acc_data;
5050
5051 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL,
5052 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n",
5053 (void *)e1000gp, (void *)ppd, value, vaddr);
5054
5055 switch (ppd->pp_acc_size) {
5056 case 1:
5057 *(uint8_t *)vaddr = (uint8_t)value;
5058 break;
5059
5060 case 2:
5061 *(uint16_t *)vaddr = (uint16_t)value;
5062 break;
5063
5064 case 4:
5065 *(uint32_t *)vaddr = (uint32_t)value;
5066 break;
5067
5068 case 8:
5069 *(uint64_t *)vaddr = (uint64_t)value;
5070 break;
5071 }
5072 }
5073 #endif
5074
5075 /*
5076 * Loopback Support
5077 */
5078 static lb_property_t lb_normal =
5079 { normal, "normal", E1000G_LB_NONE };
5080 static lb_property_t lb_external1000 =
5081 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 };
5082 static lb_property_t lb_external100 =
5083 { external, "100Mbps", E1000G_LB_EXTERNAL_100 };
5084 static lb_property_t lb_external10 =
5085 { external, "10Mbps", E1000G_LB_EXTERNAL_10 };
5086 static lb_property_t lb_phy =
5087 { internal, "PHY", E1000G_LB_INTERNAL_PHY };
5088
5089 static enum ioc_reply
e1000g_loopback_ioctl(struct e1000g * Adapter,struct iocblk * iocp,mblk_t * mp)5090 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp)
5091 {
5092 lb_info_sz_t *lbsp;
5093 lb_property_t *lbpp;
5094 struct e1000_hw *hw;
5095 uint32_t *lbmp;
5096 uint32_t size;
5097 uint32_t value;
5098
5099 hw = &Adapter->shared;
5100
5101 if (mp->b_cont == NULL)
5102 return (IOC_INVAL);
5103
5104 if (!e1000g_check_loopback_support(hw)) {
5105 e1000g_log(NULL, CE_WARN,
5106 "Loopback is not supported on e1000g%d", Adapter->instance);
5107 return (IOC_INVAL);
5108 }
5109
5110 switch (iocp->ioc_cmd) {
5111 default:
5112 return (IOC_INVAL);
5113
5114 case LB_GET_INFO_SIZE:
5115 size = sizeof (lb_info_sz_t);
5116 if (iocp->ioc_count != size)
5117 return (IOC_INVAL);
5118
5119 rw_enter(&Adapter->chip_lock, RW_WRITER);
5120 e1000g_get_phy_state(Adapter);
5121
5122 /*
5123 * Workaround for hardware faults. In order to get a stable
5124 * state of phy, we will wait for a specific interval and
5125 * try again. The time delay is an experiential value based
5126 * on our testing.
5127 */
5128 msec_delay(100);
5129 e1000g_get_phy_state(Adapter);
5130 rw_exit(&Adapter->chip_lock);
5131
5132 value = sizeof (lb_normal);
5133 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
5134 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) ||
5135 (hw->phy.media_type == e1000_media_type_fiber) ||
5136 (hw->phy.media_type == e1000_media_type_internal_serdes)) {
5137 value += sizeof (lb_phy);
5138 switch (hw->mac.type) {
5139 case e1000_82571:
5140 case e1000_82572:
5141 case e1000_80003es2lan:
5142 value += sizeof (lb_external1000);
5143 break;
5144 }
5145 }
5146 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
5147 (Adapter->phy_status & MII_SR_100T2_FD_CAPS))
5148 value += sizeof (lb_external100);
5149 if (Adapter->phy_status & MII_SR_10T_FD_CAPS)
5150 value += sizeof (lb_external10);
5151
5152 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr;
5153 *lbsp = value;
5154 break;
5155
5156 case LB_GET_INFO:
5157 value = sizeof (lb_normal);
5158 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
5159 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) ||
5160 (hw->phy.media_type == e1000_media_type_fiber) ||
5161 (hw->phy.media_type == e1000_media_type_internal_serdes)) {
5162 value += sizeof (lb_phy);
5163 switch (hw->mac.type) {
5164 case e1000_82571:
5165 case e1000_82572:
5166 case e1000_80003es2lan:
5167 value += sizeof (lb_external1000);
5168 break;
5169 }
5170 }
5171 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
5172 (Adapter->phy_status & MII_SR_100T2_FD_CAPS))
5173 value += sizeof (lb_external100);
5174 if (Adapter->phy_status & MII_SR_10T_FD_CAPS)
5175 value += sizeof (lb_external10);
5176
5177 size = value;
5178 if (iocp->ioc_count != size)
5179 return (IOC_INVAL);
5180
5181 value = 0;
5182 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr;
5183 lbpp[value++] = lb_normal;
5184 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
5185 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) ||
5186 (hw->phy.media_type == e1000_media_type_fiber) ||
5187 (hw->phy.media_type == e1000_media_type_internal_serdes)) {
5188 lbpp[value++] = lb_phy;
5189 switch (hw->mac.type) {
5190 case e1000_82571:
5191 case e1000_82572:
5192 case e1000_80003es2lan:
5193 lbpp[value++] = lb_external1000;
5194 break;
5195 }
5196 }
5197 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
5198 (Adapter->phy_status & MII_SR_100T2_FD_CAPS))
5199 lbpp[value++] = lb_external100;
5200 if (Adapter->phy_status & MII_SR_10T_FD_CAPS)
5201 lbpp[value++] = lb_external10;
5202 break;
5203
5204 case LB_GET_MODE:
5205 size = sizeof (uint32_t);
5206 if (iocp->ioc_count != size)
5207 return (IOC_INVAL);
5208
5209 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
5210 *lbmp = Adapter->loopback_mode;
5211 break;
5212
5213 case LB_SET_MODE:
5214 size = 0;
5215 if (iocp->ioc_count != sizeof (uint32_t))
5216 return (IOC_INVAL);
5217
5218 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
5219 if (!e1000g_set_loopback_mode(Adapter, *lbmp))
5220 return (IOC_INVAL);
5221 break;
5222 }
5223
5224 iocp->ioc_count = size;
5225 iocp->ioc_error = 0;
5226
5227 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
5228 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
5229 return (IOC_INVAL);
5230 }
5231
5232 return (IOC_REPLY);
5233 }
5234
5235 static boolean_t
e1000g_check_loopback_support(struct e1000_hw * hw)5236 e1000g_check_loopback_support(struct e1000_hw *hw)
5237 {
5238 switch (hw->mac.type) {
5239 case e1000_82540:
5240 case e1000_82545:
5241 case e1000_82545_rev_3:
5242 case e1000_82546:
5243 case e1000_82546_rev_3:
5244 case e1000_82541:
5245 case e1000_82541_rev_2:
5246 case e1000_82547:
5247 case e1000_82547_rev_2:
5248 case e1000_82571:
5249 case e1000_82572:
5250 case e1000_82573:
5251 case e1000_82574:
5252 case e1000_80003es2lan:
5253 case e1000_ich9lan:
5254 case e1000_ich10lan:
5255 return (B_TRUE);
5256 }
5257 return (B_FALSE);
5258 }
5259
5260 static boolean_t
e1000g_set_loopback_mode(struct e1000g * Adapter,uint32_t mode)5261 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode)
5262 {
5263 struct e1000_hw *hw;
5264 int i, times;
5265 boolean_t link_up;
5266
5267 if (mode == Adapter->loopback_mode)
5268 return (B_TRUE);
5269
5270 hw = &Adapter->shared;
5271 times = 0;
5272
5273 Adapter->loopback_mode = mode;
5274
5275 if (mode == E1000G_LB_NONE) {
5276 /* Reset the chip */
5277 hw->phy.autoneg_wait_to_complete = B_TRUE;
5278 (void) e1000g_reset_adapter(Adapter);
5279 hw->phy.autoneg_wait_to_complete = B_FALSE;
5280 return (B_TRUE);
5281 }
5282
5283 again:
5284
5285 rw_enter(&Adapter->chip_lock, RW_WRITER);
5286
5287 switch (mode) {
5288 default:
5289 rw_exit(&Adapter->chip_lock);
5290 return (B_FALSE);
5291
5292 case E1000G_LB_EXTERNAL_1000:
5293 e1000g_set_external_loopback_1000(Adapter);
5294 break;
5295
5296 case E1000G_LB_EXTERNAL_100:
5297 e1000g_set_external_loopback_100(Adapter);
5298 break;
5299
5300 case E1000G_LB_EXTERNAL_10:
5301 e1000g_set_external_loopback_10(Adapter);
5302 break;
5303
5304 case E1000G_LB_INTERNAL_PHY:
5305 e1000g_set_internal_loopback(Adapter);
5306 break;
5307 }
5308
5309 times++;
5310
5311 rw_exit(&Adapter->chip_lock);
5312
5313 /* Wait for link up */
5314 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--)
5315 msec_delay(100);
5316
5317 rw_enter(&Adapter->chip_lock, RW_WRITER);
5318
5319 link_up = e1000g_link_up(Adapter);
5320
5321 rw_exit(&Adapter->chip_lock);
5322
5323 if (!link_up) {
5324 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL,
5325 "Failed to get the link up");
5326 if (times < 2) {
5327 /* Reset the link */
5328 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL,
5329 "Reset the link ...");
5330 (void) e1000g_reset_adapter(Adapter);
5331 goto again;
5332 }
5333
5334 /*
5335 * Reset driver to loopback none when set loopback failed
5336 * for the second time.
5337 */
5338 Adapter->loopback_mode = E1000G_LB_NONE;
5339
5340 /* Reset the chip */
5341 hw->phy.autoneg_wait_to_complete = B_TRUE;
5342 (void) e1000g_reset_adapter(Adapter);
5343 hw->phy.autoneg_wait_to_complete = B_FALSE;
5344
5345 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL,
5346 "Set loopback mode failed, reset to loopback none");
5347
5348 return (B_FALSE);
5349 }
5350
5351 return (B_TRUE);
5352 }
5353
5354 /*
5355 * The following loopback settings are from Intel's technical
5356 * document - "How To Loopback". All the register settings and
5357 * time delay values are directly inherited from the document
5358 * without more explanations available.
5359 */
5360 static void
e1000g_set_internal_loopback(struct e1000g * Adapter)5361 e1000g_set_internal_loopback(struct e1000g *Adapter)
5362 {
5363 struct e1000_hw *hw;
5364 uint32_t ctrl;
5365 uint32_t status;
5366 uint16_t phy_ctrl;
5367 uint16_t phy_reg;
5368 uint32_t txcw;
5369
5370 hw = &Adapter->shared;
5371
5372 /* Disable Smart Power Down */
5373 phy_spd_state(hw, B_FALSE);
5374
5375 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
5376 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10);
5377 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000;
5378
5379 switch (hw->mac.type) {
5380 case e1000_82540:
5381 case e1000_82545:
5382 case e1000_82545_rev_3:
5383 case e1000_82546:
5384 case e1000_82546_rev_3:
5385 case e1000_82573:
5386 /* Auto-MDI/MDIX off */
5387 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
5388 /* Reset PHY to update Auto-MDI/MDIX */
5389 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5390 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN);
5391 /* Reset PHY to auto-neg off and force 1000 */
5392 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5393 phy_ctrl | MII_CR_RESET);
5394 /*
5395 * Disable PHY receiver for 82540/545/546 and 82573 Family.
5396 * See comments above e1000g_set_internal_loopback() for the
5397 * background.
5398 */
5399 (void) e1000_write_phy_reg(hw, 29, 0x001F);
5400 (void) e1000_write_phy_reg(hw, 30, 0x8FFC);
5401 (void) e1000_write_phy_reg(hw, 29, 0x001A);
5402 (void) e1000_write_phy_reg(hw, 30, 0x8FF0);
5403 break;
5404 case e1000_80003es2lan:
5405 /* Force Link Up */
5406 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
5407 0x1CC);
5408 /* Sets PCS loopback at 1Gbs */
5409 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
5410 0x1046);
5411 break;
5412 }
5413
5414 /*
5415 * The following registers should be set for e1000_phy_bm phy type.
5416 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy.
5417 * For others, we do not need to set these registers.
5418 */
5419 if (hw->phy.type == e1000_phy_bm) {
5420 /* Set Default MAC Interface speed to 1GB */
5421 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg);
5422 phy_reg &= ~0x0007;
5423 phy_reg |= 0x006;
5424 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg);
5425 /* Assert SW reset for above settings to take effect */
5426 (void) e1000_phy_commit(hw);
5427 msec_delay(1);
5428 /* Force Full Duplex */
5429 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg);
5430 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16),
5431 phy_reg | 0x000C);
5432 /* Set Link Up (in force link) */
5433 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg);
5434 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16),
5435 phy_reg | 0x0040);
5436 /* Force Link */
5437 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg);
5438 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16),
5439 phy_reg | 0x0040);
5440 /* Set Early Link Enable */
5441 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg);
5442 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20),
5443 phy_reg | 0x0400);
5444 }
5445
5446 /* Set loopback */
5447 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK);
5448
5449 msec_delay(250);
5450
5451 /* Now set up the MAC to the same speed/duplex as the PHY. */
5452 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5453 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
5454 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
5455 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
5456 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */
5457 E1000_CTRL_FD); /* Force Duplex to FULL */
5458
5459 switch (hw->mac.type) {
5460 case e1000_82540:
5461 case e1000_82545:
5462 case e1000_82545_rev_3:
5463 case e1000_82546:
5464 case e1000_82546_rev_3:
5465 /*
5466 * For some serdes we'll need to commit the writes now
5467 * so that the status is updated on link
5468 */
5469 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
5470 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5471 msec_delay(100);
5472 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5473 }
5474
5475 if (hw->phy.media_type == e1000_media_type_copper) {
5476 /* Invert Loss of Signal */
5477 ctrl |= E1000_CTRL_ILOS;
5478 } else {
5479 /* Set ILOS on fiber nic if half duplex is detected */
5480 status = E1000_READ_REG(hw, E1000_STATUS);
5481 if ((status & E1000_STATUS_FD) == 0)
5482 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU;
5483 }
5484 break;
5485
5486 case e1000_82571:
5487 case e1000_82572:
5488 /*
5489 * The fiber/SerDes versions of this adapter do not contain an
5490 * accessible PHY. Therefore, loopback beyond MAC must be done
5491 * using SerDes analog loopback.
5492 */
5493 if (hw->phy.media_type != e1000_media_type_copper) {
5494 /* Disable autoneg by setting bit 31 of TXCW to zero */
5495 txcw = E1000_READ_REG(hw, E1000_TXCW);
5496 txcw &= ~((uint32_t)1 << 31);
5497 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
5498
5499 /*
5500 * Write 0x410 to Serdes Control register
5501 * to enable Serdes analog loopback
5502 */
5503 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410);
5504 msec_delay(10);
5505 }
5506
5507 status = E1000_READ_REG(hw, E1000_STATUS);
5508 /* Set ILOS on fiber nic if half duplex is detected */
5509 if ((hw->phy.media_type == e1000_media_type_fiber) &&
5510 ((status & E1000_STATUS_FD) == 0 ||
5511 (status & E1000_STATUS_LU) == 0))
5512 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU;
5513 else if (hw->phy.media_type == e1000_media_type_internal_serdes)
5514 ctrl |= E1000_CTRL_SLU;
5515 break;
5516
5517 case e1000_82573:
5518 ctrl |= E1000_CTRL_ILOS;
5519 break;
5520 case e1000_ich9lan:
5521 case e1000_ich10lan:
5522 ctrl |= E1000_CTRL_SLU;
5523 break;
5524 }
5525 if (hw->phy.type == e1000_phy_bm)
5526 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS;
5527
5528 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5529 }
5530
5531 static void
e1000g_set_external_loopback_1000(struct e1000g * Adapter)5532 e1000g_set_external_loopback_1000(struct e1000g *Adapter)
5533 {
5534 struct e1000_hw *hw;
5535 uint32_t rctl;
5536 uint32_t ctrl_ext;
5537 uint32_t ctrl;
5538 uint32_t status;
5539 uint32_t txcw;
5540 uint16_t phydata;
5541
5542 hw = &Adapter->shared;
5543
5544 /* Disable Smart Power Down */
5545 phy_spd_state(hw, B_FALSE);
5546
5547 switch (hw->mac.type) {
5548 case e1000_82571:
5549 case e1000_82572:
5550 switch (hw->phy.media_type) {
5551 case e1000_media_type_copper:
5552 /* Force link up (Must be done before the PHY writes) */
5553 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5554 ctrl |= E1000_CTRL_SLU; /* Force Link Up */
5555 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5556
5557 rctl = E1000_READ_REG(hw, E1000_RCTL);
5558 rctl |= (E1000_RCTL_EN |
5559 E1000_RCTL_SBP |
5560 E1000_RCTL_UPE |
5561 E1000_RCTL_MPE |
5562 E1000_RCTL_LPE |
5563 E1000_RCTL_BAM); /* 0x803E */
5564 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
5565
5566 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5567 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA |
5568 E1000_CTRL_EXT_SDP6_DATA |
5569 E1000_CTRL_EXT_SDP3_DATA |
5570 E1000_CTRL_EXT_SDP4_DIR |
5571 E1000_CTRL_EXT_SDP6_DIR |
5572 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */
5573 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5574
5575 /*
5576 * This sequence tunes the PHY's SDP and no customer
5577 * settable values. For background, see comments above
5578 * e1000g_set_internal_loopback().
5579 */
5580 (void) e1000_write_phy_reg(hw, 0x0, 0x140);
5581 msec_delay(10);
5582 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00);
5583 (void) e1000_write_phy_reg(hw, 0x12, 0xC10);
5584 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10);
5585 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76);
5586 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1);
5587 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0);
5588
5589 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65);
5590 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C);
5591 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC);
5592 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C);
5593 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC);
5594
5595 msec_delay(50);
5596 break;
5597 case e1000_media_type_fiber:
5598 case e1000_media_type_internal_serdes:
5599 status = E1000_READ_REG(hw, E1000_STATUS);
5600 if (((status & E1000_STATUS_LU) == 0) ||
5601 (hw->phy.media_type ==
5602 e1000_media_type_internal_serdes)) {
5603 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5604 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU;
5605 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5606 }
5607
5608 /* Disable autoneg by setting bit 31 of TXCW to zero */
5609 txcw = E1000_READ_REG(hw, E1000_TXCW);
5610 txcw &= ~((uint32_t)1 << 31);
5611 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
5612
5613 /*
5614 * Write 0x410 to Serdes Control register
5615 * to enable Serdes analog loopback
5616 */
5617 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410);
5618 msec_delay(10);
5619 break;
5620 default:
5621 break;
5622 }
5623 break;
5624 case e1000_82574:
5625 case e1000_80003es2lan:
5626 case e1000_ich9lan:
5627 case e1000_ich10lan:
5628 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata);
5629 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16),
5630 phydata | (1 << 5));
5631 Adapter->param_adv_autoneg = 1;
5632 Adapter->param_adv_1000fdx = 1;
5633 (void) e1000g_reset_link(Adapter);
5634 break;
5635 }
5636 }
5637
5638 static void
e1000g_set_external_loopback_100(struct e1000g * Adapter)5639 e1000g_set_external_loopback_100(struct e1000g *Adapter)
5640 {
5641 struct e1000_hw *hw;
5642 uint32_t ctrl;
5643 uint16_t phy_ctrl;
5644
5645 hw = &Adapter->shared;
5646
5647 /* Disable Smart Power Down */
5648 phy_spd_state(hw, B_FALSE);
5649
5650 phy_ctrl = (MII_CR_FULL_DUPLEX |
5651 MII_CR_SPEED_100);
5652
5653 /* Force 100/FD, reset PHY */
5654 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5655 phy_ctrl | MII_CR_RESET); /* 0xA100 */
5656 msec_delay(10);
5657
5658 /* Force 100/FD */
5659 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5660 phy_ctrl); /* 0x2100 */
5661 msec_delay(10);
5662
5663 /* Now setup the MAC to the same speed/duplex as the PHY. */
5664 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5665 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
5666 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */
5667 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
5668 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
5669 E1000_CTRL_SPD_100 | /* Force Speed to 100 */
5670 E1000_CTRL_FD); /* Force Duplex to FULL */
5671
5672 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5673 }
5674
5675 static void
e1000g_set_external_loopback_10(struct e1000g * Adapter)5676 e1000g_set_external_loopback_10(struct e1000g *Adapter)
5677 {
5678 struct e1000_hw *hw;
5679 uint32_t ctrl;
5680 uint16_t phy_ctrl;
5681
5682 hw = &Adapter->shared;
5683
5684 /* Disable Smart Power Down */
5685 phy_spd_state(hw, B_FALSE);
5686
5687 phy_ctrl = (MII_CR_FULL_DUPLEX |
5688 MII_CR_SPEED_10);
5689
5690 /* Force 10/FD, reset PHY */
5691 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5692 phy_ctrl | MII_CR_RESET); /* 0x8100 */
5693 msec_delay(10);
5694
5695 /* Force 10/FD */
5696 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5697 phy_ctrl); /* 0x0100 */
5698 msec_delay(10);
5699
5700 /* Now setup the MAC to the same speed/duplex as the PHY. */
5701 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5702 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
5703 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */
5704 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
5705 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
5706 E1000_CTRL_SPD_10 | /* Force Speed to 10 */
5707 E1000_CTRL_FD); /* Force Duplex to FULL */
5708
5709 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5710 }
5711
5712 #ifdef __sparc
5713 static boolean_t
e1000g_find_mac_address(struct e1000g * Adapter)5714 e1000g_find_mac_address(struct e1000g *Adapter)
5715 {
5716 struct e1000_hw *hw = &Adapter->shared;
5717 uchar_t *bytes;
5718 struct ether_addr sysaddr;
5719 uint_t nelts;
5720 int err;
5721 boolean_t found = B_FALSE;
5722
5723 /*
5724 * The "vendor's factory-set address" may already have
5725 * been extracted from the chip, but if the property
5726 * "local-mac-address" is set we use that instead.
5727 *
5728 * We check whether it looks like an array of 6
5729 * bytes (which it should, if OBP set it). If we can't
5730 * make sense of it this way, we'll ignore it.
5731 */
5732 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip,
5733 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts);
5734 if (err == DDI_PROP_SUCCESS) {
5735 if (nelts == ETHERADDRL) {
5736 while (nelts--)
5737 hw->mac.addr[nelts] = bytes[nelts];
5738 found = B_TRUE;
5739 }
5740 ddi_prop_free(bytes);
5741 }
5742
5743 /*
5744 * Look up the OBP property "local-mac-address?". If the user has set
5745 * 'local-mac-address? = false', use "the system address" instead.
5746 */
5747 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0,
5748 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) {
5749 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) {
5750 if (localetheraddr(NULL, &sysaddr) != 0) {
5751 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
5752 found = B_TRUE;
5753 }
5754 }
5755 ddi_prop_free(bytes);
5756 }
5757
5758 /*
5759 * Finally(!), if there's a valid "mac-address" property (created
5760 * if we netbooted from this interface), we must use this instead
5761 * of any of the above to ensure that the NFS/install server doesn't
5762 * get confused by the address changing as Solaris takes over!
5763 */
5764 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip,
5765 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts);
5766 if (err == DDI_PROP_SUCCESS) {
5767 if (nelts == ETHERADDRL) {
5768 while (nelts--)
5769 hw->mac.addr[nelts] = bytes[nelts];
5770 found = B_TRUE;
5771 }
5772 ddi_prop_free(bytes);
5773 }
5774
5775 if (found) {
5776 bcopy(hw->mac.addr, hw->mac.perm_addr,
5777 ETHERADDRL);
5778 }
5779
5780 return (found);
5781 }
5782 #endif
5783
5784 static int
e1000g_add_intrs(struct e1000g * Adapter)5785 e1000g_add_intrs(struct e1000g *Adapter)
5786 {
5787 dev_info_t *devinfo;
5788 int intr_types;
5789 int rc;
5790
5791 devinfo = Adapter->dip;
5792
5793 /* Get supported interrupt types */
5794 rc = ddi_intr_get_supported_types(devinfo, &intr_types);
5795
5796 if (rc != DDI_SUCCESS) {
5797 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5798 "Get supported interrupt types failed: %d\n", rc);
5799 return (DDI_FAILURE);
5800 }
5801
5802 /*
5803 * Based on Intel Technical Advisory document (TA-160), there are some
5804 * cases where some older Intel PCI-X NICs may "advertise" to the OS
5805 * that it supports MSI, but in fact has problems.
5806 * So we should only enable MSI for PCI-E NICs and disable MSI for old
5807 * PCI/PCI-X NICs.
5808 */
5809 if (Adapter->shared.mac.type < e1000_82571)
5810 Adapter->msi_enable = B_FALSE;
5811
5812 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) {
5813 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI);
5814
5815 if (rc != DDI_SUCCESS) {
5816 /* EMPTY */
5817 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL,
5818 "Add MSI failed, trying Legacy interrupts\n");
5819 } else {
5820 Adapter->intr_type = DDI_INTR_TYPE_MSI;
5821 }
5822 }
5823
5824 if ((Adapter->intr_type == 0) &&
5825 (intr_types & DDI_INTR_TYPE_FIXED)) {
5826 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED);
5827
5828 if (rc != DDI_SUCCESS) {
5829 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL,
5830 "Add Legacy interrupts failed\n");
5831 return (DDI_FAILURE);
5832 }
5833
5834 Adapter->intr_type = DDI_INTR_TYPE_FIXED;
5835 }
5836
5837 if (Adapter->intr_type == 0) {
5838 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL,
5839 "No interrupts registered\n");
5840 return (DDI_FAILURE);
5841 }
5842
5843 return (DDI_SUCCESS);
5844 }
5845
5846 /*
5847 * e1000g_intr_add() handles MSI/Legacy interrupts
5848 */
5849 static int
e1000g_intr_add(struct e1000g * Adapter,int intr_type)5850 e1000g_intr_add(struct e1000g *Adapter, int intr_type)
5851 {
5852 dev_info_t *devinfo;
5853 int count, avail, actual;
5854 int x, y, rc, inum = 0;
5855 int flag;
5856 ddi_intr_handler_t *intr_handler;
5857
5858 devinfo = Adapter->dip;
5859
5860 /* get number of interrupts */
5861 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
5862 if ((rc != DDI_SUCCESS) || (count == 0)) {
5863 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL,
5864 "Get interrupt number failed. Return: %d, count: %d\n",
5865 rc, count);
5866 return (DDI_FAILURE);
5867 }
5868
5869 /* get number of available interrupts */
5870 rc = ddi_intr_get_navail(devinfo, intr_type, &avail);
5871 if ((rc != DDI_SUCCESS) || (avail == 0)) {
5872 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL,
5873 "Get interrupt available number failed. "
5874 "Return: %d, available: %d\n", rc, avail);
5875 return (DDI_FAILURE);
5876 }
5877
5878 if (avail < count) {
5879 /* EMPTY */
5880 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL,
5881 "Interrupts count: %d, available: %d\n",
5882 count, avail);
5883 }
5884
5885 /* Allocate an array of interrupt handles */
5886 Adapter->intr_size = count * sizeof (ddi_intr_handle_t);
5887 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP);
5888
5889 /* Set NORMAL behavior for both MSI and FIXED interrupt */
5890 flag = DDI_INTR_ALLOC_NORMAL;
5891
5892 /* call ddi_intr_alloc() */
5893 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum,
5894 count, &actual, flag);
5895
5896 if ((rc != DDI_SUCCESS) || (actual == 0)) {
5897 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5898 "Allocate interrupts failed: %d\n", rc);
5899
5900 kmem_free(Adapter->htable, Adapter->intr_size);
5901 return (DDI_FAILURE);
5902 }
5903
5904 if (actual < count) {
5905 /* EMPTY */
5906 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL,
5907 "Interrupts requested: %d, received: %d\n",
5908 count, actual);
5909 }
5910
5911 Adapter->intr_cnt = actual;
5912
5913 /* Get priority for first msi, assume remaining are all the same */
5914 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri);
5915
5916 if (rc != DDI_SUCCESS) {
5917 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5918 "Get interrupt priority failed: %d\n", rc);
5919
5920 /* Free already allocated intr */
5921 for (y = 0; y < actual; y++)
5922 (void) ddi_intr_free(Adapter->htable[y]);
5923
5924 kmem_free(Adapter->htable, Adapter->intr_size);
5925 return (DDI_FAILURE);
5926 }
5927
5928 /*
5929 * In Legacy Interrupt mode, for PCI-Express adapters, we should
5930 * use the interrupt service routine e1000g_intr_pciexpress()
5931 * to avoid interrupt stealing when sharing interrupt with other
5932 * devices.
5933 */
5934 if (Adapter->shared.mac.type < e1000_82571)
5935 intr_handler = (ddi_intr_handler_t *)e1000g_intr;
5936 else
5937 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress;
5938
5939 /* Call ddi_intr_add_handler() */
5940 for (x = 0; x < actual; x++) {
5941 rc = ddi_intr_add_handler(Adapter->htable[x],
5942 intr_handler, (caddr_t)Adapter, NULL);
5943
5944 if (rc != DDI_SUCCESS) {
5945 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5946 "Add interrupt handler failed: %d\n", rc);
5947
5948 /* Remove already added handler */
5949 for (y = 0; y < x; y++)
5950 (void) ddi_intr_remove_handler(
5951 Adapter->htable[y]);
5952
5953 /* Free already allocated intr */
5954 for (y = 0; y < actual; y++)
5955 (void) ddi_intr_free(Adapter->htable[y]);
5956
5957 kmem_free(Adapter->htable, Adapter->intr_size);
5958 return (DDI_FAILURE);
5959 }
5960 }
5961
5962 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap);
5963
5964 if (rc != DDI_SUCCESS) {
5965 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5966 "Get interrupt cap failed: %d\n", rc);
5967
5968 /* Free already allocated intr */
5969 for (y = 0; y < actual; y++) {
5970 (void) ddi_intr_remove_handler(Adapter->htable[y]);
5971 (void) ddi_intr_free(Adapter->htable[y]);
5972 }
5973
5974 kmem_free(Adapter->htable, Adapter->intr_size);
5975 return (DDI_FAILURE);
5976 }
5977
5978 return (DDI_SUCCESS);
5979 }
5980
5981 static int
e1000g_rem_intrs(struct e1000g * Adapter)5982 e1000g_rem_intrs(struct e1000g *Adapter)
5983 {
5984 int x;
5985 int rc;
5986
5987 for (x = 0; x < Adapter->intr_cnt; x++) {
5988 rc = ddi_intr_remove_handler(Adapter->htable[x]);
5989 if (rc != DDI_SUCCESS) {
5990 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5991 "Remove intr handler failed: %d\n", rc);
5992 return (DDI_FAILURE);
5993 }
5994
5995 rc = ddi_intr_free(Adapter->htable[x]);
5996 if (rc != DDI_SUCCESS) {
5997 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5998 "Free intr failed: %d\n", rc);
5999 return (DDI_FAILURE);
6000 }
6001 }
6002
6003 kmem_free(Adapter->htable, Adapter->intr_size);
6004
6005 return (DDI_SUCCESS);
6006 }
6007
6008 static int
e1000g_enable_intrs(struct e1000g * Adapter)6009 e1000g_enable_intrs(struct e1000g *Adapter)
6010 {
6011 int x;
6012 int rc;
6013
6014 /* Enable interrupts */
6015 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) {
6016 /* Call ddi_intr_block_enable() for MSI */
6017 rc = ddi_intr_block_enable(Adapter->htable,
6018 Adapter->intr_cnt);
6019 if (rc != DDI_SUCCESS) {
6020 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
6021 "Enable block intr failed: %d\n", rc);
6022 return (DDI_FAILURE);
6023 }
6024 } else {
6025 /* Call ddi_intr_enable() for Legacy/MSI non block enable */
6026 for (x = 0; x < Adapter->intr_cnt; x++) {
6027 rc = ddi_intr_enable(Adapter->htable[x]);
6028 if (rc != DDI_SUCCESS) {
6029 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
6030 "Enable intr failed: %d\n", rc);
6031 return (DDI_FAILURE);
6032 }
6033 }
6034 }
6035
6036 return (DDI_SUCCESS);
6037 }
6038
6039 static int
e1000g_disable_intrs(struct e1000g * Adapter)6040 e1000g_disable_intrs(struct e1000g *Adapter)
6041 {
6042 int x;
6043 int rc;
6044
6045 /* Disable all interrupts */
6046 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) {
6047 rc = ddi_intr_block_disable(Adapter->htable,
6048 Adapter->intr_cnt);
6049 if (rc != DDI_SUCCESS) {
6050 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
6051 "Disable block intr failed: %d\n", rc);
6052 return (DDI_FAILURE);
6053 }
6054 } else {
6055 for (x = 0; x < Adapter->intr_cnt; x++) {
6056 rc = ddi_intr_disable(Adapter->htable[x]);
6057 if (rc != DDI_SUCCESS) {
6058 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
6059 "Disable intr failed: %d\n", rc);
6060 return (DDI_FAILURE);
6061 }
6062 }
6063 }
6064
6065 return (DDI_SUCCESS);
6066 }
6067
6068 /*
6069 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter
6070 */
6071 static void
e1000g_get_phy_state(struct e1000g * Adapter)6072 e1000g_get_phy_state(struct e1000g *Adapter)
6073 {
6074 struct e1000_hw *hw = &Adapter->shared;
6075
6076 if (hw->phy.media_type == e1000_media_type_copper) {
6077 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl);
6078 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status);
6079 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
6080 &Adapter->phy_an_adv);
6081 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP,
6082 &Adapter->phy_an_exp);
6083 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS,
6084 &Adapter->phy_ext_status);
6085 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL,
6086 &Adapter->phy_1000t_ctrl);
6087 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6088 &Adapter->phy_1000t_status);
6089 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY,
6090 &Adapter->phy_lp_able);
6091
6092 Adapter->param_autoneg_cap =
6093 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0;
6094 Adapter->param_pause_cap =
6095 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
6096 Adapter->param_asym_pause_cap =
6097 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
6098 Adapter->param_1000fdx_cap =
6099 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
6100 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0;
6101 Adapter->param_1000hdx_cap =
6102 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) ||
6103 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0;
6104 Adapter->param_100t4_cap =
6105 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0;
6106 Adapter->param_100fdx_cap =
6107 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
6108 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0;
6109 Adapter->param_100hdx_cap =
6110 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) ||
6111 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0;
6112 Adapter->param_10fdx_cap =
6113 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0;
6114 Adapter->param_10hdx_cap =
6115 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0;
6116
6117 Adapter->param_adv_autoneg = hw->mac.autoneg;
6118 Adapter->param_adv_pause =
6119 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
6120 Adapter->param_adv_asym_pause =
6121 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
6122 Adapter->param_adv_1000hdx =
6123 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0;
6124 Adapter->param_adv_100t4 =
6125 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0;
6126 if (Adapter->param_adv_autoneg == 1) {
6127 Adapter->param_adv_1000fdx =
6128 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS)
6129 ? 1 : 0;
6130 Adapter->param_adv_100fdx =
6131 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS)
6132 ? 1 : 0;
6133 Adapter->param_adv_100hdx =
6134 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS)
6135 ? 1 : 0;
6136 Adapter->param_adv_10fdx =
6137 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0;
6138 Adapter->param_adv_10hdx =
6139 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0;
6140 }
6141
6142 Adapter->param_lp_autoneg =
6143 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0;
6144 Adapter->param_lp_pause =
6145 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0;
6146 Adapter->param_lp_asym_pause =
6147 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0;
6148 Adapter->param_lp_1000fdx =
6149 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0;
6150 Adapter->param_lp_1000hdx =
6151 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0;
6152 Adapter->param_lp_100t4 =
6153 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0;
6154 Adapter->param_lp_100fdx =
6155 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0;
6156 Adapter->param_lp_100hdx =
6157 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0;
6158 Adapter->param_lp_10fdx =
6159 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0;
6160 Adapter->param_lp_10hdx =
6161 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0;
6162 } else {
6163 /*
6164 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning,
6165 * it can only work with 1Gig Full Duplex Link Partner.
6166 */
6167 Adapter->param_autoneg_cap = 0;
6168 Adapter->param_pause_cap = 1;
6169 Adapter->param_asym_pause_cap = 1;
6170 Adapter->param_1000fdx_cap = 1;
6171 Adapter->param_1000hdx_cap = 0;
6172 Adapter->param_100t4_cap = 0;
6173 Adapter->param_100fdx_cap = 0;
6174 Adapter->param_100hdx_cap = 0;
6175 Adapter->param_10fdx_cap = 0;
6176 Adapter->param_10hdx_cap = 0;
6177
6178 Adapter->param_adv_autoneg = 0;
6179 Adapter->param_adv_pause = 1;
6180 Adapter->param_adv_asym_pause = 1;
6181 Adapter->param_adv_1000fdx = 1;
6182 Adapter->param_adv_1000hdx = 0;
6183 Adapter->param_adv_100t4 = 0;
6184 Adapter->param_adv_100fdx = 0;
6185 Adapter->param_adv_100hdx = 0;
6186 Adapter->param_adv_10fdx = 0;
6187 Adapter->param_adv_10hdx = 0;
6188
6189 Adapter->param_lp_autoneg = 0;
6190 Adapter->param_lp_pause = 0;
6191 Adapter->param_lp_asym_pause = 0;
6192 Adapter->param_lp_1000fdx = 0;
6193 Adapter->param_lp_1000hdx = 0;
6194 Adapter->param_lp_100t4 = 0;
6195 Adapter->param_lp_100fdx = 0;
6196 Adapter->param_lp_100hdx = 0;
6197 Adapter->param_lp_10fdx = 0;
6198 Adapter->param_lp_10hdx = 0;
6199 }
6200 }
6201
6202 /*
6203 * FMA support
6204 */
6205
6206 int
e1000g_check_acc_handle(ddi_acc_handle_t handle)6207 e1000g_check_acc_handle(ddi_acc_handle_t handle)
6208 {
6209 ddi_fm_error_t de;
6210
6211 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
6212 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
6213 return (de.fme_status);
6214 }
6215
6216 int
e1000g_check_dma_handle(ddi_dma_handle_t handle)6217 e1000g_check_dma_handle(ddi_dma_handle_t handle)
6218 {
6219 ddi_fm_error_t de;
6220
6221 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
6222 return (de.fme_status);
6223 }
6224
6225 /*
6226 * The IO fault service error handling callback function
6227 */
6228 /* ARGSUSED2 */
6229 static int
e1000g_fm_error_cb(dev_info_t * dip,ddi_fm_error_t * err,const void * impl_data)6230 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
6231 {
6232 /*
6233 * as the driver can always deal with an error in any dma or
6234 * access handle, we can just return the fme_status value.
6235 */
6236 pci_ereport_post(dip, err, NULL);
6237 return (err->fme_status);
6238 }
6239
6240 static void
e1000g_fm_init(struct e1000g * Adapter)6241 e1000g_fm_init(struct e1000g *Adapter)
6242 {
6243 ddi_iblock_cookie_t iblk;
6244 int fma_dma_flag;
6245
6246 /* Only register with IO Fault Services if we have some capability */
6247 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
6248 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
6249 } else {
6250 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
6251 }
6252
6253 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
6254 fma_dma_flag = 1;
6255 } else {
6256 fma_dma_flag = 0;
6257 }
6258
6259 (void) e1000g_set_fma_flags(fma_dma_flag);
6260
6261 if (Adapter->fm_capabilities) {
6262
6263 /* Register capabilities with IO Fault Services */
6264 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk);
6265
6266 /*
6267 * Initialize pci ereport capabilities if ereport capable
6268 */
6269 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) ||
6270 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities))
6271 pci_ereport_setup(Adapter->dip);
6272
6273 /*
6274 * Register error callback if error callback capable
6275 */
6276 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities))
6277 ddi_fm_handler_register(Adapter->dip,
6278 e1000g_fm_error_cb, (void*) Adapter);
6279 }
6280 }
6281
6282 static void
e1000g_fm_fini(struct e1000g * Adapter)6283 e1000g_fm_fini(struct e1000g *Adapter)
6284 {
6285 /* Only unregister FMA capabilities if we registered some */
6286 if (Adapter->fm_capabilities) {
6287
6288 /*
6289 * Release any resources allocated by pci_ereport_setup()
6290 */
6291 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) ||
6292 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities))
6293 pci_ereport_teardown(Adapter->dip);
6294
6295 /*
6296 * Un-register error callback if error callback capable
6297 */
6298 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities))
6299 ddi_fm_handler_unregister(Adapter->dip);
6300
6301 /* Unregister from IO Fault Services */
6302 mutex_enter(&e1000g_rx_detach_lock);
6303 ddi_fm_fini(Adapter->dip);
6304 if (Adapter->priv_dip != NULL) {
6305 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL;
6306 }
6307 mutex_exit(&e1000g_rx_detach_lock);
6308 }
6309 }
6310
6311 void
e1000g_fm_ereport(struct e1000g * Adapter,char * detail)6312 e1000g_fm_ereport(struct e1000g *Adapter, char *detail)
6313 {
6314 uint64_t ena;
6315 char buf[FM_MAX_CLASS];
6316
6317 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
6318 ena = fm_ena_generate(0, FM_ENA_FMT1);
6319 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) {
6320 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP,
6321 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
6322 }
6323 }
6324
6325 /*
6326 * quiesce(9E) entry point.
6327 *
6328 * This function is called when the system is single-threaded at high
6329 * PIL with preemption disabled. Therefore, this function must not be
6330 * blocked.
6331 *
6332 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
6333 * DDI_FAILURE indicates an error condition and should almost never happen.
6334 */
6335 static int
e1000g_quiesce(dev_info_t * devinfo)6336 e1000g_quiesce(dev_info_t *devinfo)
6337 {
6338 struct e1000g *Adapter;
6339
6340 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo);
6341
6342 if (Adapter == NULL)
6343 return (DDI_FAILURE);
6344
6345 e1000g_clear_all_interrupts(Adapter);
6346
6347 (void) e1000_reset_hw(&Adapter->shared);
6348
6349 /* Setup our HW Tx Head & Tail descriptor pointers */
6350 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0);
6351 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0);
6352
6353 /* Setup our HW Rx Head & Tail descriptor pointers */
6354 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0);
6355 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0);
6356
6357 return (DDI_SUCCESS);
6358 }
6359
6360 /*
6361 * synchronize the adv* and en* parameters.
6362 *
6363 * See comments in <sys/dld.h> for details of the *_en_*
6364 * parameters. The usage of ndd for setting adv parameters will
6365 * synchronize all the en parameters with the e1000g parameters,
6366 * implicitly disabling any settings made via dladm.
6367 */
6368 static void
e1000g_param_sync(struct e1000g * Adapter)6369 e1000g_param_sync(struct e1000g *Adapter)
6370 {
6371 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx;
6372 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx;
6373 Adapter->param_en_100fdx = Adapter->param_adv_100fdx;
6374 Adapter->param_en_100hdx = Adapter->param_adv_100hdx;
6375 Adapter->param_en_10fdx = Adapter->param_adv_10fdx;
6376 Adapter->param_en_10hdx = Adapter->param_adv_10hdx;
6377 }
6378
6379 /*
6380 * e1000g_get_driver_control - tell manageability firmware that the driver
6381 * has control.
6382 */
6383 static void
e1000g_get_driver_control(struct e1000_hw * hw)6384 e1000g_get_driver_control(struct e1000_hw *hw)
6385 {
6386 uint32_t ctrl_ext;
6387 uint32_t swsm;
6388
6389 /* tell manageability firmware the driver has taken over */
6390 switch (hw->mac.type) {
6391 case e1000_82573:
6392 swsm = E1000_READ_REG(hw, E1000_SWSM);
6393 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
6394 break;
6395 case e1000_82571:
6396 case e1000_82572:
6397 case e1000_82574:
6398 case e1000_80003es2lan:
6399 case e1000_ich8lan:
6400 case e1000_ich9lan:
6401 case e1000_ich10lan:
6402 case e1000_pchlan:
6403 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
6404 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
6405 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
6406 break;
6407 default:
6408 /* no manageability firmware: do nothing */
6409 break;
6410 }
6411 }
6412
6413 /*
6414 * e1000g_release_driver_control - tell manageability firmware that the driver
6415 * has released control.
6416 */
6417 static void
e1000g_release_driver_control(struct e1000_hw * hw)6418 e1000g_release_driver_control(struct e1000_hw *hw)
6419 {
6420 uint32_t ctrl_ext;
6421 uint32_t swsm;
6422
6423 /* tell manageability firmware the driver has released control */
6424 switch (hw->mac.type) {
6425 case e1000_82573:
6426 swsm = E1000_READ_REG(hw, E1000_SWSM);
6427 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
6428 break;
6429 case e1000_82571:
6430 case e1000_82572:
6431 case e1000_82574:
6432 case e1000_80003es2lan:
6433 case e1000_ich8lan:
6434 case e1000_ich9lan:
6435 case e1000_ich10lan:
6436 case e1000_pchlan:
6437 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
6438 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
6439 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
6440 break;
6441 default:
6442 /* no manageability firmware: do nothing */
6443 break;
6444 }
6445 }
6446
6447 /*
6448 * Restore e1000g promiscuous mode.
6449 */
6450 static void
e1000g_restore_promisc(struct e1000g * Adapter)6451 e1000g_restore_promisc(struct e1000g *Adapter)
6452 {
6453 if (Adapter->e1000g_promisc) {
6454 uint32_t rctl;
6455
6456 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL);
6457 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM);
6458 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl);
6459 }
6460 }
6461