1 /*
2 * This file is provided under a CDDLv1 license. When using or
3 * redistributing this file, you may do so under this license.
4 * In redistributing this file this license must be included
5 * and no other modification of this header file is permitted.
6 *
7 * CDDL LICENSE SUMMARY
8 *
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10 *
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
13 *
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 * http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
19 */
20
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms of the CDDLv1.
24 */
25
26 /*
27 * IntelVersion: 1.49 v3-1-10-1_2009-9-18_Release14-6
28 */
29 #include "e1000_api.h"
30
31 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
32
33 /*
34 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
35 * @hw: pointer to the HW structure
36 *
37 * Setups up the function pointers to no-op functions
38 */
39 void
e1000_init_nvm_ops_generic(struct e1000_hw * hw)40 e1000_init_nvm_ops_generic(struct e1000_hw *hw)
41 {
42 struct e1000_nvm_info *nvm = &hw->nvm;
43 DEBUGFUNC("e1000_init_nvm_ops_generic");
44
45 /* Initialize function pointers */
46 nvm->ops.init_params = e1000_null_ops_generic;
47 nvm->ops.acquire = e1000_null_ops_generic;
48 nvm->ops.read = e1000_null_read_nvm;
49 nvm->ops.release = e1000_null_nvm_generic;
50 nvm->ops.reload = e1000_reload_nvm_generic;
51 nvm->ops.update = e1000_null_ops_generic;
52 nvm->ops.valid_led_default = e1000_null_led_default;
53 nvm->ops.validate = e1000_null_ops_generic;
54 nvm->ops.write = e1000_null_write_nvm;
55 }
56
57 /*
58 * e1000_null_nvm_read - No-op function, return 0
59 * @hw: pointer to the HW structure
60 */
61 s32
e1000_null_read_nvm(struct e1000_hw * hw,u16 a,u16 b,u16 * c)62 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
63 {
64 DEBUGFUNC("e1000_null_read_nvm");
65 UNREFERENCED_4PARAMETER(hw, a, b, c);
66 return (E1000_SUCCESS);
67 }
68
69 /*
70 * e1000_null_nvm_generic - No-op function, return void
71 * @hw: pointer to the HW structure
72 */
73 void
e1000_null_nvm_generic(struct e1000_hw * hw)74 e1000_null_nvm_generic(struct e1000_hw *hw)
75 {
76 DEBUGFUNC("e1000_null_nvm_generic");
77 UNREFERENCED_1PARAMETER(hw);
78 }
79
80 /*
81 * e1000_null_led_default - No-op function, return 0
82 * @hw: pointer to the HW structure
83 */
84 s32
e1000_null_led_default(struct e1000_hw * hw,u16 * data)85 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
86 {
87 DEBUGFUNC("e1000_null_led_default");
88 UNREFERENCED_2PARAMETER(hw, data);
89 return (E1000_SUCCESS);
90 }
91
92 /*
93 * e1000_null_write_nvm - No-op function, return 0
94 * @hw: pointer to the HW structure
95 */
96 s32
e1000_null_write_nvm(struct e1000_hw * hw,u16 a,u16 b,u16 * c)97 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
98 {
99 DEBUGFUNC("e1000_null_write_nvm");
100 UNREFERENCED_4PARAMETER(hw, a, b, c);
101 return (E1000_SUCCESS);
102 }
103
104 /*
105 * e1000_raise_eec_clk - Raise EEPROM clock
106 * @hw: pointer to the HW structure
107 * @eecd: pointer to the EEPROM
108 *
109 * Enable/Raise the EEPROM clock bit.
110 */
111 static void
e1000_raise_eec_clk(struct e1000_hw * hw,u32 * eecd)112 e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
113 {
114 *eecd = *eecd | E1000_EECD_SK;
115 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
116 E1000_WRITE_FLUSH(hw);
117 usec_delay(hw->nvm.delay_usec);
118 }
119
120 /*
121 * e1000_lower_eec_clk - Lower EEPROM clock
122 * @hw: pointer to the HW structure
123 * @eecd: pointer to the EEPROM
124 *
125 * Clear/Lower the EEPROM clock bit.
126 */
127 static void
e1000_lower_eec_clk(struct e1000_hw * hw,u32 * eecd)128 e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
129 {
130 *eecd = *eecd & ~E1000_EECD_SK;
131 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
132 E1000_WRITE_FLUSH(hw);
133 usec_delay(hw->nvm.delay_usec);
134 }
135
136 /*
137 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
138 * @hw: pointer to the HW structure
139 * @data: data to send to the EEPROM
140 * @count: number of bits to shift out
141 *
142 * We need to shift 'count' bits out to the EEPROM. So, the value in the
143 * "data" parameter will be shifted out to the EEPROM one bit at a time.
144 * In order to do this, "data" must be broken down into bits.
145 */
146 static void
e1000_shift_out_eec_bits(struct e1000_hw * hw,u16 data,u16 count)147 e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
148 {
149 struct e1000_nvm_info *nvm = &hw->nvm;
150 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
151 u32 mask;
152
153 DEBUGFUNC("e1000_shift_out_eec_bits");
154
155 mask = 0x01 << (count - 1);
156 if (nvm->type == e1000_nvm_eeprom_microwire)
157 eecd &= ~E1000_EECD_DO;
158 else if (nvm->type == e1000_nvm_eeprom_spi)
159 eecd |= E1000_EECD_DO;
160
161 do {
162 eecd &= ~E1000_EECD_DI;
163
164 if (data & mask)
165 eecd |= E1000_EECD_DI;
166
167 E1000_WRITE_REG(hw, E1000_EECD, eecd);
168 E1000_WRITE_FLUSH(hw);
169
170 usec_delay(nvm->delay_usec);
171
172 e1000_raise_eec_clk(hw, &eecd);
173 e1000_lower_eec_clk(hw, &eecd);
174
175 mask >>= 1;
176 } while (mask);
177
178 eecd &= ~E1000_EECD_DI;
179 E1000_WRITE_REG(hw, E1000_EECD, eecd);
180 }
181
182 /*
183 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
184 * @hw: pointer to the HW structure
185 * @count: number of bits to shift in
186 *
187 * In order to read a register from the EEPROM, we need to shift 'count' bits
188 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
189 * the EEPROM (setting the SK bit), and then reading the value of the data out
190 * "DO" bit. During this "shifting in" process the data in "DI" bit should
191 * always be clear.
192 */
193 static u16
e1000_shift_in_eec_bits(struct e1000_hw * hw,u16 count)194 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
195 {
196 u32 eecd;
197 u32 i;
198 u16 data;
199
200 DEBUGFUNC("e1000_shift_in_eec_bits");
201
202 eecd = E1000_READ_REG(hw, E1000_EECD);
203
204 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
205 data = 0;
206
207 for (i = 0; i < count; i++) {
208 data <<= 1;
209 e1000_raise_eec_clk(hw, &eecd);
210
211 eecd = E1000_READ_REG(hw, E1000_EECD);
212
213 eecd &= ~E1000_EECD_DI;
214 if (eecd & E1000_EECD_DO)
215 data |= 1;
216
217 e1000_lower_eec_clk(hw, &eecd);
218 }
219
220 return (data);
221 }
222
223 /*
224 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
225 * @hw: pointer to the HW structure
226 * @ee_reg: EEPROM flag for polling
227 *
228 * Polls the EEPROM status bit for either read or write completion based
229 * upon the value of 'ee_reg'.
230 */
231 s32
e1000_poll_eerd_eewr_done(struct e1000_hw * hw,int ee_reg)232 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
233 {
234 u32 attempts = 100000;
235 u32 i, reg = 0;
236 s32 ret_val = -E1000_ERR_NVM;
237
238 DEBUGFUNC("e1000_poll_eerd_eewr_done");
239
240 for (i = 0; i < attempts; i++) {
241 if (ee_reg == E1000_NVM_POLL_READ)
242 reg = E1000_READ_REG(hw, E1000_EERD);
243 else
244 reg = E1000_READ_REG(hw, E1000_EEWR);
245
246 if (reg & E1000_NVM_RW_REG_DONE) {
247 ret_val = E1000_SUCCESS;
248 break;
249 }
250
251 usec_delay(5);
252 }
253
254 return (ret_val);
255 }
256
257 /*
258 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
259 * @hw: pointer to the HW structure
260 *
261 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
262 * Return successful if access grant bit set, else clear the request for
263 * EEPROM access and return -E1000_ERR_NVM (-1).
264 */
265 s32
e1000_acquire_nvm_generic(struct e1000_hw * hw)266 e1000_acquire_nvm_generic(struct e1000_hw *hw)
267 {
268 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
269 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
270 s32 ret_val = E1000_SUCCESS;
271
272 DEBUGFUNC("e1000_acquire_nvm_generic");
273
274 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
275 eecd = E1000_READ_REG(hw, E1000_EECD);
276
277 while (timeout) {
278 if (eecd & E1000_EECD_GNT)
279 break;
280 usec_delay(5);
281 eecd = E1000_READ_REG(hw, E1000_EECD);
282 timeout--;
283 }
284
285 if (!timeout) {
286 eecd &= ~E1000_EECD_REQ;
287 E1000_WRITE_REG(hw, E1000_EECD, eecd);
288 DEBUGOUT("Could not acquire NVM grant\n");
289 ret_val = -E1000_ERR_NVM;
290 }
291 return (ret_val);
292 }
293
294 /*
295 * e1000_standby_nvm - Return EEPROM to standby state
296 * @hw: pointer to the HW structure
297 *
298 * Return the EEPROM to a standby state.
299 */
300 static void
e1000_standby_nvm(struct e1000_hw * hw)301 e1000_standby_nvm(struct e1000_hw *hw)
302 {
303 struct e1000_nvm_info *nvm = &hw->nvm;
304 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
305
306 DEBUGFUNC("e1000_standby_nvm");
307
308 if (nvm->type == e1000_nvm_eeprom_microwire) {
309 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
310 E1000_WRITE_REG(hw, E1000_EECD, eecd);
311 E1000_WRITE_FLUSH(hw);
312 usec_delay(nvm->delay_usec);
313
314 e1000_raise_eec_clk(hw, &eecd);
315
316 /* Select EEPROM */
317 eecd |= E1000_EECD_CS;
318 E1000_WRITE_REG(hw, E1000_EECD, eecd);
319 E1000_WRITE_FLUSH(hw);
320 usec_delay(nvm->delay_usec);
321
322 e1000_lower_eec_clk(hw, &eecd);
323 } else if (nvm->type == e1000_nvm_eeprom_spi) {
324 /* Toggle CS to flush commands */
325 eecd |= E1000_EECD_CS;
326 E1000_WRITE_REG(hw, E1000_EECD, eecd);
327 E1000_WRITE_FLUSH(hw);
328 usec_delay(nvm->delay_usec);
329 eecd &= ~E1000_EECD_CS;
330 E1000_WRITE_REG(hw, E1000_EECD, eecd);
331 E1000_WRITE_FLUSH(hw);
332 usec_delay(nvm->delay_usec);
333 }
334 }
335
336 /*
337 * e1000_stop_nvm - Terminate EEPROM command
338 * @hw: pointer to the HW structure
339 *
340 * Terminates the current command by inverting the EEPROM's chip select pin.
341 */
342 void
e1000_stop_nvm(struct e1000_hw * hw)343 e1000_stop_nvm(struct e1000_hw *hw)
344 {
345 u32 eecd;
346
347 DEBUGFUNC("e1000_stop_nvm");
348
349 eecd = E1000_READ_REG(hw, E1000_EECD);
350 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
351 /* Pull CS high */
352 eecd |= E1000_EECD_CS;
353 e1000_lower_eec_clk(hw, &eecd);
354 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
355 /* CS on Microwire is active-high */
356 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
357 E1000_WRITE_REG(hw, E1000_EECD, eecd);
358 e1000_raise_eec_clk(hw, &eecd);
359 e1000_lower_eec_clk(hw, &eecd);
360 }
361 }
362
363 /*
364 * e1000_release_nvm_generic - Release exclusive access to EEPROM
365 * @hw: pointer to the HW structure
366 *
367 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
368 */
369 void
e1000_release_nvm_generic(struct e1000_hw * hw)370 e1000_release_nvm_generic(struct e1000_hw *hw)
371 {
372 u32 eecd;
373
374 DEBUGFUNC("e1000_release_nvm_generic");
375
376 e1000_stop_nvm(hw);
377
378 eecd = E1000_READ_REG(hw, E1000_EECD);
379 eecd &= ~E1000_EECD_REQ;
380 E1000_WRITE_REG(hw, E1000_EECD, eecd);
381 }
382
383 /*
384 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
385 * @hw: pointer to the HW structure
386 *
387 * Setups the EEPROM for reading and writing.
388 */
389 static s32
e1000_ready_nvm_eeprom(struct e1000_hw * hw)390 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
391 {
392 struct e1000_nvm_info *nvm = &hw->nvm;
393 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
394 s32 ret_val = E1000_SUCCESS;
395 u16 timeout = 0;
396 u8 spi_stat_reg;
397
398 DEBUGFUNC("e1000_ready_nvm_eeprom");
399
400 if (nvm->type == e1000_nvm_eeprom_microwire) {
401 /* Clear SK and DI */
402 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
403 E1000_WRITE_REG(hw, E1000_EECD, eecd);
404 /* Set CS */
405 eecd |= E1000_EECD_CS;
406 E1000_WRITE_REG(hw, E1000_EECD, eecd);
407 } else if (nvm->type == e1000_nvm_eeprom_spi) {
408 /* Clear SK and CS */
409 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
410 E1000_WRITE_REG(hw, E1000_EECD, eecd);
411 usec_delay(1);
412 timeout = NVM_MAX_RETRY_SPI;
413
414 /*
415 * Read "Status Register" repeatedly until the LSB is cleared.
416 * The EEPROM will signal that the command has been completed
417 * by clearing bit 0 of the internal status register. If it's
418 * not cleared within 'timeout', then error out.
419 */
420 while (timeout) {
421 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
422 hw->nvm.opcode_bits);
423 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
424 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
425 break;
426
427 usec_delay(5);
428 e1000_standby_nvm(hw);
429 timeout--;
430 }
431
432 if (!timeout) {
433 DEBUGOUT("SPI NVM Status error\n");
434 ret_val = -E1000_ERR_NVM;
435 goto out;
436 }
437 }
438
439 out:
440 return (ret_val);
441 }
442
443 /*
444 * e1000_read_nvm_spi - Read EEPROM's using SPI
445 * @hw: pointer to the HW structure
446 * @offset: offset of word in the EEPROM to read
447 * @words: number of words to read
448 * @data: word read from the EEPROM
449 *
450 * Reads a 16 bit word from the EEPROM.
451 */
452 s32
e1000_read_nvm_spi(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)453 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 * data)
454 {
455 struct e1000_nvm_info *nvm = &hw->nvm;
456 u32 i = 0;
457 s32 ret_val;
458 u16 word_in;
459 u8 read_opcode = NVM_READ_OPCODE_SPI;
460
461 DEBUGFUNC("e1000_read_nvm_spi");
462
463 /*
464 * A check for invalid values: offset too large, too many words, and
465 * not enough words.
466 */
467 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
468 (words == 0)) {
469 DEBUGOUT("nvm parameter(s) out of bounds\n");
470 ret_val = -E1000_ERR_NVM;
471 goto out;
472 }
473
474 ret_val = nvm->ops.acquire(hw);
475 if (ret_val)
476 goto out;
477
478 ret_val = e1000_ready_nvm_eeprom(hw);
479 if (ret_val)
480 goto release;
481
482 e1000_standby_nvm(hw);
483
484 if ((nvm->address_bits == 8) && (offset >= 128))
485 read_opcode |= NVM_A8_OPCODE_SPI;
486
487 /* Send the READ command (opcode + addr) */
488 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
489 e1000_shift_out_eec_bits(hw, (u16)(offset * 2), nvm->address_bits);
490
491 /*
492 * Read the data. SPI NVMs increment the address with each byte read
493 * and will roll over if reading beyond the end. This allows us to
494 * read the whole NVM from any offset
495 */
496 for (i = 0; i < words; i++) {
497 word_in = e1000_shift_in_eec_bits(hw, 16);
498 data[i] = (word_in >> 8) | (word_in << 8);
499 }
500
501 release:
502 nvm->ops.release(hw);
503
504 out:
505 return (ret_val);
506 }
507
508 /*
509 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
510 * @hw: pointer to the HW structure
511 * @offset: offset of word in the EEPROM to read
512 * @words: number of words to read
513 * @data: word read from the EEPROM
514 *
515 * Reads a 16 bit word from the EEPROM.
516 */
517 s32
e1000_read_nvm_microwire(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)518 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
519 {
520 struct e1000_nvm_info *nvm = &hw->nvm;
521 u32 i = 0;
522 s32 ret_val;
523 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
524
525 DEBUGFUNC("e1000_read_nvm_microwire");
526
527 /*
528 * A check for invalid values: offset too large, too many words, and
529 * not enough words.
530 */
531 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
532 (words == 0)) {
533 DEBUGOUT("nvm parameter(s) out of bounds\n");
534 ret_val = -E1000_ERR_NVM;
535 goto out;
536 }
537
538 ret_val = nvm->ops.acquire(hw);
539 if (ret_val)
540 goto out;
541
542 ret_val = e1000_ready_nvm_eeprom(hw);
543 if (ret_val)
544 goto release;
545
546 for (i = 0; i < words; i++) {
547 /* Send the READ command (opcode + addr) */
548 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
549 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
550 nvm->address_bits);
551
552 /*
553 * Read the data. For microwire, each word requires the
554 * overhead of setup and tear-down.
555 */
556 data[i] = e1000_shift_in_eec_bits(hw, 16);
557 e1000_standby_nvm(hw);
558 }
559
560 release:
561 nvm->ops.release(hw);
562
563 out:
564 return (ret_val);
565 }
566
567 /*
568 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
569 * @hw: pointer to the HW structure
570 * @offset: offset of word in the EEPROM to read
571 * @words: number of words to read
572 * @data: word read from the EEPROM
573 *
574 * Reads a 16 bit word from the EEPROM using the EERD register.
575 */
576 s32
e1000_read_nvm_eerd(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)577 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
578 {
579 struct e1000_nvm_info *nvm = &hw->nvm;
580 u32 i, eerd = 0;
581 s32 ret_val = E1000_SUCCESS;
582
583 DEBUGFUNC("e1000_read_nvm_eerd");
584
585 /*
586 * A check for invalid values: offset too large, too many words,
587 * too many words for the offset, and not enough words.
588 */
589 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
590 (words == 0)) {
591 DEBUGOUT("nvm parameter(s) out of bounds\n");
592 ret_val = -E1000_ERR_NVM;
593 goto out;
594 }
595
596 for (i = 0; i < words; i++) {
597 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) +
598 E1000_NVM_RW_REG_START;
599
600 E1000_WRITE_REG(hw, E1000_EERD, eerd);
601 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
602 if (ret_val)
603 break;
604
605 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
606 E1000_NVM_RW_REG_DATA);
607 }
608
609 out:
610 return (ret_val);
611 }
612
613 /*
614 * e1000_write_nvm_spi - Write to EEPROM using SPI
615 * @hw: pointer to the HW structure
616 * @offset: offset within the EEPROM to be written to
617 * @words: number of words to write
618 * @data: 16 bit word(s) to be written to the EEPROM
619 *
620 * Writes data to EEPROM at offset using SPI interface.
621 *
622 * If e1000_update_nvm_checksum is not called after this function , the
623 * EEPROM will most likely contain an invalid checksum.
624 */
625 s32
e1000_write_nvm_spi(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)626 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
627 {
628 struct e1000_nvm_info *nvm = &hw->nvm;
629 s32 ret_val;
630 u16 widx = 0;
631
632 DEBUGFUNC("e1000_write_nvm_spi");
633
634 /*
635 * A check for invalid values: offset too large, too many words, and
636 * not enough words.
637 */
638 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
639 (words == 0)) {
640 DEBUGOUT("nvm parameter(s) out of bounds\n");
641 ret_val = -E1000_ERR_NVM;
642 goto out;
643 }
644
645 ret_val = nvm->ops.acquire(hw);
646 if (ret_val)
647 goto out;
648
649 while (widx < words) {
650 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
651
652 ret_val = e1000_ready_nvm_eeprom(hw);
653 if (ret_val)
654 goto release;
655
656 e1000_standby_nvm(hw);
657
658 /* Send the WRITE ENABLE command (8 bit opcode) */
659 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
660 nvm->opcode_bits);
661
662 e1000_standby_nvm(hw);
663
664 /*
665 * Some SPI eeproms use the 8th address bit embedded in the
666 * opcode
667 */
668 if ((nvm->address_bits == 8) && (offset >= 128))
669 write_opcode |= NVM_A8_OPCODE_SPI;
670
671 /* Send the Write command (8-bit opcode + addr) */
672 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
673 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
674 nvm->address_bits);
675
676 /* Loop to allow for up to whole page write of eeprom */
677 while (widx < words) {
678 u16 word_out = data[widx];
679
680 word_out = (word_out >> 8) | (word_out << 8);
681 e1000_shift_out_eec_bits(hw, word_out, 16);
682 widx++;
683
684 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
685 e1000_standby_nvm(hw);
686 break;
687 }
688 }
689 }
690
691 msec_delay(10);
692 release:
693 nvm->ops.release(hw);
694
695 out:
696 return (ret_val);
697 }
698
699 /*
700 * e1000_write_nvm_microwire - Writes EEPROM using microwire
701 * @hw: pointer to the HW structure
702 * @offset: offset within the EEPROM to be written to
703 * @words: number of words to write
704 * @data: 16 bit word(s) to be written to the EEPROM
705 *
706 * Writes data to EEPROM at offset using microwire interface.
707 *
708 * If e1000_update_nvm_checksum is not called after this function , the
709 * EEPROM will most likely contain an invalid checksum.
710 */
711 s32
e1000_write_nvm_microwire(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)712 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
713 {
714 struct e1000_nvm_info *nvm = &hw->nvm;
715 s32 ret_val;
716 u32 eecd;
717 u16 words_written = 0;
718 u16 widx = 0;
719
720 DEBUGFUNC("e1000_write_nvm_microwire");
721
722 /*
723 * A check for invalid values: offset too large, too many words, and
724 * not enough words.
725 */
726 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
727 (words == 0)) {
728 DEBUGOUT("nvm parameter(s) out of bounds\n");
729 ret_val = -E1000_ERR_NVM;
730 goto out;
731 }
732
733 ret_val = nvm->ops.acquire(hw);
734 if (ret_val)
735 goto out;
736
737 ret_val = e1000_ready_nvm_eeprom(hw);
738 if (ret_val)
739 goto release;
740
741 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
742 (u16)(nvm->opcode_bits + 2));
743
744 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
745
746 e1000_standby_nvm(hw);
747
748 while (words_written < words) {
749 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
750 nvm->opcode_bits);
751
752 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
753 nvm->address_bits);
754
755 e1000_shift_out_eec_bits(hw, data[words_written], 16);
756
757 e1000_standby_nvm(hw);
758
759 for (widx = 0; widx < 200; widx++) {
760 eecd = E1000_READ_REG(hw, E1000_EECD);
761 if (eecd & E1000_EECD_DO)
762 break;
763 usec_delay(50);
764 }
765
766 if (widx == 200) {
767 DEBUGOUT("NVM Write did not complete\n");
768 ret_val = -E1000_ERR_NVM;
769 goto release;
770 }
771
772 e1000_standby_nvm(hw);
773
774 words_written++;
775 }
776
777 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
778 (u16)(nvm->opcode_bits + 2));
779
780 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
781
782 release:
783 nvm->ops.release(hw);
784
785 out:
786 return (ret_val);
787 }
788
789 /*
790 * e1000_read_pba_num_generic - Read device part number
791 * @hw: pointer to the HW structure
792 * @pba_num: pointer to device part number
793 *
794 * Reads the product board assembly (PBA) number from the EEPROM and stores
795 * the value in pba_num.
796 */
797 s32
e1000_read_pba_num_generic(struct e1000_hw * hw,u32 * pba_num)798 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
799 {
800 s32 ret_val;
801 u16 nvm_data;
802
803 DEBUGFUNC("e1000_read_pba_num_generic");
804
805 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
806 if (ret_val) {
807 DEBUGOUT("NVM Read Error\n");
808 goto out;
809 }
810 *pba_num = (u32)(nvm_data << 16);
811
812 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
813 if (ret_val) {
814 DEBUGOUT("NVM Read Error\n");
815 goto out;
816 }
817 *pba_num |= nvm_data;
818
819 out:
820 return (ret_val);
821 }
822
823 /*
824 * e1000_read_mac_addr_generic - Read device MAC address
825 * @hw: pointer to the HW structure
826 *
827 * Reads the device MAC address from the EEPROM and stores the value.
828 * Since devices with two ports use the same EEPROM, we increment the
829 * last bit in the MAC address for the second port.
830 */
831 s32
e1000_read_mac_addr_generic(struct e1000_hw * hw)832 e1000_read_mac_addr_generic(struct e1000_hw *hw)
833 {
834 u32 rar_high;
835 u32 rar_low;
836 u16 i;
837
838 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
839 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
840
841 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
842 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
843
844 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
845 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
846
847 for (i = 0; i < ETH_ADDR_LEN; i++)
848 hw->mac.addr[i] = hw->mac.perm_addr[i];
849
850 return (E1000_SUCCESS);
851 }
852
853 /*
854 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
855 * @hw: pointer to the HW structure
856 *
857 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
858 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
859 */
860 s32
e1000_validate_nvm_checksum_generic(struct e1000_hw * hw)861 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
862 {
863 s32 ret_val = E1000_SUCCESS;
864 u16 checksum = 0;
865 u16 i, nvm_data;
866
867 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
868
869 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
870 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
871 if (ret_val) {
872 DEBUGOUT("NVM Read Error\n");
873 goto out;
874 }
875 checksum += nvm_data;
876 }
877
878 if (checksum != (u16)NVM_SUM) {
879 DEBUGOUT("NVM Checksum Invalid\n");
880 ret_val = -E1000_ERR_NVM;
881 goto out;
882 }
883
884 out:
885 return (ret_val);
886 }
887
888 /*
889 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
890 * @hw: pointer to the HW structure
891 *
892 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
893 * up to the checksum. Then calculates the EEPROM checksum and writes the
894 * value to the EEPROM.
895 */
896 s32
e1000_update_nvm_checksum_generic(struct e1000_hw * hw)897 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
898 {
899 s32 ret_val;
900 u16 checksum = 0;
901 u16 i, nvm_data;
902
903 DEBUGFUNC("e1000_update_nvm_checksum");
904
905 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
906 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
907 if (ret_val) {
908 DEBUGOUT("NVM Read Error while updating checksum.\n");
909 goto out;
910 }
911 checksum += nvm_data;
912 }
913 checksum = (u16)NVM_SUM - checksum;
914 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
915 if (ret_val) {
916 /* EMPTY */
917 DEBUGOUT("NVM Write Error while updating checksum.\n");
918 }
919
920 out:
921 return (ret_val);
922 }
923
924 /*
925 * e1000_reload_nvm_generic - Reloads EEPROM
926 * @hw: pointer to the HW structure
927 *
928 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
929 * extended control register.
930 */
931 void
e1000_reload_nvm_generic(struct e1000_hw * hw)932 e1000_reload_nvm_generic(struct e1000_hw *hw)
933 {
934 u32 ctrl_ext;
935
936 DEBUGFUNC("e1000_reload_nvm_generic");
937
938 usec_delay(10);
939 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
940 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
941 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
942 E1000_WRITE_FLUSH(hw);
943 }
944