1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * IntelVersion: 1.9 v3-1-10-1_2009-9-18_Release14-6 28 */ 29 #ifndef _E1000_82541_H_ 30 #define _E1000_82541_H_ 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1) 37 38 #define IGP01E1000_PHY_CHANNEL_NUM 4 39 40 #define IGP01E1000_PHY_AGC_A 0x1172 41 #define IGP01E1000_PHY_AGC_B 0x1272 42 #define IGP01E1000_PHY_AGC_C 0x1472 43 #define IGP01E1000_PHY_AGC_D 0x1872 44 45 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 46 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 47 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 48 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 49 50 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 51 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 52 53 #define IGP01E1000_PHY_DSP_RESET 0x1F33 54 55 #define IGP01E1000_PHY_DSP_FFE 0x1F35 56 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 57 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A 58 59 #define IGP01E1000_IEEE_FORCE_GIG 0x0140 60 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 61 62 #define IGP01E1000_AGC_LENGTH_SHIFT 7 63 #define IGP01E1000_AGC_RANGE 10 64 65 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 66 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 67 68 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 69 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 70 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC 71 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE 72 73 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 74 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 75 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 76 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 77 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 78 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 79 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 80 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 81 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 82 83 #define IGP01E1000_MSE_CHANNEL_D 0x000F 84 #define IGP01E1000_MSE_CHANNEL_C 0x00F0 85 #define IGP01E1000_MSE_CHANNEL_B 0x0F00 86 #define IGP01E1000_MSE_CHANNEL_A 0xF000 87 88 #define E1000_FIFO_MULTIPLIER 0x80 89 #define E1000_FIFO_HDR_SIZE 0x10 90 #define E1000_FIFO_GRANULARITY 0x10 91 #define E1000_FIFO_PAD_82547 0x3E0 92 #define E1000_ERR_FIFO_WRAP 8 93 94 #define DSP_RESET_ENABLE 0x0 95 #define DSP_RESET_DISABLE 0x2 96 #define E1000_MAX_DSP_RESETS 10 97 98 #define E1000_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 99 100 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state); 101 s32 e1000_fifo_workaround_82547(struct e1000_hw *hw, u16 length); 102 void e1000_update_tx_fifo_head_82547(struct e1000_hw *hw, u32 length); 103 void e1000_set_ttl_workaround_state_82541(struct e1000_hw *hw, bool state); 104 bool e1000_ttl_workaround_enabled_82541(struct e1000_hw *hw); 105 s32 e1000_igp_ttl_workaround_82547(struct e1000_hw *hw); 106 107 #ifdef __cplusplus 108 } 109 #endif 110 111 #endif /* _E1000_82541_H_ */ 112