1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _FP_H 28 #define _FP_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <stdio.h> 33 #include <strings.h> 34 #include <stdlib.h> 35 #include <libintl.h> 36 #include <sys/fsr.h> 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* Co-Processor Types */ 43 44 #define FABS 30 /* FABS */ 45 #define INVALID -1 /* Invalid device code */ 46 #define MC68881 20 /* Motorola family 68881 */ 47 #define MEIKO 100 /* Meiko LSIL L64804 */ 48 #define NONE 111 /* No FPU installed */ 49 #define SUNRAY_FPC 40 /* Sunray - uses the TI8847 */ 50 #define TI8847 10 /* TI family 8847 */ 51 #define WEITEK 0 /* Weitek family */ 52 #define WTL3170 11 /* Weitek WTL3170/2 */ 53 54 #define CPU_TYPE_SHIFT 24 /* bits to shift to get the cpu type */ 55 #define CPU_TYPE_MASK 0xff /* 1 byte indicates cpu type */ 56 57 /* True and False */ 58 59 #ifndef FALSE 60 #define FALSE 0 61 #endif 62 63 #ifndef TRUE 64 #define TRUE 1 65 #endif 66 67 /* Return Codes */ 68 69 #define FPU_UNSUPPORT -1 70 #define FPU_OK 0 71 #define FPU_FOROFFLINE 1 72 #define FPU_BIND_FAIL 2 73 #define FPU_INVALID_ARG 3 74 #define FPU_SIG_SEGV 4 75 #define FPU_SIG_BUS 5 76 #define FPU_SIG_FPE 6 77 #define FPU_SIG_ILL 7 78 #define FPU_SYSCALL_TRYAGAIN 8 79 #define FPU_SYSCALL_FAIL 9 80 #define FPU_EREPORT_INCOM 10 81 #define FPU_EREPORT_FAIL 11 82 83 /* Math constants */ 84 85 #define DPMARGIN 0.000000000000001 86 #define MARGIN 0.0000000010 87 #define pi 3.141592654 88 #define SPMARGIN 0.0000001 89 90 #define denorm_sp 0x00000001 91 #define denorm_lsw 0x00000001 92 #define denorm_msw 0x00000000 93 94 #define half_sp 0x3f000000 95 #define half_lsw 0x00000000 96 #define half_msw 0x3fe00000 97 98 #define maxn_lsw 0xffffffff 99 #define maxn_msw 0x7fefffff 100 #define maxn_sp 0x7f7fffff 101 102 #define nan_dp 0x7ff7ffffffffffff 103 #define nan_sp 0x7fbfffff 104 #define nan_lsw 0xffffffff 105 #define nan_msw 0x7ff7ffff 106 107 #define one_sp 0x3f800000 108 #define one_lsw 0x00000000 109 #define one_msw 0x3ff00000 110 111 #define two_sp 0x40000000 112 #define two_lsw 0x00000000 113 #define two_msw 0x40000000 114 115 #define zero_sp 0x00000000 116 #define zero_lsw 0x00000000 117 #define zero_msw 0x00000000 118 119 /* -1 */ 120 121 #define m_one_sp 0xbf800000 122 #define m_one_lsw 0x00000000 123 #define m_one_msw 0xbff00000 124 125 #define pi_dp 0x400921fb54442d18UL 126 #define pi_lsw 0x54442d18 127 #define pi_msw 0x400921fb 128 #define pi_sp 0x40490fdb 129 130 #define pi_4_sp 0x3f490fdb 131 #define pi_4_lsw 0x54442d18 132 #define pi_4_msw 0x3fe921fb 133 134 /* +infinity */ 135 136 #define p_inf_lsw 0x00000000 137 #define p_inf_msw 0x7ff00000 138 #define p_inf_sp 0x7f800000 139 140 /* -infinity */ 141 142 #define n_inf_lsw 0x00000000 143 #define n_inf_msw 0xfff00000 144 #define n_inf_sp 0xff800000 145 146 147 /* pow(2, -126). Smallest SP normalized number */ 148 #define minn_sp 0x00800000 149 150 /* pow(2, -1022). Smallest DP normalized number */ 151 #define minn_lsw 0x00000000 152 #define minn_msw 0x00100000 153 154 #define min1_lsw 0x00010001 155 #define min1_msw 0x00100001 156 #define min1_sp 0x00800001 157 158 #define maxd_lsw 0xffffffff 159 #define maxd_msw 0x000fffff 160 #define maxd_sp 0x007fffff 161 162 #define maxm_lsw 0x55554000 163 #define maxm_msw 0x7fd55555 164 #define maxm_sp 0x7eaaaa00 165 166 #define nn_lsw 0x00000000 167 #define nn_msw 0x7ff00080 168 #define nn_sp 0x7f800400 169 #define nocare 0 170 171 /* FP operations */ 172 173 #define op_add_sp 1 174 #define op_add_dp 2 175 #define op_div_sp 3 176 #define op_div_dp 4 177 #define op_div_dp_c2sp 5 /* After DP division, convert to SP */ 178 #define op_fxtos 6 179 #define op_sub_sp 7 180 #define op_sub_dp 8 181 #define op_mul_sp 9 182 #define op_mul_dp 10 183 #define op_fstod 11 184 #define op_fdtos 12 185 #define op_fsqrts 13 186 #define op_fsqrtd 14 187 188 struct testws { 189 190 unsigned long a_msw; 191 unsigned long a_lsw; 192 unsigned long b_msw; 193 unsigned long b_lsw; 194 unsigned long instr; 195 unsigned long fsr_tem0_ieee754_exc; 196 unsigned long fsr_tem1_ieee754_exc; 197 unsigned long ecode; 198 }; 199 200 /* The values of cexc and aexc when FSR.TEM = 0 */ 201 #define FSR_TEM0_NX (FSR_CEXC_NX | FSR_AEXC_NX) 202 #define FSR_TEM0_DZ (FSR_CEXC_DZ | FSR_AEXC_DZ) 203 #define FSR_TEM0_UF (FSR_CEXC_UF | FSR_AEXC_UF) 204 #define FSR_TEM0_OF (FSR_CEXC_OF | FSR_AEXC_OF) 205 #define FSR_TEM0_NV (FSR_CEXC_NV | FSR_AEXC_NV) 206 207 /* When FSR.TEM=1, the FSR.aexc field will be untouched */ 208 #define FSR_TEM1_NX FSR_CEXC_NX 209 #define FSR_TEM1_DZ FSR_CEXC_DZ 210 #define FSR_TEM1_UF FSR_CEXC_UF 211 #define FSR_TEM1_OF FSR_CEXC_OF 212 #define FSR_TEM1_NV FSR_CEXC_NV 213 214 /* 215 * To enable/disable TEM bits in FSR use the following flags Steps: 1. 216 * unsigned long val; 2. val=get_fsr(); 3-1. val = val | FSR_ENABLE_TEM_NV 217 * (for enabling) 3-2. val = val & FSR_DISABLE_TEM_NV (for disabling) 4. 218 * set_fsr(val); 219 */ 220 221 #define FSR_ENABLE_TEM_NX 0x800000 222 #define FSR_ENABLE_TEM_DZ 0x1000000 223 #define FSR_ENABLE_TEM_UF 0x2000000 224 #define FSR_ENABLE_TEM_OF 0x4000000 225 #define FSR_ENABLE_TEM_NV 0x8000000 226 #define FSR_ENABLE_TEM 0xF800000 227 228 #define FSR_DISABLE_TEM_NX 0xFFFFFFFFFF7FFFFF 229 #define FSR_DISABLE_TEM_DZ 0xFFFFFFFFFEFFFFFF 230 #define FSR_DISABLE_TEM_UF 0xFFFFFFFFFDFFFFFF 231 #define FSR_DISABLE_TEM_OF 0xFFFFFFFFFBFFFFFF 232 #define FSR_DISABLE_TEM_NV 0xFFFFFFFFF7FFFFFF 233 #define FSR_DISABLE_TEM 0xFFFFFFFFF07FFFFF 234 235 236 /* 237 * There is no TEM1 equivalent for these. That is because if 238 * trap is enabled, the NX bit will not be set. See Section 239 * 5.1.7.9 "FSR_current_exception (cexc)" in the SPARC V9 240 * Architecture Manual 241 */ 242 243 #define FSR_TEM0_UF_NX (FSR_TEM0_UF | FSR_TEM0_NX) 244 #define FSR_TEM0_OF_NX (FSR_TEM0_OF | FSR_TEM0_NX) 245 246 #define GSR_IM_ZERO 0xFFFFFFFFF7FFFFFF /* GSR.IM = 0 */ 247 248 /* Values for 'ecode' of 'struct testws' */ 249 250 #define E_NX 0 251 #define E_DZ 1 252 #define E_UF 2 253 #define E_OF 3 254 #define E_NV 4 255 #define E_UF_NX 5 256 #define E_OF_NX 6 257 258 #define SIGN_FLAG_SP 0x80000000 259 #define SIGN_FLAG_DP 0x8000000000000000 260 261 #define ZERO_SP 0x00000000 262 #define ZERO_DP 0x0000000000000000 263 #define PLUS_ZERO_SP 0x00000000 264 #define MINUS_ZERO_SP 0x80000000 265 #define PLUS_ZERO_DP 0x0000000000000000 266 #define MINUS_ZERO_DP 0x8000000000000000 267 #define PLUS_INF_SP 0x7F800000 268 #define MINUS_INF_SP 0xFF800000 269 #define PLUS_INF_DP 0x7FF0000000000000 270 #define MINUS_INF_DP 0xFFF0000000000000 271 272 #define ALLZEROES_DP 0x0000000000000000UL 273 #define ALLZEROES_SP 0x00000000U 274 #define ALLONES_DP 0xFFFFFFFFFFFFFFFFUL 275 #define ALLONES_SP 0xFFFFFFFFU 276 277 #define TRAP_SOLICITED 1 278 #define TRAP_UNSOLICITED 2 279 280 #ifdef __cplusplus 281 } 282 #endif 283 284 #endif /* _FP_H */ 285