1 /* $NetBSD: t_lwp_create.c,v 1.4 2021/08/22 20:18:39 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 2012 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * This code is partly based on code by Joel Sing <joel at sing.id.au>
31 */
32
33 #include <atf-c.h>
34 #include <lwp.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <ucontext.h>
38 #include <inttypes.h>
39 #include <errno.h>
40
41 #ifdef __alpha__
42 #include <machine/alpha_cpu.h>
43 #endif
44 #ifdef __amd64__
45 #include <machine/vmparam.h>
46 #include <machine/psl.h>
47 #endif
48 #ifdef __hppa__
49 #include <machine/psl.h>
50 #endif
51 #ifdef __i386__
52 #include <machine/segments.h>
53 #include <machine/psl.h>
54 #endif
55 #if defined(__m68k__) || defined(__sh3__) || defined __vax__
56 #include <machine/psl.h>
57 #endif
58
59 volatile lwpid_t the_lwp_id = 0;
60
lwp_main_func(void * arg)61 static void lwp_main_func(void* arg)
62 {
63 the_lwp_id = _lwp_self();
64 _lwp_exit();
65 }
66
67 /*
68 * Hard to document - see usage examples below.
69 */
70 #define INVALID_UCONTEXT(ARCH,NAME,DESC) \
71 static void ARCH##_##NAME(ucontext_t *); \
72 ATF_TC(lwp_create_##ARCH##_fail_##NAME); \
73 ATF_TC_HEAD(lwp_create_##ARCH##_fail_##NAME, tc) \
74 { \
75 atf_tc_set_md_var(tc, "descr", "verify rejection of invalid ucontext " \
76 "on " #ARCH " due to " DESC); \
77 } \
78 \
79 ATF_TC_BODY(lwp_create_##ARCH##_fail_##NAME, tc) \
80 { \
81 ucontext_t uc; \
82 lwpid_t lid; \
83 int error; \
84 \
85 getcontext(&uc); \
86 uc.uc_flags = _UC_CPU; \
87 ARCH##_##NAME(&uc); \
88 \
89 error = _lwp_create(&uc, 0, &lid); \
90 ATF_REQUIRE(error != 0 && errno == EINVAL); \
91 } \
92 static void ARCH##_##NAME(ucontext_t *uc) \
93 {
94
95
96 ATF_TC(lwp_create_works);
ATF_TC_HEAD(lwp_create_works,tc)97 ATF_TC_HEAD(lwp_create_works, tc)
98 {
99 atf_tc_set_md_var(tc, "descr", "Verify creation of a lwp and waiting"
100 " for it to finish");
101 }
102
ATF_TC_BODY(lwp_create_works,tc)103 ATF_TC_BODY(lwp_create_works, tc)
104 {
105 ucontext_t uc;
106 lwpid_t lid;
107 int error;
108 void *stack;
109 static const size_t ssize = 16*1024;
110
111 stack = malloc(ssize);
112 _lwp_makecontext(&uc, lwp_main_func, NULL, NULL, stack, ssize);
113
114 error = _lwp_create(&uc, 0, &lid);
115 ATF_REQUIRE(error == 0);
116
117 error = _lwp_wait(lid, NULL);
118 ATF_REQUIRE(error == 0);
119 ATF_REQUIRE(lid == the_lwp_id);
120 }
121
122 ATF_TC(lwp_create_bad_lid_ptr);
ATF_TC_HEAD(lwp_create_bad_lid_ptr,tc)123 ATF_TC_HEAD(lwp_create_bad_lid_ptr, tc)
124 {
125 atf_tc_set_md_var(tc, "descr",
126 "Verify _lwp_create() fails as expected with bad lid pointer");
127 }
128
ATF_TC_BODY(lwp_create_bad_lid_ptr,tc)129 ATF_TC_BODY(lwp_create_bad_lid_ptr, tc)
130 {
131 ucontext_t uc;
132 int error;
133 int serrno;
134 void *stack;
135 static const size_t ssize = 16*1024;
136
137 stack = malloc(ssize);
138 _lwp_makecontext(&uc, lwp_main_func, NULL, NULL, stack, ssize);
139
140 error = _lwp_create(&uc, 0, NULL);
141 serrno = errno;
142 ATF_REQUIRE(error == -1);
143 ATF_REQUIRE(serrno == EFAULT);
144 }
145
146 INVALID_UCONTEXT(generic, no_uc_cpu, "not setting cpu registers")
147 uc->uc_flags &= ~_UC_CPU;
148 }
149
150 #ifdef __alpha__
151 INVALID_UCONTEXT(alpha, pslset, "trying to clear the USERMODE flag")
152 uc->uc_mcontext.__gregs[_REG_PS] &= ~ALPHA_PSL_USERMODE;
153 }
154 INVALID_UCONTEXT(alpha, pslclr, "trying to set a 'must be zero' flag")
155 uc->uc_mcontext.__gregs[_REG_PS] |= ALPHA_PSL_IPL_HIGH;
156 }
157 #endif
158 #ifdef __amd64__
159 INVALID_UCONTEXT(amd64, untouchable_rflags, "forbidden rflags changed")
160 uc->uc_mcontext.__gregs[_REG_RFLAGS] |= PSL_MBZ;
161 }
162 /*
163 * XXX: add invalid GS/DS selector tests
164 */
165 INVALID_UCONTEXT(amd64, pc_too_high,
166 "instruction pointer outside userland address space")
167 uc->uc_mcontext.__gregs[_REG_RIP] = VM_MAXUSER_ADDRESS;
168 }
169 #endif
170 #ifdef __arm__
171 INVALID_UCONTEXT(arm, invalid_mode, "psr or r15 set to non-user-mode")
172 uc->uc_mcontext.__gregs[_REG_PC] |= 0x1f /*PSR_SYS32_MODE*/;
173 uc->uc_mcontext.__gregs[_REG_CPSR] |= 0x03 /*R15_MODE_SVC*/;
174 }
175 #endif
176 #ifdef __hppa__
177 INVALID_UCONTEXT(hppa, invalid_1, "set illegal bits in psw")
178 uc->uc_mcontext.__gregs[_REG_PSW] |= PSW_MBZ;
179 }
180 INVALID_UCONTEXT(hppa, invalid_0, "clear illegal bits in psw")
181 uc->uc_mcontext.__gregs[_REG_PSW] &= ~PSW_MBS;
182 }
183 #endif
184 #ifdef __i386__
185 INVALID_UCONTEXT(i386, untouchable_eflags, "changing forbidden eflags")
186 uc->uc_mcontext.__gregs[_REG_EFL] |= PSL_IOPL;
187 }
188 INVALID_UCONTEXT(i386, priv_escalation, "modifying privilege level")
189 uc->uc_mcontext.__gregs[_REG_CS] &= ~SEL_RPL;
190 }
191 #endif
192 #ifdef __m68k__
193 INVALID_UCONTEXT(m68k, invalid_ps_bits,
194 "setting forbidden bits in the ps register")
195 uc->uc_mcontext.__gregs[_REG_PS] |= (PSL_MBZ|PSL_IPL|PSL_S);
196 }
197 #endif
198 #ifdef __sh3__
199 INVALID_UCONTEXT(sh3, modify_userstatic,
200 "modifying illegal bits in the status register")
201 uc->uc_mcontext.__gregs[_REG_SR] |= PSL_MD;
202 }
203 #endif
204 #ifdef __sparc__
205 INVALID_UCONTEXT(sparc, pc_odd, "mis-aligned instruction pointer")
206 uc->uc_mcontext.__gregs[_REG_PC] = 0x100002;
207 }
208 INVALID_UCONTEXT(sparc, npc_odd, "mis-aligned next instruction pointer")
209 uc->uc_mcontext.__gregs[_REG_nPC] = 0x100002;
210 }
211 INVALID_UCONTEXT(sparc, pc_null, "NULL instruction pointer")
212 uc->uc_mcontext.__gregs[_REG_PC] = 0;
213 }
214 INVALID_UCONTEXT(sparc, npc_null, "NULL next instruction pointer")
215 uc->uc_mcontext.__gregs[_REG_nPC] = 0;
216 }
217 #endif
218 #ifdef __vax__
219 INVALID_UCONTEXT(vax, psl_0, "clearing forbidden bits in psl")
220 uc->uc_mcontext.__gregs[_REG_PSL] &= ~(PSL_U | PSL_PREVU);
221 }
222 INVALID_UCONTEXT(vax, psl_1, "setting forbidden bits in psl")
223 uc->uc_mcontext.__gregs[_REG_PSL] |= PSL_IPL | PSL_IS;
224 }
225 INVALID_UCONTEXT(vax, psl_cm, "setting CM bit in psl")
226 uc->uc_mcontext.__gregs[_REG_PSL] |= PSL_CM;
227 }
228 #endif
229
230 ATF_TP_ADD_TCS(tp)
231 {
232 ATF_TP_ADD_TC(tp, lwp_create_works);
233 ATF_TP_ADD_TC(tp, lwp_create_bad_lid_ptr);
234 ATF_TP_ADD_TC(tp, lwp_create_generic_fail_no_uc_cpu);
235 #ifdef __alpha__
236 ATF_TP_ADD_TC(tp, lwp_create_alpha_fail_pslset);
237 ATF_TP_ADD_TC(tp, lwp_create_alpha_fail_pslclr);
238 #endif
239 #ifdef __amd64__
240 ATF_TP_ADD_TC(tp, lwp_create_amd64_fail_untouchable_rflags);
241 ATF_TP_ADD_TC(tp, lwp_create_amd64_fail_pc_too_high);
242 #endif
243 #ifdef __arm__
244 ATF_TP_ADD_TC(tp, lwp_create_arm_fail_invalid_mode);
245 #endif
246 #ifdef __hppa__
247 ATF_TP_ADD_TC(tp, lwp_create_hppa_fail_invalid_1);
248 ATF_TP_ADD_TC(tp, lwp_create_hppa_fail_invalid_0);
249 #endif
250 #ifdef __i386__
251 ATF_TP_ADD_TC(tp, lwp_create_i386_fail_untouchable_eflags);
252 ATF_TP_ADD_TC(tp, lwp_create_i386_fail_priv_escalation);
253 #endif
254 #ifdef __m68k__
255 ATF_TP_ADD_TC(tp, lwp_create_m68k_fail_invalid_ps_bits);
256 #endif
257 #ifdef __sh3__
258 ATF_TP_ADD_TC(tp, lwp_create_sh3_fail_modify_userstatic);
259 #endif
260 #ifdef __sparc__
261 ATF_TP_ADD_TC(tp, lwp_create_sparc_fail_pc_odd);
262 ATF_TP_ADD_TC(tp, lwp_create_sparc_fail_npc_odd);
263 ATF_TP_ADD_TC(tp, lwp_create_sparc_fail_pc_null);
264 ATF_TP_ADD_TC(tp, lwp_create_sparc_fail_npc_null);
265 #endif
266 #ifdef __vax__
267 ATF_TP_ADD_TC(tp, lwp_create_vax_fail_psl_0);
268 ATF_TP_ADD_TC(tp, lwp_create_vax_fail_psl_1);
269 ATF_TP_ADD_TC(tp, lwp_create_vax_fail_psl_cm);
270 #endif
271 return atf_no_error();
272 }
273