1 /* $NetBSD: qcom,gcc-mdm9615.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 6 * Copyright (c) BayLibre, SAS. 7 * Author : Neil Armstrong <narmstrong@baylibre.com> 8 */ 9 10 #ifndef _DT_BINDINGS_RESET_GCC_MDM9615_H 11 #define _DT_BINDINGS_RESET_GCC_MDM9615_H 12 13 #define SFAB_MSS_Q6_SW_RESET 0 14 #define SFAB_MSS_Q6_FW_RESET 1 15 #define QDSS_STM_RESET 2 16 #define AFAB_SMPSS_S_RESET 3 17 #define AFAB_SMPSS_M1_RESET 4 18 #define AFAB_SMPSS_M0_RESET 5 19 #define AFAB_EBI1_CH0_RESET 6 20 #define AFAB_EBI1_CH1_RESET 7 21 #define SFAB_ADM0_M0_RESET 8 22 #define SFAB_ADM0_M1_RESET 9 23 #define SFAB_ADM0_M2_RESET 10 24 #define ADM0_C2_RESET 11 25 #define ADM0_C1_RESET 12 26 #define ADM0_C0_RESET 13 27 #define ADM0_PBUS_RESET 14 28 #define ADM0_RESET 15 29 #define QDSS_CLKS_SW_RESET 16 30 #define QDSS_POR_RESET 17 31 #define QDSS_TSCTR_RESET 18 32 #define QDSS_HRESET_RESET 19 33 #define QDSS_AXI_RESET 20 34 #define QDSS_DBG_RESET 21 35 #define PCIE_A_RESET 22 36 #define PCIE_AUX_RESET 23 37 #define PCIE_H_RESET 24 38 #define SFAB_PCIE_M_RESET 25 39 #define SFAB_PCIE_S_RESET 26 40 #define SFAB_MSS_M_RESET 27 41 #define SFAB_USB3_M_RESET 28 42 #define SFAB_RIVA_M_RESET 29 43 #define SFAB_LPASS_RESET 30 44 #define SFAB_AFAB_M_RESET 31 45 #define AFAB_SFAB_M0_RESET 32 46 #define AFAB_SFAB_M1_RESET 33 47 #define SFAB_SATA_S_RESET 34 48 #define SFAB_DFAB_M_RESET 35 49 #define DFAB_SFAB_M_RESET 36 50 #define DFAB_SWAY0_RESET 37 51 #define DFAB_SWAY1_RESET 38 52 #define DFAB_ARB0_RESET 39 53 #define DFAB_ARB1_RESET 40 54 #define PPSS_PROC_RESET 41 55 #define PPSS_RESET 42 56 #define DMA_BAM_RESET 43 57 #define SPS_TIC_H_RESET 44 58 #define SLIMBUS_H_RESET 45 59 #define SFAB_CFPB_M_RESET 46 60 #define SFAB_CFPB_S_RESET 47 61 #define TSIF_H_RESET 48 62 #define CE1_H_RESET 49 63 #define CE1_CORE_RESET 50 64 #define CE1_SLEEP_RESET 51 65 #define CE2_H_RESET 52 66 #define CE2_CORE_RESET 53 67 #define SFAB_SFPB_M_RESET 54 68 #define SFAB_SFPB_S_RESET 55 69 #define RPM_PROC_RESET 56 70 #define PMIC_SSBI2_RESET 57 71 #define SDC1_RESET 58 72 #define SDC2_RESET 59 73 #define SDC3_RESET 60 74 #define SDC4_RESET 61 75 #define SDC5_RESET 62 76 #define DFAB_A2_RESET 63 77 #define USB_HS1_RESET 64 78 #define USB_HSIC_RESET 65 79 #define USB_FS1_XCVR_RESET 66 80 #define USB_FS1_RESET 67 81 #define USB_FS2_XCVR_RESET 68 82 #define USB_FS2_RESET 69 83 #define GSBI1_RESET 70 84 #define GSBI2_RESET 71 85 #define GSBI3_RESET 72 86 #define GSBI4_RESET 73 87 #define GSBI5_RESET 74 88 #define GSBI6_RESET 75 89 #define GSBI7_RESET 76 90 #define GSBI8_RESET 77 91 #define GSBI9_RESET 78 92 #define GSBI10_RESET 79 93 #define GSBI11_RESET 80 94 #define GSBI12_RESET 81 95 #define SPDM_RESET 82 96 #define TLMM_H_RESET 83 97 #define SFAB_MSS_S_RESET 84 98 #define MSS_SLP_RESET 85 99 #define MSS_Q6SW_JTAG_RESET 86 100 #define MSS_Q6FW_JTAG_RESET 87 101 #define MSS_RESET 88 102 #define SATA_H_RESET 89 103 #define SATA_RXOOB_RESE 90 104 #define SATA_PMALIVE_RESET 91 105 #define SATA_SFAB_M_RESET 92 106 #define TSSC_RESET 93 107 #define PDM_RESET 94 108 #define MPM_H_RESET 95 109 #define MPM_RESET 96 110 #define SFAB_SMPSS_S_RESET 97 111 #define PRNG_RESET 98 112 #define RIVA_RESET 99 113 #define USB_HS3_RESET 100 114 #define USB_HS4_RESET 101 115 #define CE3_RESET 102 116 #define PCIE_EXT_PCI_RESET 103 117 #define PCIE_PHY_RESET 104 118 #define PCIE_PCI_RESET 105 119 #define PCIE_POR_RESET 106 120 #define PCIE_HCLK_RESET 107 121 #define PCIE_ACLK_RESET 108 122 #define CE3_H_RESET 109 123 #define SFAB_CE3_M_RESET 110 124 #define SFAB_CE3_S_RESET 111 125 #define SATA_RESET 112 126 #define CE3_SLEEP_RESET 113 127 #define GSS_SLP_RESET 114 128 #define GSS_RESET 115 129 130 #endif 131