1 /* $NetBSD: mt8195-resets.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ 4 /* 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Christine Zhu <christine.zhu@mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 10 #define _DT_BINDINGS_RESET_CONTROLLER_MT8195 11 12 #define MT8195_TOPRGU_CONN_MCU_SW_RST 0 13 #define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 14 #define MT8195_TOPRGU_APU_SW_RST 2 15 #define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 16 #define MT8195_TOPRGU_MMSYS_SW_RST 7 17 #define MT8195_TOPRGU_MFG_SW_RST 8 18 #define MT8195_TOPRGU_VENC_SW_RST 9 19 #define MT8195_TOPRGU_VDEC_SW_RST 10 20 #define MT8195_TOPRGU_IMG_SW_RST 11 21 #define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 22 #define MT8195_TOPRGU_AUDIO_SW_RST 14 23 #define MT8195_TOPRGU_CAMSYS_SW_RST 15 24 #define MT8195_TOPRGU_EDPTX_SW_RST 16 25 #define MT8195_TOPRGU_ADSPSYS_SW_RST 21 26 #define MT8195_TOPRGU_DPTX_SW_RST 22 27 #define MT8195_TOPRGU_SPMI_MST_SW_RST 23 28 29 #define MT8195_TOPRGU_SW_RST_NUM 16 30 31 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ 32