1 /* $NetBSD: mt8135-resets.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2014 MediaTek Inc. 6 * Author: Flora Fu, MediaTek 7 */ 8 9 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 10 #define _DT_BINDINGS_RESET_CONTROLLER_MT8135 11 12 /* INFRACFG resets */ 13 #define MT8135_INFRA_EMI_REG_RST 0 14 #define MT8135_INFRA_DRAMC0_A0_RST 1 15 #define MT8135_INFRA_CCIF0_RST 2 16 #define MT8135_INFRA_APCIRQ_EINT_RST 3 17 #define MT8135_INFRA_APXGPT_RST 4 18 #define MT8135_INFRA_SCPSYS_RST 5 19 #define MT8135_INFRA_CCIF1_RST 6 20 #define MT8135_INFRA_PMIC_WRAP_RST 7 21 #define MT8135_INFRA_KP_RST 8 22 #define MT8135_INFRA_EMI_RST 32 23 #define MT8135_INFRA_DRAMC0_RST 34 24 #define MT8135_INFRA_SMI_RST 35 25 #define MT8135_INFRA_M4U_RST 36 26 27 /* PERICFG resets */ 28 #define MT8135_PERI_UART0_SW_RST 0 29 #define MT8135_PERI_UART1_SW_RST 1 30 #define MT8135_PERI_UART2_SW_RST 2 31 #define MT8135_PERI_UART3_SW_RST 3 32 #define MT8135_PERI_IRDA_SW_RST 4 33 #define MT8135_PERI_PTP_SW_RST 5 34 #define MT8135_PERI_AP_HIF_SW_RST 6 35 #define MT8135_PERI_GPCU_SW_RST 7 36 #define MT8135_PERI_MD_HIF_SW_RST 8 37 #define MT8135_PERI_NLI_SW_RST 9 38 #define MT8135_PERI_AUXADC_SW_RST 10 39 #define MT8135_PERI_DMA_SW_RST 11 40 #define MT8135_PERI_NFI_SW_RST 14 41 #define MT8135_PERI_PWM_SW_RST 15 42 #define MT8135_PERI_THERM_SW_RST 16 43 #define MT8135_PERI_MSDC0_SW_RST 17 44 #define MT8135_PERI_MSDC1_SW_RST 18 45 #define MT8135_PERI_MSDC2_SW_RST 19 46 #define MT8135_PERI_MSDC3_SW_RST 20 47 #define MT8135_PERI_I2C0_SW_RST 22 48 #define MT8135_PERI_I2C1_SW_RST 23 49 #define MT8135_PERI_I2C2_SW_RST 24 50 #define MT8135_PERI_I2C3_SW_RST 25 51 #define MT8135_PERI_I2C4_SW_RST 26 52 #define MT8135_PERI_I2C5_SW_RST 27 53 #define MT8135_PERI_I2C6_SW_RST 28 54 #define MT8135_PERI_USB_SW_RST 29 55 #define MT8135_PERI_SPI1_SW_RST 33 56 #define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 57 58 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ 59