1 /* $NetBSD: mt7622-reset.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Sean Wang <sean.wang@mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622 10 #define _DT_BINDINGS_RESET_CONTROLLER_MT7622 11 12 /* INFRACFG resets */ 13 #define MT7622_INFRA_EMI_REG_RST 0 14 #define MT7622_INFRA_DRAMC0_A0_RST 1 15 #define MT7622_INFRA_APCIRQ_EINT_RST 3 16 #define MT7622_INFRA_APXGPT_RST 4 17 #define MT7622_INFRA_SCPSYS_RST 5 18 #define MT7622_INFRA_PMIC_WRAP_RST 7 19 #define MT7622_INFRA_IRRX_RST 9 20 #define MT7622_INFRA_EMI_RST 16 21 #define MT7622_INFRA_WED0_RST 17 22 #define MT7622_INFRA_DRAMC_RST 18 23 #define MT7622_INFRA_CCI_INTF_RST 19 24 #define MT7622_INFRA_TRNG_RST 21 25 #define MT7622_INFRA_SYSIRQ_RST 22 26 #define MT7622_INFRA_WED1_RST 25 27 28 /* PERICFG Subsystem resets */ 29 #define MT7622_PERI_UART0_SW_RST 0 30 #define MT7622_PERI_UART1_SW_RST 1 31 #define MT7622_PERI_UART2_SW_RST 2 32 #define MT7622_PERI_UART3_SW_RST 3 33 #define MT7622_PERI_UART4_SW_RST 4 34 #define MT7622_PERI_BTIF_SW_RST 6 35 #define MT7622_PERI_PWM_SW_RST 8 36 #define MT7622_PERI_AUXADC_SW_RST 10 37 #define MT7622_PERI_DMA_SW_RST 11 38 #define MT7622_PERI_IRTX_SW_RST 13 39 #define MT7622_PERI_NFI_SW_RST 14 40 #define MT7622_PERI_THERM_SW_RST 16 41 #define MT7622_PERI_MSDC0_SW_RST 19 42 #define MT7622_PERI_MSDC1_SW_RST 20 43 #define MT7622_PERI_I2C0_SW_RST 22 44 #define MT7622_PERI_I2C1_SW_RST 23 45 #define MT7622_PERI_I2C2_SW_RST 24 46 #define MT7622_PERI_SPI0_SW_RST 33 47 #define MT7622_PERI_SPI1_SW_RST 34 48 #define MT7622_PERI_FLASHIF_SW_RST 36 49 50 /* TOPRGU resets */ 51 #define MT7622_TOPRGU_INFRA_RST 0 52 #define MT7622_TOPRGU_ETHDMA_RST 1 53 #define MT7622_TOPRGU_DDRPHY_RST 6 54 #define MT7622_TOPRGU_INFRA_AO_RST 8 55 #define MT7622_TOPRGU_CONN_RST 9 56 #define MT7622_TOPRGU_APMIXED_RST 10 57 #define MT7622_TOPRGU_CONN_MCU_RST 12 58 59 /* PCIe/SATA Subsystem resets */ 60 #define MT7622_SATA_PHY_REG_RST 12 61 #define MT7622_SATA_PHY_SW_RST 13 62 #define MT7622_SATA_AXI_BUS_RST 15 63 #define MT7622_PCIE1_CORE_RST 19 64 #define MT7622_PCIE1_MMIO_RST 20 65 #define MT7622_PCIE1_HRST 21 66 #define MT7622_PCIE1_USER_RST 22 67 #define MT7622_PCIE1_PIPE_RST 23 68 #define MT7622_PCIE0_CORE_RST 27 69 #define MT7622_PCIE0_MMIO_RST 28 70 #define MT7622_PCIE0_HRST 29 71 #define MT7622_PCIE0_USER_RST 30 72 #define MT7622_PCIE0_PIPE_RST 31 73 74 /* SSUSB Subsystem resets */ 75 #define MT7622_SSUSB_PHY_PWR_RST 3 76 #define MT7622_SSUSB_MAC_PWR_RST 4 77 78 /* ETHSYS Subsystem resets */ 79 #define MT7622_ETHSYS_SYS_RST 0 80 #define MT7622_ETHSYS_MCM_RST 2 81 #define MT7622_ETHSYS_HSDMA_RST 5 82 #define MT7622_ETHSYS_FE_RST 6 83 #define MT7622_ETHSYS_GMAC_RST 23 84 #define MT7622_ETHSYS_EPHY_RST 24 85 #define MT7622_ETHSYS_CRYPTO_RST 29 86 #define MT7622_ETHSYS_PPE_RST 31 87 88 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */ 89