1 /* $NetBSD: mt2701-resets.h,v 1.1.1.4 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com> 6 */ 7 8 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701 9 #define _DT_BINDINGS_RESET_CONTROLLER_MT2701 10 11 /* INFRACFG resets */ 12 #define MT2701_INFRA_EMI_REG_RST 0 13 #define MT2701_INFRA_DRAMC0_A0_RST 1 14 #define MT2701_INFRA_FHCTL_RST 2 15 #define MT2701_INFRA_APCIRQ_EINT_RST 3 16 #define MT2701_INFRA_APXGPT_RST 4 17 #define MT2701_INFRA_SCPSYS_RST 5 18 #define MT2701_INFRA_KP_RST 6 19 #define MT2701_INFRA_PMIC_WRAP_RST 7 20 #define MT2701_INFRA_MIPI_RST 8 21 #define MT2701_INFRA_IRRX_RST 9 22 #define MT2701_INFRA_CEC_RST 10 23 #define MT2701_INFRA_EMI_RST 32 24 #define MT2701_INFRA_DRAMC0_RST 34 25 #define MT2701_INFRA_TRNG_RST 37 26 #define MT2701_INFRA_SYSIRQ_RST 38 27 28 /* PERICFG resets */ 29 #define MT2701_PERI_UART0_SW_RST 0 30 #define MT2701_PERI_UART1_SW_RST 1 31 #define MT2701_PERI_UART2_SW_RST 2 32 #define MT2701_PERI_UART3_SW_RST 3 33 #define MT2701_PERI_GCPU_SW_RST 5 34 #define MT2701_PERI_BTIF_SW_RST 6 35 #define MT2701_PERI_PWM_SW_RST 8 36 #define MT2701_PERI_AUXADC_SW_RST 10 37 #define MT2701_PERI_DMA_SW_RST 11 38 #define MT2701_PERI_NFI_SW_RST 14 39 #define MT2701_PERI_NLI_SW_RST 15 40 #define MT2701_PERI_THERM_SW_RST 16 41 #define MT2701_PERI_MSDC2_SW_RST 17 42 #define MT2701_PERI_MSDC0_SW_RST 19 43 #define MT2701_PERI_MSDC1_SW_RST 20 44 #define MT2701_PERI_I2C0_SW_RST 22 45 #define MT2701_PERI_I2C1_SW_RST 23 46 #define MT2701_PERI_I2C2_SW_RST 24 47 #define MT2701_PERI_I2C3_SW_RST 25 48 #define MT2701_PERI_USB_SW_RST 28 49 #define MT2701_PERI_ETH_SW_RST 29 50 #define MT2701_PERI_SPI0_SW_RST 33 51 52 /* TOPRGU resets */ 53 #define MT2701_TOPRGU_INFRA_RST 0 54 #define MT2701_TOPRGU_MM_RST 1 55 #define MT2701_TOPRGU_MFG_RST 2 56 #define MT2701_TOPRGU_ETHDMA_RST 3 57 #define MT2701_TOPRGU_VDEC_RST 4 58 #define MT2701_TOPRGU_VENC_IMG_RST 5 59 #define MT2701_TOPRGU_DDRPHY_RST 6 60 #define MT2701_TOPRGU_MD_RST 7 61 #define MT2701_TOPRGU_INFRA_AO_RST 8 62 #define MT2701_TOPRGU_CONN_RST 9 63 #define MT2701_TOPRGU_APMIXED_RST 10 64 #define MT2701_TOPRGU_HIFSYS_RST 11 65 #define MT2701_TOPRGU_CONN_MCU_RST 12 66 #define MT2701_TOPRGU_BDP_DISP_RST 13 67 68 /* HIFSYS resets */ 69 #define MT2701_HIFSYS_UHOST0_RST 3 70 #define MT2701_HIFSYS_UHOST1_RST 4 71 #define MT2701_HIFSYS_UPHY0_RST 21 72 #define MT2701_HIFSYS_UPHY1_RST 22 73 #define MT2701_HIFSYS_PCIE0_RST 24 74 #define MT2701_HIFSYS_PCIE1_RST 25 75 #define MT2701_HIFSYS_PCIE2_RST 26 76 77 /* ETHSYS resets */ 78 #define MT2701_ETHSYS_SYS_RST 0 79 #define MT2701_ETHSYS_MCM_RST 2 80 #define MT2701_ETHSYS_FE_RST 6 81 #define MT2701_ETHSYS_GMAC_RST 23 82 #define MT2701_ETHSYS_PPE_RST 31 83 84 /* G3DSYS resets */ 85 #define MT2701_G3DSYS_CORE_RST 0 86 87 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ 88