1 /* $NetBSD: amlogic,meson-a1-reset.h,v 1.1.1.1 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * 5 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 6 * Author: Xingyu Chen <xingyu.chen@amlogic.com> 7 * 8 */ 9 10 #ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H 11 #define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H 12 13 /* RESET0 */ 14 /* 0 */ 15 #define RESET_AM2AXI_VAD 1 16 /* 2-3 */ 17 #define RESET_PSRAM 4 18 #define RESET_PAD_CTRL 5 19 /* 6 */ 20 #define RESET_TEMP_SENSOR 7 21 #define RESET_AM2AXI_DEV 8 22 /* 9 */ 23 #define RESET_SPICC_A 10 24 #define RESET_MSR_CLK 11 25 #define RESET_AUDIO 12 26 #define RESET_ANALOG_CTRL 13 27 #define RESET_SAR_ADC 14 28 #define RESET_AUDIO_VAD 15 29 #define RESET_CEC 16 30 #define RESET_PWM_EF 17 31 #define RESET_PWM_CD 18 32 #define RESET_PWM_AB 19 33 /* 20 */ 34 #define RESET_IR_CTRL 21 35 #define RESET_I2C_S_A 22 36 /* 23 */ 37 #define RESET_I2C_M_D 24 38 #define RESET_I2C_M_C 25 39 #define RESET_I2C_M_B 26 40 #define RESET_I2C_M_A 27 41 #define RESET_I2C_PROD_AHB 28 42 #define RESET_I2C_PROD 29 43 /* 30-31 */ 44 45 /* RESET1 */ 46 #define RESET_ACODEC 32 47 #define RESET_DMA 33 48 #define RESET_SD_EMMC_A 34 49 /* 35 */ 50 #define RESET_USBCTRL 36 51 /* 37 */ 52 #define RESET_USBPHY 38 53 /* 39-41 */ 54 #define RESET_RSA 42 55 #define RESET_DMC 43 56 /* 44 */ 57 #define RESET_IRQ_CTRL 45 58 /* 46 */ 59 #define RESET_NIC_VAD 47 60 #define RESET_NIC_AXI 48 61 #define RESET_RAMA 49 62 #define RESET_RAMB 50 63 /* 51-52 */ 64 #define RESET_ROM 53 65 #define RESET_SPIFC 54 66 #define RESET_GIC 55 67 #define RESET_UART_C 56 68 #define RESET_UART_B 57 69 #define RESET_UART_A 58 70 #define RESET_OSC_RING 59 71 /* 60-63 */ 72 73 /* RESET2 */ 74 /* 64-95 */ 75 76 #endif 77