1 /* $NetBSD: altr,rst-mgr-s10.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (C) 2016 Intel Corporation. All rights reserved 6 * Copyright (C) 2016 Altera Corporation. All rights reserved 7 * 8 * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" 9 */ 10 11 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 12 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 13 14 /* MPUMODRST */ 15 #define CPU0_RESET 0 16 #define CPU1_RESET 1 17 #define CPU2_RESET 2 18 #define CPU3_RESET 3 19 20 /* PER0MODRST */ 21 #define EMAC0_RESET 32 22 #define EMAC1_RESET 33 23 #define EMAC2_RESET 34 24 #define USB0_RESET 35 25 #define USB1_RESET 36 26 #define NAND_RESET 37 27 /* 38 is empty */ 28 #define SDMMC_RESET 39 29 #define EMAC0_OCP_RESET 40 30 #define EMAC1_OCP_RESET 41 31 #define EMAC2_OCP_RESET 42 32 #define USB0_OCP_RESET 43 33 #define USB1_OCP_RESET 44 34 #define NAND_OCP_RESET 45 35 /* 46 is empty */ 36 #define SDMMC_OCP_RESET 47 37 #define DMA_RESET 48 38 #define SPIM0_RESET 49 39 #define SPIM1_RESET 50 40 #define SPIS0_RESET 51 41 #define SPIS1_RESET 52 42 #define DMA_OCP_RESET 53 43 #define EMAC_PTP_RESET 54 44 /* 55 is empty*/ 45 #define DMAIF0_RESET 56 46 #define DMAIF1_RESET 57 47 #define DMAIF2_RESET 58 48 #define DMAIF3_RESET 59 49 #define DMAIF4_RESET 60 50 #define DMAIF5_RESET 61 51 #define DMAIF6_RESET 62 52 #define DMAIF7_RESET 63 53 54 /* PER1MODRST */ 55 #define WATCHDOG0_RESET 64 56 #define WATCHDOG1_RESET 65 57 #define WATCHDOG2_RESET 66 58 #define WATCHDOG3_RESET 67 59 #define L4SYSTIMER0_RESET 68 60 #define L4SYSTIMER1_RESET 69 61 #define SPTIMER0_RESET 70 62 #define SPTIMER1_RESET 71 63 #define I2C0_RESET 72 64 #define I2C1_RESET 73 65 #define I2C2_RESET 74 66 #define I2C3_RESET 75 67 #define I2C4_RESET 76 68 /* 77-79 is empty */ 69 #define UART0_RESET 80 70 #define UART1_RESET 81 71 /* 82-87 is empty */ 72 #define GPIO0_RESET 88 73 #define GPIO1_RESET 89 74 75 /* BRGMODRST */ 76 #define SOC2FPGA_RESET 96 77 #define LWHPS2FPGA_RESET 97 78 #define FPGA2SOC_RESET 98 79 #define F2SSDRAM0_RESET 99 80 #define F2SSDRAM1_RESET 100 81 #define F2SSDRAM2_RESET 101 82 #define DDRSCH_RESET 102 83 84 /* COLDMODRST */ 85 #define CPUPO0_RESET 160 86 #define CPUPO1_RESET 161 87 #define CPUPO2_RESET 162 88 #define CPUPO3_RESET 163 89 /* 164-167 is empty */ 90 #define L2_RESET 168 91 92 /* DBGMODRST */ 93 #define DBG_RESET 224 94 #define CSDAP_RESET 225 95 96 /* TAPMODRST */ 97 #define TAP_RESET 256 98 99 #endif 100