1 /* $NetBSD: rzn1-pinctrl.h,v 1.1.1.1 2019/01/22 14:57:01 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Defines macros and constants for Renesas RZ/N1 pin controller pin 6 * muxing functions. 7 */ 8 #ifndef __DT_BINDINGS_RZN1_PINCTRL_H 9 #define __DT_BINDINGS_RZN1_PINCTRL_H 10 11 #define RZN1_PINMUX(_gpio, _func) \ 12 (((_func) << 8) | (_gpio)) 13 14 /* 15 * Given the different levels of muxing on the SoC, it was decided to 16 * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO 17 * muxes are all represented by one single value. 18 * 19 * You can derive the hardware value pretty easily too, as 20 * 0...9 are Level 1 21 * 10...71 are Level 2. The Level 2 mux will be set to this 22 * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be 23 * set accordingly. 24 * 72...103 are for the 2 MDIO muxes. 25 */ 26 #define RZN1_FUNC_HIGHZ 0 27 #define RZN1_FUNC_0L 1 28 #define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 29 #define RZN1_FUNC_CLK_ETH_NAND 3 30 #define RZN1_FUNC_QSPI 4 31 #define RZN1_FUNC_SDIO 5 32 #define RZN1_FUNC_LCD 6 33 #define RZN1_FUNC_LCD_E 7 34 #define RZN1_FUNC_MSEBIM 8 35 #define RZN1_FUNC_MSEBIS 9 36 #define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ 37 38 #define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) 39 #define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) 40 #define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) 41 #define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) 42 #define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) 43 #define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) 44 #define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) 45 #define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) 46 #define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) 47 #define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) 48 #define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) 49 #define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) 50 #define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) 51 #define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) 52 #define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) 53 #define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) 54 #define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) 55 #define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) 56 #define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) 57 #define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) 58 #define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) 59 #define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) 60 #define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) 61 #define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) 62 #define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) 63 #define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) 64 #define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) 65 #define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) 66 #define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) 67 #define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) 68 #define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) 69 #define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) 70 #define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) 71 #define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) 72 #define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) 73 #define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) 74 #define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) 75 #define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) 76 #define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) 77 #define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) 78 #define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) 79 #define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) 80 #define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) 81 #define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) 82 #define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) 83 #define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) 84 #define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) 85 #define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) 86 #define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) 87 #define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) 88 #define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) 89 #define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) 90 #define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) 91 #define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) 92 #define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) 93 #define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) 94 #define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) 95 #define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) 96 #define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) 97 #define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) 98 #define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) 99 #define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) 100 101 #define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) 102 103 /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ 104 #define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) 105 #define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) 106 #define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) 107 #define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) 108 #define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) 109 #define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) 110 #define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) 111 #define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) 112 /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ 113 #define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) 114 #define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) 115 #define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) 116 #define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) 117 #define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) 118 #define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) 119 #define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) 120 #define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) 121 122 /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ 123 #define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) 124 #define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) 125 #define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) 126 #define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) 127 #define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) 128 #define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) 129 #define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) 130 #define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) 131 /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ 132 #define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) 133 #define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) 134 #define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) 135 #define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) 136 #define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) 137 #define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) 138 #define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) 139 #define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) 140 141 #define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) 142 143 #endif /* __DT_BINDINGS_RZN1_PINCTRL_H */ 144