1 /* $NetBSD: tegra124-mc.h,v 1.1.1.3 2018/06/27 16:27:08 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 #ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H 5 #define DT_BINDINGS_MEMORY_TEGRA124_MC_H 6 7 #define TEGRA_SWGROUP_PTC 0 8 #define TEGRA_SWGROUP_DC 1 9 #define TEGRA_SWGROUP_DCB 2 10 #define TEGRA_SWGROUP_AFI 3 11 #define TEGRA_SWGROUP_AVPC 4 12 #define TEGRA_SWGROUP_HDA 5 13 #define TEGRA_SWGROUP_HC 6 14 #define TEGRA_SWGROUP_MSENC 7 15 #define TEGRA_SWGROUP_PPCS 8 16 #define TEGRA_SWGROUP_SATA 9 17 #define TEGRA_SWGROUP_VDE 10 18 #define TEGRA_SWGROUP_MPCORELP 11 19 #define TEGRA_SWGROUP_MPCORE 12 20 #define TEGRA_SWGROUP_ISP2 13 21 #define TEGRA_SWGROUP_XUSB_HOST 14 22 #define TEGRA_SWGROUP_XUSB_DEV 15 23 #define TEGRA_SWGROUP_ISP2B 16 24 #define TEGRA_SWGROUP_TSEC 17 25 #define TEGRA_SWGROUP_A9AVP 18 26 #define TEGRA_SWGROUP_GPU 19 27 #define TEGRA_SWGROUP_SDMMC1A 20 28 #define TEGRA_SWGROUP_SDMMC2A 21 29 #define TEGRA_SWGROUP_SDMMC3A 22 30 #define TEGRA_SWGROUP_SDMMC4A 23 31 #define TEGRA_SWGROUP_VIC 24 32 #define TEGRA_SWGROUP_VI 25 33 34 #define TEGRA124_MC_RESET_AFI 0 35 #define TEGRA124_MC_RESET_AVPC 1 36 #define TEGRA124_MC_RESET_DC 2 37 #define TEGRA124_MC_RESET_DCB 3 38 #define TEGRA124_MC_RESET_HC 4 39 #define TEGRA124_MC_RESET_HDA 5 40 #define TEGRA124_MC_RESET_ISP2 6 41 #define TEGRA124_MC_RESET_MPCORE 7 42 #define TEGRA124_MC_RESET_MPCORELP 8 43 #define TEGRA124_MC_RESET_MSENC 9 44 #define TEGRA124_MC_RESET_PPCS 10 45 #define TEGRA124_MC_RESET_SATA 11 46 #define TEGRA124_MC_RESET_VDE 12 47 #define TEGRA124_MC_RESET_VI 13 48 #define TEGRA124_MC_RESET_VIC 14 49 #define TEGRA124_MC_RESET_XUSB_HOST 15 50 #define TEGRA124_MC_RESET_XUSB_DEV 16 51 #define TEGRA124_MC_RESET_TSEC 17 52 #define TEGRA124_MC_RESET_SDMMC1 18 53 #define TEGRA124_MC_RESET_SDMMC2 19 54 #define TEGRA124_MC_RESET_SDMMC3 20 55 #define TEGRA124_MC_RESET_SDMMC4 21 56 #define TEGRA124_MC_RESET_ISP2B 22 57 #define TEGRA124_MC_RESET_GPU 23 58 59 #endif 60