1 /* $NetBSD: mt8192-larb-port.h,v 1.1.1.1 2021/11/07 16:49:56 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2020 MediaTek Inc. 6 * 7 * Author: Chao Hao <chao.hao@mediatek.com> 8 * Author: Yong Wu <yong.wu@mediatek.com> 9 */ 10 #ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ 11 #define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ 12 13 #include <dt-bindings/memory/mtk-memory-port.h> 14 15 /* 16 * MM IOMMU supports 16GB dma address. 17 * 18 * The address will preassign like this: 19 * 20 * modules dma-address-region larbs-ports 21 * disp 0 ~ 4G larb0/1 22 * vcodec 4G ~ 8G larb4/5/7 23 * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 24 * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 25 * CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 26 * 27 * larb3/6/8/10/12/15 is null. 28 */ 29 30 /* larb0 */ 31 #define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) 32 #define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_ID(0, 1) 33 #define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2) 34 #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 3) 35 #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 4) 36 #define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) 37 38 /* larb1 */ 39 #define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_ID(1, 0) 40 #define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_ID(1, 1) 41 #define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 2) 42 #define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_ID(1, 3) 43 #define M4U_PORT_L1_DISP_MDP_RDMA4 MTK_M4U_ID(1, 4) 44 #define M4U_PORT_L1_DISP_RDMA4 MTK_M4U_ID(1, 5) 45 #define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_ID(1, 6) 46 #define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 7) 47 48 /* larb2 */ 49 #define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) 50 #define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1) 51 #define M4U_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) 52 #define M4U_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3) 53 #define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_ID(2, 4) 54 55 /* larb3: null */ 56 57 /* larb4 */ 58 #define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_ID(4, 0) 59 #define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_ID(4, 1) 60 #define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_ID(4, 2) 61 #define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3) 62 #define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4) 63 #define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5) 64 #define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_ID(4, 6) 65 #define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_ID(4, 7) 66 #define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_ID(4, 8) 67 #define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9) 68 #define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 10) 69 70 /* larb5 */ 71 #define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_ID(5, 0) 72 #define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(5, 1) 73 #define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(5, 2) 74 #define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(5, 3) 75 #define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_ID(5, 4) 76 #define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(5, 5) 77 #define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT MTK_M4U_ID(5, 6) 78 #define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_ID(5, 7) 79 80 /* larb6: null */ 81 82 /* larb7 */ 83 #define M4U_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0) 84 #define M4U_PORT_L7_VENC_REC MTK_M4U_ID(7, 1) 85 #define M4U_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2) 86 #define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3) 87 #define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4) 88 #define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5) 89 #define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6) 90 #define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7) 91 #define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8) 92 #define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9) 93 #define M4U_PORT_L7_JPGENC_Q_RDMA MTK_M4U_ID(7, 10) 94 #define M4U_PORT_L7_JPGENC_C_TABLE MTK_M4U_ID(7, 11) 95 #define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12) 96 #define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_ID(7, 13) 97 #define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_ID(7, 14) 98 99 /* larb8: null */ 100 101 /* larb9 */ 102 #define M4U_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0) 103 #define M4U_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1) 104 #define M4U_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2) 105 #define M4U_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3) 106 #define M4U_PORT_L9_IMG_ICE_D1 MTK_M4U_ID(9, 4) 107 #define M4U_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5) 108 #define M4U_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6) 109 #define M4U_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7) 110 #define M4U_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8) 111 #define M4U_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9) 112 #define M4U_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10) 113 #define M4U_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11) 114 #define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12) 115 #define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13) 116 #define M4U_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14) 117 118 /* larb10: null */ 119 120 /* larb11 */ 121 #define M4U_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0) 122 #define M4U_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1) 123 #define M4U_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2) 124 #define M4U_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3) 125 #define M4U_PORT_L11_IMG_ICE_D1 MTK_M4U_ID(11, 4) 126 #define M4U_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5) 127 #define M4U_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6) 128 #define M4U_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7) 129 #define M4U_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8) 130 #define M4U_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9) 131 #define M4U_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10) 132 #define M4U_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11) 133 #define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12) 134 #define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13) 135 #define M4U_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14) 136 #define M4U_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15) 137 #define M4U_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) 138 #define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17) 139 #define M4U_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18) 140 #define M4U_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19) 141 #define M4U_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20) 142 #define M4U_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21) 143 #define M4U_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22) 144 #define M4U_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23) 145 #define M4U_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24) 146 #define M4U_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25) 147 148 /* larb12: null */ 149 150 /* larb13 */ 151 #define M4U_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0) 152 #define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_ID(13, 1) 153 #define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_ID(13, 2) 154 #define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_ID(13, 3) 155 #define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_ID(13, 4) 156 #define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_ID(13, 5) 157 #define M4U_PORT_L13_CAM_CAMSV4 MTK_M4U_ID(13, 6) 158 #define M4U_PORT_L13_CAM_CAMSV5 MTK_M4U_ID(13, 7) 159 #define M4U_PORT_L13_CAM_CAMSV6 MTK_M4U_ID(13, 8) 160 #define M4U_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9) 161 #define M4U_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10) 162 #define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11) 163 164 /* larb14 */ 165 #define M4U_PORT_L14_CAM_RESERVE1 MTK_M4U_ID(14, 0) 166 #define M4U_PORT_L14_CAM_RESERVE2 MTK_M4U_ID(14, 1) 167 #define M4U_PORT_L14_CAM_RESERVE3 MTK_M4U_ID(14, 2) 168 #define M4U_PORT_L14_CAM_CAMSV0 MTK_M4U_ID(14, 3) 169 #define M4U_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4) 170 #define M4U_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5) 171 172 /* larb15: null */ 173 174 /* larb16 */ 175 #define M4U_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0) 176 #define M4U_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1) 177 #define M4U_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2) 178 #define M4U_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3) 179 #define M4U_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4) 180 #define M4U_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5) 181 #define M4U_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6) 182 #define M4U_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7) 183 #define M4U_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8) 184 #define M4U_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9) 185 #define M4U_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10) 186 #define M4U_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11) 187 #define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12) 188 #define M4U_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13) 189 #define M4U_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14) 190 #define M4U_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15) 191 #define M4U_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16) 192 193 /* larb17 */ 194 #define M4U_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0) 195 #define M4U_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1) 196 #define M4U_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2) 197 #define M4U_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3) 198 #define M4U_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4) 199 #define M4U_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5) 200 #define M4U_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6) 201 #define M4U_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7) 202 #define M4U_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8) 203 #define M4U_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9) 204 #define M4U_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10) 205 #define M4U_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11) 206 #define M4U_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12) 207 #define M4U_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13) 208 #define M4U_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14) 209 #define M4U_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15) 210 #define M4U_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16) 211 212 /* larb18 */ 213 #define M4U_PORT_L18_CAM_IMGO_R1_C MTK_M4U_ID(18, 0) 214 #define M4U_PORT_L18_CAM_RRZO_R1_C MTK_M4U_ID(18, 1) 215 #define M4U_PORT_L18_CAM_CQI_R1_C MTK_M4U_ID(18, 2) 216 #define M4U_PORT_L18_CAM_BPCI_R1_C MTK_M4U_ID(18, 3) 217 #define M4U_PORT_L18_CAM_YUVO_R1_C MTK_M4U_ID(18, 4) 218 #define M4U_PORT_L18_CAM_UFDI_R2_C MTK_M4U_ID(18, 5) 219 #define M4U_PORT_L18_CAM_RAWI_R2_C MTK_M4U_ID(18, 6) 220 #define M4U_PORT_L18_CAM_RAWI_R3_C MTK_M4U_ID(18, 7) 221 #define M4U_PORT_L18_CAM_AAO_R1_C MTK_M4U_ID(18, 8) 222 #define M4U_PORT_L18_CAM_AFO_R1_C MTK_M4U_ID(18, 9) 223 #define M4U_PORT_L18_CAM_FLKO_R1_C MTK_M4U_ID(18, 10) 224 #define M4U_PORT_L18_CAM_LCESO_R1_C MTK_M4U_ID(18, 11) 225 #define M4U_PORT_L18_CAM_CRZO_R1_C MTK_M4U_ID(18, 12) 226 #define M4U_PORT_L18_CAM_LTMSO_R1_C MTK_M4U_ID(18, 13) 227 #define M4U_PORT_L18_CAM_RSSO_R1_C MTK_M4U_ID(18, 14) 228 #define M4U_PORT_L18_CAM_AAHO_R1_C MTK_M4U_ID(18, 15) 229 #define M4U_PORT_L18_CAM_LSCI_R1_C MTK_M4U_ID(18, 16) 230 231 /* larb19 */ 232 #define M4U_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0) 233 #define M4U_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1) 234 #define M4U_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2) 235 #define M4U_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3) 236 237 /* larb20 */ 238 #define M4U_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0) 239 #define M4U_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1) 240 #define M4U_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2) 241 #define M4U_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3) 242 #define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) 243 #define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) 244 245 #endif 246