1 /* $NetBSD: mt8183-larb-port.h,v 1.1.1.2 2021/11/07 16:49:56 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2018 MediaTek Inc. 6 * Author: Yong Wu <yong.wu@mediatek.com> 7 */ 8 #ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ 9 #define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ 10 11 #include <dt-bindings/memory/mtk-memory-port.h> 12 13 #define M4U_LARB0_ID 0 14 #define M4U_LARB1_ID 1 15 #define M4U_LARB2_ID 2 16 #define M4U_LARB3_ID 3 17 #define M4U_LARB4_ID 4 18 #define M4U_LARB5_ID 5 19 #define M4U_LARB6_ID 6 20 #define M4U_LARB7_ID 7 21 22 /* larb0 */ 23 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 24 #define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1) 25 #define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2) 26 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) 27 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) 28 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 29 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) 30 #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) 31 #define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8) 32 #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) 33 34 /* larb1 */ 35 #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 36 #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 37 #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 38 #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 39 #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 40 #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 41 #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 42 43 /* larb2 VPU0 */ 44 #define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0) 45 #define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1) 46 #define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2) 47 48 /* larb3 VPU1 */ 49 #define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0) 50 #define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1) 51 #define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2) 52 #define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3) 53 #define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4) 54 55 /* larb4 */ 56 #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0) 57 #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1) 58 #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2) 59 #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3) 60 #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4) 61 #define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5) 62 #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6) 63 #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7) 64 #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8) 65 #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9) 66 #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10) 67 68 /* larb5 */ 69 #define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0) 70 #define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1) 71 #define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2) 72 #define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3) 73 #define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4) 74 #define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5) 75 #define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6) 76 #define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7) 77 #define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8) 78 #define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9) 79 #define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10) 80 #define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11) 81 #define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12) 82 #define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13) 83 #define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14) 84 #define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15) 85 #define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16) 86 #define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17) 87 #define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18) 88 #define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19) 89 #define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20) 90 #define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21) 91 #define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22) 92 #define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23) 93 #define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24) 94 95 /* larb6 */ 96 #define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0) 97 #define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1) 98 #define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2) 99 #define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3) 100 #define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4) 101 #define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5) 102 #define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6) 103 #define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7) 104 #define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8) 105 #define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9) 106 #define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10) 107 #define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11) 108 #define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12) 109 #define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13) 110 #define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14) 111 #define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15) 112 #define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16) 113 #define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17) 114 #define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18) 115 #define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19) 116 #define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20) 117 #define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21) 118 #define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22) 119 #define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23) 120 #define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24) 121 #define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25) 122 #define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26) 123 #define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27) 124 #define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28) 125 #define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29) 126 #define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30) 127 128 /* CCU */ 129 #define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0) 130 #define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1) 131 132 #endif 133