1 /* $NetBSD: mt8167-larb-port.h,v 1.1.1.1 2021/11/07 16:49:56 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2020 MediaTek Inc. 6 * Copyright (c) 2020 BayLibre, SAS 7 * Author: Honghui Zhang <honghui.zhang@mediatek.com> 8 * Author: Fabien Parent <fparent@baylibre.com> 9 */ 10 #ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ 11 #define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ 12 13 #include <dt-bindings/memory/mtk-memory-port.h> 14 15 #define M4U_LARB0_ID 0 16 #define M4U_LARB1_ID 1 17 #define M4U_LARB2_ID 2 18 19 /* larb0 */ 20 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 21 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 22 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 23 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3) 24 #define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4) 25 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5) 26 #define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6) 27 #define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) 28 29 /* larb1*/ 30 #define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0) 31 #define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) 32 #define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2) 33 #define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) 34 #define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) 35 #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5) 36 #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6) 37 #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7) 38 #define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8) 39 #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) 40 #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) 41 #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) 42 #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) 43 44 /* larb2*/ 45 #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) 46 #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) 47 #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) 48 #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) 49 #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) 50 #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) 51 #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) 52 53 #endif 54