1 /* $NetBSD: mt2712-larb-port.h,v 1.1.1.2 2021/11/07 16:49:56 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Yong Wu <yong.wu@mediatek.com> 7 */ 8 #ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ 9 #define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ 10 11 #include <dt-bindings/memory/mtk-memory-port.h> 12 13 #define M4U_LARB0_ID 0 14 #define M4U_LARB1_ID 1 15 #define M4U_LARB2_ID 2 16 #define M4U_LARB3_ID 3 17 #define M4U_LARB4_ID 4 18 #define M4U_LARB5_ID 5 19 #define M4U_LARB6_ID 6 20 #define M4U_LARB7_ID 7 21 #define M4U_LARB8_ID 8 22 #define M4U_LARB9_ID 9 23 24 /* larb0 */ 25 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 26 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 27 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 28 #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) 29 #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) 30 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 31 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) 32 #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) 33 34 /* larb1 */ 35 #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 36 #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 37 #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 38 #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 39 #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 40 #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 41 #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 42 #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) 43 #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) 44 #define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) 45 #define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) 46 47 /* larb2 */ 48 #define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) 49 #define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) 50 #define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) 51 52 /* larb3 */ 53 #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 54 #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 55 #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 56 #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 57 #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 58 #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) 59 #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) 60 #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) 61 #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) 62 63 /* larb4 */ 64 #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) 65 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) 66 #define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) 67 #define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) 68 #define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) 69 #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) 70 #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) 71 72 /* larb5 */ 73 #define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) 74 #define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) 75 #define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) 76 #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) 77 78 /* larb6 */ 79 #define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) 80 #define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) 81 #define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) 82 #define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) 83 84 /* larb7 */ 85 #define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) 86 #define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) 87 88 /* larb8 */ 89 #define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) 90 #define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) 91 #define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) 92 93 /* larb9 */ 94 #define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) 95 #define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) 96 97 #endif 98