1 /* $NetBSD: mt8195-gce.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Jason-JH Lin <jason0jh.lin@mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_GCE_MT8195_H 10 #define _DT_BINDINGS_GCE_MT8195_H 11 12 /* assign timeout 0 also means default */ 13 #define CMDQ_NO_TIMEOUT 0xffffffff 14 #define CMDQ_TIMEOUT_DEFAULT 1000 15 16 /* GCE thread priority */ 17 #define CMDQ_THR_PRIO_LOWEST 0 18 #define CMDQ_THR_PRIO_1 1 19 #define CMDQ_THR_PRIO_2 2 20 #define CMDQ_THR_PRIO_3 3 21 #define CMDQ_THR_PRIO_4 4 22 #define CMDQ_THR_PRIO_5 5 23 #define CMDQ_THR_PRIO_6 6 24 #define CMDQ_THR_PRIO_HIGHEST 7 25 26 /* CPR count in 32bit register */ 27 #define GCE_CPR_COUNT 1312 28 29 /* GCE subsys table */ 30 #define SUBSYS_1400XXXX 0 31 #define SUBSYS_1401XXXX 1 32 #define SUBSYS_1402XXXX 2 33 #define SUBSYS_1c00XXXX 3 34 #define SUBSYS_1c01XXXX 4 35 #define SUBSYS_1c02XXXX 5 36 #define SUBSYS_1c10XXXX 6 37 #define SUBSYS_1c11XXXX 7 38 #define SUBSYS_1c12XXXX 8 39 #define SUBSYS_14f0XXXX 9 40 #define SUBSYS_14f1XXXX 10 41 #define SUBSYS_14f2XXXX 11 42 #define SUBSYS_1800XXXX 12 43 #define SUBSYS_1801XXXX 13 44 #define SUBSYS_1802XXXX 14 45 #define SUBSYS_1803XXXX 15 46 #define SUBSYS_1032XXXX 16 47 #define SUBSYS_1033XXXX 17 48 #define SUBSYS_1600XXXX 18 49 #define SUBSYS_1601XXXX 19 50 #define SUBSYS_14e0XXXX 20 51 #define SUBSYS_1c20XXXX 21 52 #define SUBSYS_1c30XXXX 22 53 #define SUBSYS_1c40XXXX 23 54 #define SUBSYS_1c50XXXX 24 55 #define SUBSYS_1c60XXXX 25 56 57 /* GCE General Purpose Register (GPR) support */ 58 #define GCE_GPR_R00 0x0 59 #define GCE_GPR_R01 0x1 60 #define GCE_GPR_R02 0x2 61 #define GCE_GPR_R03 0x3 62 #define GCE_GPR_R04 0x4 63 #define GCE_GPR_R05 0x5 64 #define GCE_GPR_R06 0x6 65 #define GCE_GPR_R07 0x7 66 #define GCE_GPR_R08 0x8 67 #define GCE_GPR_R09 0x9 68 #define GCE_GPR_R10 0xa 69 #define GCE_GPR_R11 0xb 70 #define GCE_GPR_R12 0xc 71 #define GCE_GPR_R13 0xd 72 #define GCE_GPR_R14 0xe 73 #define GCE_GPR_R15 0xf 74 75 /* GCE hw event id */ 76 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_0 1 77 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_1 2 78 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_2 3 79 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_3 4 80 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_4 5 81 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_5 6 82 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_6 7 83 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_7 8 84 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_8 9 85 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_9 10 86 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_10 11 87 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_11 12 88 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_12 13 89 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_13 14 90 #define CMDQ_EVENT_CQ_THR_DONE_TRAW0_14 15 91 #define CMDQ_EVENT_TRAW0_DMA_ERROR_INT 16 92 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_0 17 93 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_1 18 94 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_2 19 95 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_3 20 96 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_4 21 97 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_5 22 98 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_6 23 99 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_7 24 100 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_8 25 101 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_9 26 102 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_10 27 103 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_11 28 104 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_12 29 105 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_13 30 106 #define CMDQ_EVENT_CQ_THR_DONE_TRAW1_14 31 107 #define CMDQ_EVENT_TRAW1_DMA_ERROR_INT 32 108 109 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_0 65 110 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_1 66 111 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_2 67 112 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_3 68 113 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_4 69 114 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_5 70 115 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_6 71 116 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_7 72 117 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_8 73 118 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_9 74 119 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_10 75 120 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_11 76 121 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_12 77 122 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_13 78 123 #define CMDQ_EVENT_DIP0_FRAME_DONE_P2_14 79 124 #define CMDQ_EVENT_DIP0_DMA_ERR 80 125 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_0 81 126 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_1 82 127 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_2 83 128 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_3 84 129 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_4 85 130 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_5 86 131 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_6 87 132 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_7 88 133 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_8 89 134 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_9 90 135 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_10 91 136 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_11 92 137 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_12 93 138 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_13 94 139 #define CMDQ_EVENT_PQA0_FRAME_DONE_P2_14 95 140 #define CMDQ_EVENT_PQA0_DMA_ERR 96 141 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_0 97 142 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_1 98 143 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_2 99 144 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_3 100 145 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_4 101 146 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_5 102 147 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_6 103 148 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_7 104 149 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_8 105 150 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_9 106 151 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_10 107 152 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_11 108 153 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_12 109 154 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_13 110 155 #define CMDQ_EVENT_PQB0_FRAME_DONE_P2_14 111 156 #define CMDQ_EVENT_PQB0_DMA_ERR 112 157 #define CMDQ_EVENT_DIP0_DUMMY_0 113 158 #define CMDQ_EVENT_DIP0_DUMMY_1 114 159 #define CMDQ_EVENT_DIP0_DUMMY_2 115 160 #define CMDQ_EVENT_DIP0_DUMMY_3 116 161 #define CMDQ_EVENT_WPE0_EIS_GCE_FRAME_DONE 117 162 #define CMDQ_EVENT_WPE0_EIS_DONE_SYNC_OUT 118 163 #define CMDQ_EVENT_WPE0_TNR_GCE_FRAME_DONE 119 164 #define CMDQ_EVENT_WPE0_TNR_DONE_SYNC_OUT 120 165 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_0 121 166 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_1 122 167 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_2 123 168 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_3 124 169 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_4 125 170 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_5 126 171 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_6 127 172 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_7 128 173 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_8 129 174 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_9 130 175 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_10 131 176 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_11 132 177 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_12 133 178 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_13 134 179 #define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_14 135 180 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_0 136 181 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_1 137 182 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_2 138 183 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_3 139 184 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_4 140 185 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_5 141 186 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_6 142 187 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_7 143 188 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_8 144 189 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_9 145 190 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_10 146 191 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_11 147 192 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_12 148 193 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_13 149 194 #define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_14 150 195 #define CMDQ_EVENT_WPE0_DUMMY_0 151 196 #define CMDQ_EVENT_IMGSYS_IPE_DUMMY 152 197 #define CMDQ_EVENT_IMGSYS_IPE_FDVT_DONE 153 198 #define CMDQ_EVENT_IMGSYS_IPE_ME_DONE 154 199 #define CMDQ_EVENT_IMGSYS_IPE_DVS_DONE 155 200 #define CMDQ_EVENT_IMGSYS_IPE_DVP_DONE 156 201 202 #define CMDQ_EVENT_TPR_0 194 203 #define CMDQ_EVENT_TPR_1 195 204 #define CMDQ_EVENT_TPR_2 196 205 #define CMDQ_EVENT_TPR_3 197 206 #define CMDQ_EVENT_TPR_4 198 207 #define CMDQ_EVENT_TPR_5 199 208 #define CMDQ_EVENT_TPR_6 200 209 #define CMDQ_EVENT_TPR_7 201 210 #define CMDQ_EVENT_TPR_8 202 211 #define CMDQ_EVENT_TPR_9 203 212 #define CMDQ_EVENT_TPR_10 204 213 #define CMDQ_EVENT_TPR_11 205 214 #define CMDQ_EVENT_TPR_12 206 215 #define CMDQ_EVENT_TPR_13 207 216 #define CMDQ_EVENT_TPR_14 208 217 #define CMDQ_EVENT_TPR_15 209 218 #define CMDQ_EVENT_TPR_16 210 219 #define CMDQ_EVENT_TPR_17 211 220 #define CMDQ_EVENT_TPR_18 212 221 #define CMDQ_EVENT_TPR_19 213 222 #define CMDQ_EVENT_TPR_20 214 223 #define CMDQ_EVENT_TPR_21 215 224 #define CMDQ_EVENT_TPR_22 216 225 #define CMDQ_EVENT_TPR_23 217 226 #define CMDQ_EVENT_TPR_24 218 227 #define CMDQ_EVENT_TPR_25 219 228 #define CMDQ_EVENT_TPR_26 220 229 #define CMDQ_EVENT_TPR_27 221 230 #define CMDQ_EVENT_TPR_28 222 231 #define CMDQ_EVENT_TPR_29 223 232 #define CMDQ_EVENT_TPR_30 224 233 #define CMDQ_EVENT_TPR_31 225 234 #define CMDQ_EVENT_TPR_TIMEOUT_0 226 235 #define CMDQ_EVENT_TPR_TIMEOUT_1 227 236 #define CMDQ_EVENT_TPR_TIMEOUT_2 228 237 #define CMDQ_EVENT_TPR_TIMEOUT_3 229 238 #define CMDQ_EVENT_TPR_TIMEOUT_4 230 239 #define CMDQ_EVENT_TPR_TIMEOUT_5 231 240 #define CMDQ_EVENT_TPR_TIMEOUT_6 232 241 #define CMDQ_EVENT_TPR_TIMEOUT_7 233 242 #define CMDQ_EVENT_TPR_TIMEOUT_8 234 243 #define CMDQ_EVENT_TPR_TIMEOUT_9 235 244 #define CMDQ_EVENT_TPR_TIMEOUT_10 236 245 #define CMDQ_EVENT_TPR_TIMEOUT_11 237 246 #define CMDQ_EVENT_TPR_TIMEOUT_12 238 247 #define CMDQ_EVENT_TPR_TIMEOUT_13 239 248 #define CMDQ_EVENT_TPR_TIMEOUT_14 240 249 #define CMDQ_EVENT_TPR_TIMEOUT_15 241 250 251 #define CMDQ_EVENT_VPP0_MDP_RDMA_SOF 256 252 #define CMDQ_EVENT_VPP0_MDP_FG_SOF 257 253 #define CMDQ_EVENT_VPP0_STITCH_SOF 258 254 #define CMDQ_EVENT_VPP0_MDP_HDR_SOF 259 255 #define CMDQ_EVENT_VPP0_MDP_AAL_SOF 260 256 #define CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF 261 257 #define CMDQ_EVENT_VPP0_MDP_TDSHP_SOF 262 258 #define CMDQ_EVENT_VPP0_DISP_COLOR_SOF 263 259 #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_SOF 264 260 #define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_SOF 265 261 #define CMDQ_EVENT_VPP0_MDP_TCC_IN_SOF 266 262 #define CMDQ_EVENT_VPP0_MDP_WROT_SOF 267 263 264 #define CMDQ_EVENT_VPP0_WARP0_MMSYS_TOP_RELAY_SOF_PRE 269 265 #define CMDQ_EVENT_VPP0_WARP1_MMSYS_TOP_RELAY_SOF_PRE 270 266 #define CMDQ_EVENT_VPP0_VPP1_MMSYS_TOP_RELAY_SOF 271 267 #define CMDQ_EVENT_VPP0_VPP1_IN_MMSYS_TOP_RELAY_SOF_PRE 272 268 269 #define CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE 288 270 #define CMDQ_EVENT_VPP0_MDP_FG_TILE_DONE 289 271 #define CMDQ_EVENT_VPP0_STITCH_FRAME_DONE 290 272 #define CMDQ_EVENT_VPP0_MDP_HDR_FRAME_DONE 291 273 #define CMDQ_EVENT_VPP0_MDP_AAL_FRAME_DONE 292 274 #define CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE 293 275 #define CMDQ_EVENT_VPP0_MDP_TDSHP_FRAME_DONE 294 276 #define CMDQ_EVENT_VPP0_DISP_COLOR_FRAME_DONE 295 277 #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_DONE 296 278 #define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_FRAME_DONE 297 279 #define CMDQ_EVENT_VPP0_MDP_TCC_TCC_FRAME_DONE 298 280 #define CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE 299 281 282 #define CMDQ_EVENT_VPP0_STREAM_DONE_0 320 283 #define CMDQ_EVENT_VPP0_STREAM_DONE_1 321 284 #define CMDQ_EVENT_VPP0_STREAM_DONE_2 322 285 #define CMDQ_EVENT_VPP0_STREAM_DONE_3 323 286 #define CMDQ_EVENT_VPP0_STREAM_DONE_4 324 287 #define CMDQ_EVENT_VPP0_STREAM_DONE_5 325 288 #define CMDQ_EVENT_VPP0_STREAM_DONE_6 326 289 #define CMDQ_EVENT_VPP0_STREAM_DONE_7 327 290 #define CMDQ_EVENT_VPP0_STREAM_DONE_8 328 291 #define CMDQ_EVENT_VPP0_STREAM_DONE_9 329 292 #define CMDQ_EVENT_VPP0_STREAM_DONE_10 330 293 #define CMDQ_EVENT_VPP0_STREAM_DONE_11 331 294 #define CMDQ_EVENT_VPP0_STREAM_DONE_12 332 295 #define CMDQ_EVENT_VPP0_STREAM_DONE_13 333 296 #define CMDQ_EVENT_VPP0_STREAM_DONE_14 334 297 #define CMDQ_EVENT_VPP0_STREAM_DONE_15 335 298 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_0 336 299 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_1 337 300 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_2 338 301 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_3 339 302 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_4 340 303 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_5 341 304 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_6 342 305 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_7 343 306 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_8 344 307 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_9 345 308 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_10 346 309 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_11 347 310 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_12 348 311 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_13 349 312 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_14 350 313 #define CMDQ_EVENT_VPP0_BUF_UNDERRUN_15 351 314 #define CMDQ_EVENT_VPP0_MDP_RDMA_SW_RST_DONE 352 315 #define CMDQ_EVENT_VPP0_MDP_RDMA_PM_VALID 353 316 #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_RESET_DONE_PULSE 354 317 #define CMDQ_EVENT_VPP0_MDP_WROT_SW_RST_DONE 355 318 319 #define CMDQ_EVENT_VPP1_HDMI_META_SOF 384 320 #define CMDQ_EVENT_VPP1_DGI_SOF 385 321 #define CMDQ_EVENT_VPP1_VPP_SPLIT_SOF 386 322 #define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_SOF 387 323 #define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF 388 324 #define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF 389 325 #define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF 390 326 #define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_SOF 391 327 #define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_SOF 392 328 #define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_SOF 393 329 #define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_SOF 394 330 #define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_SOF 395 331 #define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_SOF 396 332 #define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_SOF 397 333 #define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_SOF 398 334 #define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_SOF 399 335 #define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF 400 336 #define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF 401 337 #define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF 402 338 #define CMDQ_EVENT_VPP1_SVPP1_TDSHP_SOF 403 339 #define CMDQ_EVENT_VPP1_SVPP2_TDSHP_SOF 404 340 #define CMDQ_EVENT_VPP1_SVPP3_TDSHP_SOF 405 341 #define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_SOF 406 342 #define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_SOF 407 343 #define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_SOF 408 344 #define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_SOF 409 345 #define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_SOF 410 346 #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_SOF 411 347 #define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_SOF 412 348 #define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_SOF 413 349 #define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_SOF 414 350 #define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF 415 351 #define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF 416 352 #define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF 417 353 #define CMDQ_EVENT_VPP1_VPP0_DL_IRLY_SOF 418 354 #define CMDQ_EVENT_VPP1_VPP0_DL_ORLY_SOF 419 355 #define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_0_SOF 420 356 #define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_1_SOF 421 357 #define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_0_SOF 422 358 #define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_1_SOF 423 359 #define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE 424 360 #define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE 425 361 #define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE 426 362 #define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE 427 363 #define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE 428 364 #define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE 429 365 #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_FRAME_DONE 430 366 #define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE 431 367 #define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE 432 368 #define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE 433 369 #define CMDQ_EVENT_VPP1_FRAME_DONE_10 434 370 #define CMDQ_EVENT_VPP1_FRAME_DONE_11 435 371 #define CMDQ_EVENT_VPP1_FRAME_DONE_12 436 372 #define CMDQ_EVENT_VPP1_FRAME_DONE_13 437 373 #define CMDQ_EVENT_VPP1_FRAME_DONE_14 438 374 #define CMDQ_EVENT_VPP1_STREAM_DONE_0 439 375 #define CMDQ_EVENT_VPP1_STREAM_DONE_1 440 376 #define CMDQ_EVENT_VPP1_STREAM_DONE_2 441 377 #define CMDQ_EVENT_VPP1_STREAM_DONE_3 442 378 #define CMDQ_EVENT_VPP1_STREAM_DONE_4 443 379 #define CMDQ_EVENT_VPP1_STREAM_DONE_5 444 380 #define CMDQ_EVENT_VPP1_STREAM_DONE_6 445 381 #define CMDQ_EVENT_VPP1_STREAM_DONE_7 446 382 #define CMDQ_EVENT_VPP1_STREAM_DONE_8 447 383 #define CMDQ_EVENT_VPP1_STREAM_DONE_9 448 384 #define CMDQ_EVENT_VPP1_STREAM_DONE_10 449 385 #define CMDQ_EVENT_VPP1_STREAM_DONE_11 450 386 #define CMDQ_EVENT_VPP1_STREAM_DONE_12 451 387 #define CMDQ_EVENT_VPP1_STREAM_DONE_13 452 388 #define CMDQ_EVENT_VPP1_STREAM_DONE_14 453 389 #define CMDQ_EVENT_VPP1_STREAM_DONE_15 454 390 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_0 455 391 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_1 456 392 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_2 457 393 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_3 458 394 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_4 459 395 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_5 460 396 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_6 461 397 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_7 462 398 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_8 463 399 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_9 464 400 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_10 465 401 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_11 466 402 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_12 467 403 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_13 468 404 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_14 469 405 #define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_15 470 406 #define CMDQ_EVENT_VPP1_DGI_0 471 407 #define CMDQ_EVENT_VPP1_DGI_1 472 408 #define CMDQ_EVENT_VPP1_DGI_2 473 409 #define CMDQ_EVENT_VPP1_DGI_3 474 410 #define CMDQ_EVENT_VPP1_DGI_4 475 411 #define CMDQ_EVENT_VPP1_DGI_5 476 412 #define CMDQ_EVENT_VPP1_DGI_6 477 413 #define CMDQ_EVENT_VPP1_DGI_7 478 414 #define CMDQ_EVENT_VPP1_DGI_8 479 415 #define CMDQ_EVENT_VPP1_DGI_9 480 416 #define CMDQ_EVENT_VPP1_DGI_10 481 417 #define CMDQ_EVENT_VPP1_DGI_11 482 418 #define CMDQ_EVENT_VPP1_DGI_12 483 419 #define CMDQ_EVENT_VPP1_DGI_13 484 420 #define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE 485 421 #define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE 486 422 #define CMDQ_EVENT_VPP1_MDP_OVL_FRAME_RESET_DONE_PULSE 487 423 #define CMDQ_EVENT_VPP1_VPP_SPLIT_DGI 488 424 #define CMDQ_EVENT_VPP1_VPP_SPLIT_HDMI 489 425 #define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SW_RST_DONE 490 426 #define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SW_RST_DONE 491 427 #define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SW_RST_DONE 492 428 #define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_TILE_DONE 493 429 #define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_TILE_DONE 494 430 #define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_TILE_DONE 495 431 432 #define CMDQ_EVENT_VDO0_DISP_OVL0_SOF 512 433 #define CMDQ_EVENT_VDO0_DISP_WDMA0_SOF 513 434 #define CMDQ_EVENT_VDO0_DISP_RDMA0_SOF 514 435 #define CMDQ_EVENT_VDO0_DISP_COLOR0_SOF 515 436 #define CMDQ_EVENT_VDO0_DISP_CCORR0_SOF 516 437 #define CMDQ_EVENT_VDO0_DISP_AAL0_SOF 517 438 #define CMDQ_EVENT_VDO0_DISP_GAMMA0_SOF 518 439 #define CMDQ_EVENT_VDO0_DISP_DITHER0_SOF 519 440 #define CMDQ_EVENT_VDO0_DSI0_SOF 520 441 #define CMDQ_EVENT_VDO0_DSC_WRAP0C0_SOF 521 442 #define CMDQ_EVENT_VDO0_DISP_OVL1_SOF 522 443 #define CMDQ_EVENT_VDO0_DISP_WDMA1_SOF 523 444 #define CMDQ_EVENT_VDO0_DISP_RDMA1_SOF 524 445 #define CMDQ_EVENT_VDO0_DISP_COLOR1_SOF 525 446 #define CMDQ_EVENT_VDO0_DISP_CCORR1_SOF 526 447 #define CMDQ_EVENT_VDO0_DISP_AAL1_SOF 527 448 #define CMDQ_EVENT_VDO0_DISP_GAMMA1_SOF 528 449 #define CMDQ_EVENT_VDO0_DISP_DITHER1_SOF 529 450 #define CMDQ_EVENT_VDO0_DSI1_SOF 530 451 #define CMDQ_EVENT_VDO0_DSC_WRAP0C1_SOF 531 452 #define CMDQ_EVENT_VDO0_VPP_MERGE0_SOF 532 453 #define CMDQ_EVENT_VDO0_DP_INTF0_SOF 533 454 #define CMDQ_EVENT_VDO0_VPP1_DL_RELAY0_SOF 534 455 #define CMDQ_EVENT_VDO0_VPP1_DL_RELAY1_SOF 535 456 #define CMDQ_EVENT_VDO0_VDO1_DL_RELAY2_SOF 536 457 #define CMDQ_EVENT_VDO0_VDO0_DL_RELAY3_SOF 537 458 #define CMDQ_EVENT_VDO0_VDO0_DL_RELAY4_SOF 538 459 #define CMDQ_EVENT_VDO0_DISP_PWM0_SOF 539 460 #define CMDQ_EVENT_VDO0_DISP_PWM1_SOF 540 461 462 #define CMDQ_EVENT_VDO0_DISP_OVL0_FRAME_DONE 544 463 #define CMDQ_EVENT_VDO0_DISP_WDMA0_FRAME_DONE 545 464 #define CMDQ_EVENT_VDO0_DISP_RDMA0_FRAME_DONE 546 465 #define CMDQ_EVENT_VDO0_DISP_COLOR0_FRAME_DONE 547 466 #define CMDQ_EVENT_VDO0_DISP_CCORR0_FRAME_DONE 548 467 #define CMDQ_EVENT_VDO0_DISP_AAL0_FRAME_DONE 549 468 #define CMDQ_EVENT_VDO0_DISP_GAMMA0_FRAME_DONE 550 469 #define CMDQ_EVENT_VDO0_DISP_DITHER0_FRAME_DONE 551 470 #define CMDQ_EVENT_VDO0_DSI0_FRAME_DONE 552 471 #define CMDQ_EVENT_VDO0_DSC_WRAP0C0_FRAME_DONE 553 472 #define CMDQ_EVENT_VDO0_DISP_OVL1_FRAME_DONE 554 473 #define CMDQ_EVENT_VDO0_DISP_WDMA1_FRAME_DONE 555 474 #define CMDQ_EVENT_VDO0_DISP_RDMA1_FRAME_DONE 556 475 #define CMDQ_EVENT_VDO0_DISP_COLOR1_FRAME_DONE 557 476 #define CMDQ_EVENT_VDO0_DISP_CCORR1_FRAME_DONE 558 477 #define CMDQ_EVENT_VDO0_DISP_AAL1_FRAME_DONE 559 478 #define CMDQ_EVENT_VDO0_DISP_GAMMA1_FRAME_DONE 560 479 #define CMDQ_EVENT_VDO0_DISP_DITHER1_FRAME_DONE 561 480 #define CMDQ_EVENT_VDO0_DSI1_FRAME_DONE 562 481 #define CMDQ_EVENT_VDO0_DSC_WRAP0C1_FRAME_DONE 563 482 483 #define CMDQ_EVENT_VDO0_DP_INTF0_FRAME_DONE 565 484 485 #define CMDQ_EVENT_VDO0_DISP_SMIASSERT_ENG 576 486 #define CMDQ_EVENT_VDO0_DSI0_IRQ_ENG_EVENT_MM 577 487 #define CMDQ_EVENT_VDO0_DSI0_TE_ENG_EVENT_MM 578 488 #define CMDQ_EVENT_VDO0_DSI0_DONE_ENG_EVENT_MM 579 489 #define CMDQ_EVENT_VDO0_DSI0_SOF_ENG_EVENT_MM 580 490 #define CMDQ_EVENT_VDO0_DSI0_VACTL_ENG_EVENT_MM 581 491 #define CMDQ_EVENT_VDO0_DSI1_IRQ_ENG_EVENT_MM 582 492 #define CMDQ_EVENT_VDO0_DSI1_TE_ENG_EVENT_MM 583 493 #define CMDQ_EVENT_VDO0_DSI1_DONE_ENG_EVENT_MM 584 494 #define CMDQ_EVENT_VDO0_DSI1_SOF_ENG_EVENT_MM 585 495 #define CMDQ_EVENT_VDO0_DSI1_VACTL_ENG_EVENT_MM 586 496 #define CMDQ_EVENT_VDO0_DISP_WDMA0_SW_RST_DONE_ENG 587 497 #define CMDQ_EVENT_VDO0_DISP_WDMA1_SW_RST_DONE_ENG 588 498 #define CMDQ_EVENT_VDO0_DISP_OVL0_RST_DONE_ENG 589 499 #define CMDQ_EVENT_VDO0_DISP_OVL1_RST_DONE_ENG 590 500 #define CMDQ_EVENT_VDO0_DP_INTF0_VSYNC_START_ENG_EVENT_MM 591 501 #define CMDQ_EVENT_VDO0_DP_INTF0_VSYNC_END_ENG_EVENT_MM 592 502 #define CMDQ_EVENT_VDO0_DP_INTF0_VDE_START_ENG_EVENT_MM 593 503 #define CMDQ_EVENT_VDO0_DP_INTF0_VDE_END_ENG_EVENT_MM 594 504 #define CMDQ_EVENT_VDO0_DP_INTF0_TARGET_LINE_ENG_EVENT_MM 595 505 #define CMDQ_EVENT_VDO0_VPP_MERGE0_ENG 596 506 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0 597 507 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_1 598 508 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_2 599 509 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_3 600 510 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_4 601 511 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_5 602 512 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_6 603 513 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_7 604 514 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_8 605 515 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_9 606 516 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_10 607 517 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_11 608 518 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_12 609 519 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_13 610 520 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_14 611 521 #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_15 612 522 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_0 613 523 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_1 614 524 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_2 615 525 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_3 616 526 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_4 617 527 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_5 618 528 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_6 619 529 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_7 620 530 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_8 621 531 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_9 622 532 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_10 623 533 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_11 624 534 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_12 625 535 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_13 626 536 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_14 627 537 #define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_15 628 538 539 #define CMDQ_EVENT_VDO1_MDP_RDMA0_SOF 640 540 #define CMDQ_EVENT_VDO1_MDP_RDMA1_SOF 641 541 #define CMDQ_EVENT_VDO1_MDP_RDMA2_SOF 642 542 #define CMDQ_EVENT_VDO1_MDP_RDMA3_SOF 643 543 #define CMDQ_EVENT_VDO1_MDP_RDMA4_SOF 644 544 #define CMDQ_EVENT_VDO1_MDP_RDMA5_SOF 645 545 #define CMDQ_EVENT_VDO1_MDP_RDMA6_SOF 646 546 #define CMDQ_EVENT_VDO1_MDP_RDMA7_SOF 647 547 #define CMDQ_EVENT_VDO1_VPP_MERGE0_SOF 648 548 #define CMDQ_EVENT_VDO1_VPP_MERGE1_SOF 649 549 #define CMDQ_EVENT_VDO1_VPP_MERGE2_SOF 650 550 #define CMDQ_EVENT_VDO1_VPP_MERGE3_SOF 651 551 #define CMDQ_EVENT_VDO1_VPP_MERGE4_SOF 652 552 #define CMDQ_EVENT_VDO1_VPP2_DL_RELAY_SOF 653 553 #define CMDQ_EVENT_VDO1_VPP3_DL_RELAY_SOF 654 554 #define CMDQ_EVENT_VDO1_VDO0_DSC_DL_ASYNC_SOF 655 555 #define CMDQ_EVENT_VDO1_VDO0_MERGE_DL_ASYNC_SOF 656 556 #define CMDQ_EVENT_VDO1_OUT_DL_RELAY_SOF 657 557 #define CMDQ_EVENT_VDO1_DISP_MIXER_SOF 658 558 #define CMDQ_EVENT_VDO1_HDR_VDO_FE0_SOF 659 559 #define CMDQ_EVENT_VDO1_HDR_VDO_FE1_SOF 660 560 #define CMDQ_EVENT_VDO1_HDR_GFX_FE0_SOF 661 561 #define CMDQ_EVENT_VDO1_HDR_GFX_FE1_SOF 662 562 #define CMDQ_EVENT_VDO1_HDR_VDO_BE0_SOF 663 563 #define CMDQ_EVENT_VDO1_HDR_MLOAD_SOF 664 564 565 #define CMDQ_EVENT_VDO1_MDP_RDMA0_FRAME_DONE 672 566 #define CMDQ_EVENT_VDO1_MDP_RDMA1_FRAME_DONE 673 567 #define CMDQ_EVENT_VDO1_MDP_RDMA2_FRAME_DONE 674 568 #define CMDQ_EVENT_VDO1_MDP_RDMA3_FRAME_DONE 675 569 #define CMDQ_EVENT_VDO1_MDP_RDMA4_FRAME_DONE 676 570 #define CMDQ_EVENT_VDO1_MDP_RDMA5_FRAME_DONE 677 571 #define CMDQ_EVENT_VDO1_MDP_RDMA6_FRAME_DONE 678 572 #define CMDQ_EVENT_VDO1_MDP_RDMA7_FRAME_DONE 679 573 #define CMDQ_EVENT_VDO1_VPP_MERGE0_FRAME_DONE 680 574 #define CMDQ_EVENT_VDO1_VPP_MERGE1_FRAME_DONE 681 575 #define CMDQ_EVENT_VDO1_VPP_MERGE2_FRAME_DONE 682 576 #define CMDQ_EVENT_VDO1_VPP_MERGE3_FRAME_DONE 683 577 #define CMDQ_EVENT_VDO1_VPP_MERGE4_FRAME_DONE 684 578 #define CMDQ_EVENT_VDO1_DPI0_FRAME_DONE 685 579 #define CMDQ_EVENT_VDO1_DPI1_FRAME_DONE 686 580 #define CMDQ_EVENT_VDO1_DP_INTF0_FRAME_DONE 687 581 #define CMDQ_EVENT_VDO1_DISP_MIXER_FRAME_DONE_MM 688 582 583 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0 704 584 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_1 705 585 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_2 706 586 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_3 707 587 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_4 708 588 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_5 709 589 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_6 710 590 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_7 711 591 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_8 712 592 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_9 713 593 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_10 714 594 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_11 715 595 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_12 716 596 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_13 717 597 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_14 718 598 #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_15 719 599 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_0 720 600 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_1 721 601 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_2 722 602 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_3 723 603 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_4 724 604 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_5 725 605 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_6 726 606 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_7 727 607 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_8 728 608 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_9 729 609 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_10 730 610 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_11 731 611 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_12 732 612 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_13 733 613 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_14 734 614 #define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_15 735 615 #define CMDQ_EVENT_VDO1_MDP_RDMA0_SW_RST_DONE 736 616 #define CMDQ_EVENT_VDO1_MDP_RDMA1_SW_RST_DONE 737 617 #define CMDQ_EVENT_VDO1_MDP_RDMA2_SW_RST_DONE 738 618 #define CMDQ_EVENT_VDO1_MDP_RDMA3_SW_RST_DONE 739 619 #define CMDQ_EVENT_VDO1_MDP_RDMA4_SW_RST_DONE 740 620 #define CMDQ_EVENT_VDO1_MDP_RDMA5_SW_RST_DONE 741 621 #define CMDQ_EVENT_VDO1_MDP_RDMA6_SW_RST_DONE 742 622 #define CMDQ_EVENT_VDO1_MDP_RDMA7_SW_RST_DONE 743 623 624 #define CMDQ_EVENT_VDO1_DP0_VDE_END_ENG_EVENT_MM 745 625 #define CMDQ_EVENT_VDO1_DP0_VDE_START_ENG_EVENT_MM 746 626 #define CMDQ_EVENT_VDO1_DP0_VSYNC_END_ENG_EVENT_MM 747 627 #define CMDQ_EVENT_VDO1_DP0_VSYNC_START_ENG_EVENT_MM 748 628 #define CMDQ_EVENT_VDO1_DP0_TARGET_LINE_ENG_EVENT_MM 749 629 #define CMDQ_EVENT_VDO1_VPP_MERGE0 750 630 #define CMDQ_EVENT_VDO1_VPP_MERGE1 751 631 #define CMDQ_EVENT_VDO1_VPP_MERGE2 752 632 #define CMDQ_EVENT_VDO1_VPP_MERGE3 753 633 #define CMDQ_EVENT_VDO1_VPP_MERGE4 754 634 #define CMDQ_EVENT_VDO1_HDMITX 755 635 #define CMDQ_EVENT_VDO1_HDR_VDO_BE0_ADL_TRIG_EVENT_MM 756 636 #define CMDQ_EVENT_VDO1_HDR_GFX_FE1_THDR_ADL_TRIG_EVENT_MM 757 637 #define CMDQ_EVENT_VDO1_HDR_GFX_FE1_DM_ADL_TRIG_EVENT_MM 758 638 #define CMDQ_EVENT_VDO1_HDR_GFX_FE0_THDR_ADL_TRIG_EVENT_MM 759 639 #define CMDQ_EVENT_VDO1_HDR_GFX_FE0_DM_ADL_TRIG_EVENT_MM 760 640 #define CMDQ_EVENT_VDO1_HDR_VDO_FE1_ADL_TRIG_EVENT_MM 761 641 #define CMDQ_EVENT_VDO1_HDR_VDO_FE1_AD0_TRIG_EVENT_MM 762 642 643 #define CMDQ_EVENT_CAM_A_PASS1_DONE 769 644 #define CMDQ_EVENT_CAM_B_PASS1_DONE 770 645 #define CMDQ_EVENT_GCAMSV_A_PASS1_DONE 771 646 #define CMDQ_EVENT_GCAMSV_B_PASS1_DONE 772 647 #define CMDQ_EVENT_MRAW_0_PASS1_DONE 773 648 #define CMDQ_EVENT_MRAW_1_PASS1_DONE 774 649 #define CMDQ_EVENT_MRAW_2_PASS1_DONE 775 650 #define CMDQ_EVENT_MRAW_3_PASS1_DONE 776 651 #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL_X 777 652 #define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL_X 778 653 #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 779 654 #define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 780 655 #define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 781 656 #define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 782 657 #define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 783 658 #define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 784 659 #define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 785 660 #define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 786 661 #define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL_X 787 662 #define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL_X 788 663 #define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL_X 789 664 #define CMDQ_EVENT_SENINF_CAM13_FIFO_FULL_X 790 665 #define CMDQ_EVENT_TG_OVRUN_MRAW0_INT_X0 791 666 #define CMDQ_EVENT_TG_OVRUN_MRAW1_INT_X0 792 667 #define CMDQ_EVENT_TG_OVRUN_MRAW2_INT 793 668 #define CMDQ_EVENT_TG_OVRUN_MRAW3_INT 794 669 #define CMDQ_EVENT_DMA_R1_ERROR_MRAW0_INT 795 670 #define CMDQ_EVENT_DMA_R1_ERROR_MRAW1_INT 796 671 #define CMDQ_EVENT_DMA_R1_ERROR_MRAW2_INT 797 672 #define CMDQ_EVENT_DMA_R1_ERROR_MRAW3_INT 798 673 #define CMDQ_EVENT_U_CAMSYS_PDA_IRQO_EVENT_DONE_D1 799 674 #define CMDQ_EVENT_SUBB_TG_INT4 800 675 #define CMDQ_EVENT_SUBB_TG_INT3 801 676 #define CMDQ_EVENT_SUBB_TG_INT2 802 677 #define CMDQ_EVENT_SUBB_TG_INT1 803 678 #define CMDQ_EVENT_SUBA_TG_INT4 804 679 #define CMDQ_EVENT_SUBA_TG_INT3 805 680 #define CMDQ_EVENT_SUBA_TG_INT2 806 681 #define CMDQ_EVENT_SUBA_TG_INT1 807 682 #define CMDQ_EVENT_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 808 683 #define CMDQ_EVENT_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 809 684 #define CMDQ_EVENT_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 810 685 #define CMDQ_EVENT_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 811 686 #define CMDQ_EVENT_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 812 687 #define CMDQ_EVENT_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 813 688 #define CMDQ_EVENT_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 814 689 #define CMDQ_EVENT_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 815 690 #define CMDQ_EVENT_GCE1_SOF_0 816 691 #define CMDQ_EVENT_GCE1_SOF_1 817 692 #define CMDQ_EVENT_GCE1_SOF_2 818 693 #define CMDQ_EVENT_GCE1_SOF_3 819 694 #define CMDQ_EVENT_GCE1_SOF_4 820 695 #define CMDQ_EVENT_GCE1_SOF_5 821 696 #define CMDQ_EVENT_GCE1_SOF_6 822 697 #define CMDQ_EVENT_GCE1_SOF_7 823 698 #define CMDQ_EVENT_GCE1_SOF_8 824 699 #define CMDQ_EVENT_GCE1_SOF_9 825 700 #define CMDQ_EVENT_GCE1_SOF_10 826 701 #define CMDQ_EVENT_GCE1_SOF_11 827 702 #define CMDQ_EVENT_GCE1_SOF_12 828 703 #define CMDQ_EVENT_GCE1_SOF_13 829 704 #define CMDQ_EVENT_GCE1_SOF_14 830 705 #define CMDQ_EVENT_GCE1_SOF_15 831 706 707 #define CMDQ_EVENT_VDEC_LAT_LINE_COUNT_THRESHOLD_INTERRUPT 832 708 #define CMDQ_EVENT_VDEC_LAT_VDEC_INT 833 709 #define CMDQ_EVENT_VDEC_LAT_VDEC_PAUSE 834 710 #define CMDQ_EVENT_VDEC_LAT_VDEC_DEC_ERROR 835 711 #define CMDQ_EVENT_VDEC_LAT_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 836 712 #define CMDQ_EVENT_VDEC_LAT_VDEC_FRAME_DONE 837 713 #define CMDQ_EVENT_VDEC_LAT_INI_FETCH_RDY 838 714 #define CMDQ_EVENT_VDEC_LAT_PROCESS_FLAG 839 715 #define CMDQ_EVENT_VDEC_LAT_SEARCH_START_CODE_DONE 840 716 #define CMDQ_EVENT_VDEC_LAT_REF_REORDER_DONE 841 717 #define CMDQ_EVENT_VDEC_LAT_WP_TBLE_DONE 842 718 #define CMDQ_EVENT_VDEC_LAT_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 843 719 #define CMDQ_EVENT_VDEC_LAT_GCE_CNT_OP_THRESHOLD 847 720 721 #define CMDQ_EVENT_VDEC_LAT1_LINE_COUNT_THRESHOLD_INTERRUPT 848 722 #define CMDQ_EVENT_VDEC_LAT1_VDEC_INT 849 723 #define CMDQ_EVENT_VDEC_LAT1_VDEC_PAUSE 850 724 #define CMDQ_EVENT_VDEC_LAT1_VDEC_DEC_ERROR 851 725 #define CMDQ_EVENT_VDEC_LAT1_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 852 726 #define CMDQ_EVENT_VDEC_LAT1_VDEC_FRAME_DONE 853 727 #define CMDQ_EVENT_VDEC_LAT1_INI_FETCH_RDY 854 728 #define CMDQ_EVENT_VDEC_LAT1_PROCESS_FLAG 855 729 #define CMDQ_EVENT_VDEC_LAT1_SEARCH_START_CODE_DONE 856 730 #define CMDQ_EVENT_VDEC_LAT1_REF_REORDER_DONE 857 731 #define CMDQ_EVENT_VDEC_LAT1_WP_TBLE_DONE 858 732 #define CMDQ_EVENT_VDEC_LAT1_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 859 733 #define CMDQ_EVENT_VDEC_LAT1_GCE_CNT_OP_THRESHOLD 863 734 735 #define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_0 864 736 #define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_1 865 737 738 #define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_8 872 739 #define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_9 873 740 741 #define CMDQ_EVENT_VDEC_CORE_LINE_COUNT_THRESHOLD_INTERRUPT 896 742 #define CMDQ_EVENT_VDEC_CORE_VDEC_INT 897 743 #define CMDQ_EVENT_VDEC_CORE_VDEC_PAUSE 898 744 #define CMDQ_EVENT_VDEC_CORE_VDEC_DEC_ERROR 899 745 #define CMDQ_EVENT_VDEC_CORE_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 900 746 #define CMDQ_EVENT_VDEC_CORE_VDEC_FRAME_DONE 901 747 #define CMDQ_EVENT_VDEC_CORE_INI_FETCH_RDY 902 748 #define CMDQ_EVENT_VDEC_CORE_PROCESS_FLAG 903 749 #define CMDQ_EVENT_VDEC_CORE_SEARCH_START_CODE_DONE 904 750 #define CMDQ_EVENT_VDEC_CORE_REF_REORDER_DONE 905 751 #define CMDQ_EVENT_VDEC_CORE_WP_TBLE_DONE 906 752 #define CMDQ_EVENT_VDEC_CORE_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 907 753 #define CMDQ_EVENT_VDEC_CORE_GCE_CNT_OP_THRESHOLD 911 754 755 #define CMDQ_EVENT_VDEC_CORE1_LINE_COUNT_THRESHOLD_INTERRUPT 912 756 #define CMDQ_EVENT_VDEC_CORE1_VDEC_INT 913 757 #define CMDQ_EVENT_VDEC_CORE1_VDEC_PAUSE 914 758 #define CMDQ_EVENT_VDEC_CORE1_VDEC_DEC_ERROR 915 759 #define CMDQ_EVENT_VDEC_CORE1_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 916 760 #define CMDQ_EVENT_VDEC_CORE1_VDEC_FRAME_DONE 917 761 #define CMDQ_EVENT_VDEC_CORE1_INI_FETCH_RDY 918 762 #define CMDQ_EVENT_VDEC_CORE1_PROCESS_FLAG 919 763 #define CMDQ_EVENT_VDEC_CORE1_SEARCH_START_CODE_DONE 920 764 #define CMDQ_EVENT_VDEC_CORE1_REF_REORDER_DONE 921 765 #define CMDQ_EVENT_VDEC_CORE1_WP_TBLE_DONE 922 766 #define CMDQ_EVENT_VDEC_CORE1_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 923 767 #define CMDQ_EVENT_VDEC_CORE1_CNT_OP_THRESHOLD 927 768 769 #define CMDQ_EVENT_VENC_TOP_FRAME_DONE 929 770 #define CMDQ_EVENT_VENC_TOP_PAUSE_DONE 930 771 #define CMDQ_EVENT_VENC_TOP_JPGENC_DONE 931 772 #define CMDQ_EVENT_VENC_TOP_MB_DONE 932 773 #define CMDQ_EVENT_VENC_TOP_128BYTE_DONE 933 774 #define CMDQ_EVENT_VENC_TOP_JPGDEC_DONE 934 775 #define CMDQ_EVENT_VENC_TOP_JPGDEC_C1_DONE 935 776 #define CMDQ_EVENT_VENC_TOP_JPGDEC_INSUFF_DONE 936 777 #define CMDQ_EVENT_VENC_TOP_JPGDEC_C1_INSUFF_DONE 937 778 #define CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE 938 779 #define CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE 939 780 #define CMDQ_EVENT_VENC_TOP_PPS_HEADER_DONE 940 781 #define CMDQ_EVENT_VENC_TOP_SPS_HEADER_DONE 941 782 #define CMDQ_EVENT_VENC_TOP_VPS_HEADER_DONE 942 783 784 #define CMDQ_EVENT_VENC_CORE1_TOP_FRAME_DONE 945 785 #define CMDQ_EVENT_VENC_CORE1_TOP_PAUSE_DONE 946 786 #define CMDQ_EVENT_VENC_CORE1_TOP_JPGENC_DONE 947 787 #define CMDQ_EVENT_VENC_CORE1_TOP_MB_DONE 948 788 #define CMDQ_EVENT_VENC_CORE1_TOP_128BYTE_DONE 949 789 #define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_DONE 950 790 #define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_C1_DONE 951 791 #define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_INSUFF_DONE 952 792 #define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_C1_INSUFF_DONE 953 793 #define CMDQ_EVENT_VENC_CORE1_TOP_WP_2ND_STAGE_DONE 954 794 #define CMDQ_EVENT_VENC_CORE1_TOP_WP_3RD_STAGE_DONE 955 795 #define CMDQ_EVENT_VENC_CORE1_TOP_PPS_HEADER_DONE 956 796 #define CMDQ_EVENT_VENC_CORE1_TOP_SPS_HEADER_DONE 957 797 #define CMDQ_EVENT_VENC_CORE1_TOP_VPS_HEADER_DONE 958 798 799 #define CMDQ_EVENT_WPE_VPP0_WPE_GCE_FRAME_DONE 962 800 #define CMDQ_EVENT_WPE_VPP0_WPE_DONE_SYNC_OUT 963 801 802 #define CMDQ_EVENT_WPE_VPP1_WPE_GCE_FRAME_DONE 969 803 #define CMDQ_EVENT_WPE_VPP1_WPE_DONE_SYNC_OUT 970 804 805 #define CMDQ_EVENT_DP_TX_VBLANK_FALLING 994 806 #define CMDQ_EVENT_DP_TX_VSC_FINISH 995 807 808 #define CMDQ_EVENT_OUTPIN_0 1018 809 #define CMDQ_EVENT_OUTPIN_1 1019 810 811 /* end of hw event */ 812 #define CMDQ_MAX_HW_EVENT 1019 813 814 #endif 815