1 /* $NetBSD: sun5i-ccu.h,v 1.1.1.3 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright 2016 Maxime Ripard 6 * 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ 9 10 #ifndef _DT_BINDINGS_CLK_SUN5I_H_ 11 #define _DT_BINDINGS_CLK_SUN5I_H_ 12 13 #define CLK_HOSC 1 14 15 #define CLK_PLL_VIDEO0_2X 9 16 17 #define CLK_PLL_VIDEO1_2X 16 18 #define CLK_CPU 17 19 20 #define CLK_AHB_OTG 23 21 #define CLK_AHB_EHCI 24 22 #define CLK_AHB_OHCI 25 23 #define CLK_AHB_SS 26 24 #define CLK_AHB_DMA 27 25 #define CLK_AHB_BIST 28 26 #define CLK_AHB_MMC0 29 27 #define CLK_AHB_MMC1 30 28 #define CLK_AHB_MMC2 31 29 #define CLK_AHB_NAND 32 30 #define CLK_AHB_SDRAM 33 31 #define CLK_AHB_EMAC 34 32 #define CLK_AHB_TS 35 33 #define CLK_AHB_SPI0 36 34 #define CLK_AHB_SPI1 37 35 #define CLK_AHB_SPI2 38 36 #define CLK_AHB_GPS 39 37 #define CLK_AHB_HSTIMER 40 38 #define CLK_AHB_VE 41 39 #define CLK_AHB_TVE 42 40 #define CLK_AHB_LCD 43 41 #define CLK_AHB_CSI 44 42 #define CLK_AHB_HDMI 45 43 #define CLK_AHB_DE_BE 46 44 #define CLK_AHB_DE_FE 47 45 #define CLK_AHB_IEP 48 46 #define CLK_AHB_GPU 49 47 #define CLK_APB0_CODEC 50 48 #define CLK_APB0_SPDIF 51 49 #define CLK_APB0_I2S 52 50 #define CLK_APB0_PIO 53 51 #define CLK_APB0_IR 54 52 #define CLK_APB0_KEYPAD 55 53 #define CLK_APB1_I2C0 56 54 #define CLK_APB1_I2C1 57 55 #define CLK_APB1_I2C2 58 56 #define CLK_APB1_UART0 59 57 #define CLK_APB1_UART1 60 58 #define CLK_APB1_UART2 61 59 #define CLK_APB1_UART3 62 60 #define CLK_NAND 63 61 #define CLK_MMC0 64 62 #define CLK_MMC1 65 63 #define CLK_MMC2 66 64 #define CLK_TS 67 65 #define CLK_SS 68 66 #define CLK_SPI0 69 67 #define CLK_SPI1 70 68 #define CLK_SPI2 71 69 #define CLK_IR 72 70 #define CLK_I2S 73 71 #define CLK_SPDIF 74 72 #define CLK_KEYPAD 75 73 #define CLK_USB_OHCI 76 74 #define CLK_USB_PHY0 77 75 #define CLK_USB_PHY1 78 76 #define CLK_GPS 79 77 #define CLK_DRAM_VE 80 78 #define CLK_DRAM_CSI 81 79 #define CLK_DRAM_TS 82 80 #define CLK_DRAM_TVE 83 81 #define CLK_DRAM_DE_FE 84 82 #define CLK_DRAM_DE_BE 85 83 #define CLK_DRAM_ACE 86 84 #define CLK_DRAM_IEP 87 85 #define CLK_DE_BE 88 86 #define CLK_DE_FE 89 87 #define CLK_TCON_CH0 90 88 89 #define CLK_TCON_CH1 92 90 #define CLK_CSI 93 91 #define CLK_VE 94 92 #define CLK_CODEC 95 93 #define CLK_AVS 96 94 #define CLK_HDMI 97 95 #define CLK_GPU 98 96 #define CLK_MBUS 99 97 #define CLK_IEP 100 98 99 #endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ 100