1 /* $NetBSD: stih407-clks.h,v 1.1.1.2 2017/11/30 19:40:51 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * This header provides constants clk index STMicroelectronics 6 * STiH407 SoC. 7 */ 8 #ifndef _DT_BINDINGS_CLK_STIH407 9 #define _DT_BINDINGS_CLK_STIH407 10 11 /* CLOCKGEN A0 */ 12 #define CLK_IC_LMI0 0 13 #define CLK_IC_LMI1 1 14 15 /* CLOCKGEN C0 */ 16 #define CLK_ICN_GPU 0 17 #define CLK_FDMA 1 18 #define CLK_NAND 2 19 #define CLK_HVA 3 20 #define CLK_PROC_STFE 4 21 #define CLK_PROC_TP 5 22 #define CLK_RX_ICN_DMU 6 23 #define CLK_RX_ICN_DISP_0 6 24 #define CLK_RX_ICN_DISP_1 6 25 #define CLK_RX_ICN_HVA 7 26 #define CLK_RX_ICN_TS 7 27 #define CLK_ICN_CPU 8 28 #define CLK_TX_ICN_DMU 9 29 #define CLK_TX_ICN_HVA 9 30 #define CLK_TX_ICN_TS 9 31 #define CLK_ICN_COMPO 9 32 #define CLK_MMC_0 10 33 #define CLK_MMC_1 11 34 #define CLK_JPEGDEC 12 35 #define CLK_ICN_REG 13 36 #define CLK_TRACE_A9 13 37 #define CLK_PTI_STM 13 38 #define CLK_EXT2F_A9 13 39 #define CLK_IC_BDISP_0 14 40 #define CLK_IC_BDISP_1 15 41 #define CLK_PP_DMU 16 42 #define CLK_VID_DMU 17 43 #define CLK_DSS_LPC 18 44 #define CLK_ST231_AUD_0 19 45 #define CLK_ST231_GP_0 19 46 #define CLK_ST231_GP_1 20 47 #define CLK_ST231_DMU 21 48 #define CLK_ICN_LMI 22 49 #define CLK_TX_ICN_DISP_0 23 50 #define CLK_TX_ICN_DISP_1 23 51 #define CLK_ICN_SBC 24 52 #define CLK_STFE_FRC2 25 53 #define CLK_ETH_PHY 26 54 #define CLK_ETH_REF_PHYCLK 27 55 #define CLK_FLASH_PROMIP 28 56 #define CLK_MAIN_DISP 29 57 #define CLK_AUX_DISP 30 58 #define CLK_COMPO_DVP 31 59 60 /* CLOCKGEN D0 */ 61 #define CLK_PCM_0 0 62 #define CLK_PCM_1 1 63 #define CLK_PCM_2 2 64 #define CLK_SPDIFF 3 65 66 /* CLOCKGEN D2 */ 67 #define CLK_PIX_MAIN_DISP 0 68 #define CLK_PIX_PIP 1 69 #define CLK_PIX_GDP1 2 70 #define CLK_PIX_GDP2 3 71 #define CLK_PIX_GDP3 4 72 #define CLK_PIX_GDP4 5 73 #define CLK_PIX_AUX_DISP 6 74 #define CLK_DENC 7 75 #define CLK_PIX_HDDAC 8 76 #define CLK_HDDAC 9 77 #define CLK_SDDAC 10 78 #define CLK_PIX_DVO 11 79 #define CLK_DVO 12 80 #define CLK_PIX_HDMI 13 81 #define CLK_TMDS_HDMI 14 82 #define CLK_REF_HDMIPHY 15 83 84 /* CLOCKGEN D3 */ 85 #define CLK_STFE_FRC1 0 86 #define CLK_TSOUT_0 1 87 #define CLK_TSOUT_1 2 88 #define CLK_MCHI 3 89 #define CLK_VSENS_COMPO 4 90 #define CLK_FRC1_REMOTE 5 91 #define CLK_LPC_0 6 92 #define CLK_LPC_1 7 93 #endif 94