1 /* $NetBSD: sh73a0-clock.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright 2014 Ulrich Hecht 6 */ 7 8 #ifndef __DT_BINDINGS_CLOCK_SH73A0_H__ 9 #define __DT_BINDINGS_CLOCK_SH73A0_H__ 10 11 /* CPG */ 12 #define SH73A0_CLK_MAIN 0 13 #define SH73A0_CLK_PLL0 1 14 #define SH73A0_CLK_PLL1 2 15 #define SH73A0_CLK_PLL2 3 16 #define SH73A0_CLK_PLL3 4 17 #define SH73A0_CLK_DSI0PHY 5 18 #define SH73A0_CLK_DSI1PHY 6 19 #define SH73A0_CLK_ZG 7 20 #define SH73A0_CLK_M3 8 21 #define SH73A0_CLK_B 9 22 #define SH73A0_CLK_M1 10 23 #define SH73A0_CLK_M2 11 24 #define SH73A0_CLK_Z 12 25 #define SH73A0_CLK_ZX 13 26 #define SH73A0_CLK_HP 14 27 28 /* MSTP0 */ 29 #define SH73A0_CLK_IIC2 1 30 #define SH73A0_CLK_MSIOF0 0 31 32 /* MSTP1 */ 33 #define SH73A0_CLK_CEU1 29 34 #define SH73A0_CLK_CSI2_RX1 28 35 #define SH73A0_CLK_CEU0 27 36 #define SH73A0_CLK_CSI2_RX0 26 37 #define SH73A0_CLK_TMU0 25 38 #define SH73A0_CLK_DSITX0 18 39 #define SH73A0_CLK_IIC0 16 40 #define SH73A0_CLK_SGX 12 41 #define SH73A0_CLK_LCDC0 0 42 43 /* MSTP2 */ 44 #define SH73A0_CLK_SCIFA7 19 45 #define SH73A0_CLK_SY_DMAC 18 46 #define SH73A0_CLK_MP_DMAC 17 47 #define SH73A0_CLK_MSIOF3 15 48 #define SH73A0_CLK_MSIOF1 8 49 #define SH73A0_CLK_SCIFA5 7 50 #define SH73A0_CLK_SCIFB 6 51 #define SH73A0_CLK_MSIOF2 5 52 #define SH73A0_CLK_SCIFA0 4 53 #define SH73A0_CLK_SCIFA1 3 54 #define SH73A0_CLK_SCIFA2 2 55 #define SH73A0_CLK_SCIFA3 1 56 #define SH73A0_CLK_SCIFA4 0 57 58 /* MSTP3 */ 59 #define SH73A0_CLK_SCIFA6 31 60 #define SH73A0_CLK_CMT1 29 61 #define SH73A0_CLK_FSI 28 62 #define SH73A0_CLK_IRDA 25 63 #define SH73A0_CLK_IIC1 23 64 #define SH73A0_CLK_USB 22 65 #define SH73A0_CLK_FLCTL 15 66 #define SH73A0_CLK_SDHI0 14 67 #define SH73A0_CLK_SDHI1 13 68 #define SH73A0_CLK_MMCIF0 12 69 #define SH73A0_CLK_SDHI2 11 70 #define SH73A0_CLK_TPU0 4 71 #define SH73A0_CLK_TPU1 3 72 #define SH73A0_CLK_TPU2 2 73 #define SH73A0_CLK_TPU3 1 74 #define SH73A0_CLK_TPU4 0 75 76 /* MSTP4 */ 77 #define SH73A0_CLK_IIC3 11 78 #define SH73A0_CLK_IIC4 10 79 #define SH73A0_CLK_KEYSC 3 80 81 /* MSTP5 */ 82 #define SH73A0_CLK_INTCA0 8 83 84 #endif 85