1 /* $NetBSD: r8a779a0-cpg-mssr.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 #ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ 8 #define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ 9 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12 /* r8a779A0 CPG Core Clocks */ 13 #define R8A779A0_CLK_Z0 0 14 #define R8A779A0_CLK_ZX 1 15 #define R8A779A0_CLK_Z1 2 16 #define R8A779A0_CLK_ZR 3 17 #define R8A779A0_CLK_ZS 4 18 #define R8A779A0_CLK_ZT 5 19 #define R8A779A0_CLK_ZTR 6 20 #define R8A779A0_CLK_S1D1 7 21 #define R8A779A0_CLK_S1D2 8 22 #define R8A779A0_CLK_S1D4 9 23 #define R8A779A0_CLK_S1D8 10 24 #define R8A779A0_CLK_S1D12 11 25 #define R8A779A0_CLK_S3D1 12 26 #define R8A779A0_CLK_S3D2 13 27 #define R8A779A0_CLK_S3D4 14 28 #define R8A779A0_CLK_LB 15 29 #define R8A779A0_CLK_CP 16 30 #define R8A779A0_CLK_CL 17 31 #define R8A779A0_CLK_CL16MCK 18 32 #define R8A779A0_CLK_ZB30 19 33 #define R8A779A0_CLK_ZB30D2 20 34 #define R8A779A0_CLK_ZB30D4 21 35 #define R8A779A0_CLK_ZB31 22 36 #define R8A779A0_CLK_ZB31D2 23 37 #define R8A779A0_CLK_ZB31D4 24 38 #define R8A779A0_CLK_SD0H 25 39 #define R8A779A0_CLK_SD0 26 40 #define R8A779A0_CLK_RPC 27 41 #define R8A779A0_CLK_RPCD2 28 42 #define R8A779A0_CLK_MSO 29 43 #define R8A779A0_CLK_CANFD 30 44 #define R8A779A0_CLK_CSI0 31 45 #define R8A779A0_CLK_FRAY 32 46 #define R8A779A0_CLK_DSI 33 47 #define R8A779A0_CLK_VIP 34 48 #define R8A779A0_CLK_ADGH 35 49 #define R8A779A0_CLK_CNNDSP 36 50 #define R8A779A0_CLK_ICU 37 51 #define R8A779A0_CLK_ICUD2 38 52 #define R8A779A0_CLK_VCBUS 39 53 #define R8A779A0_CLK_CBFUSA 40 54 #define R8A779A0_CLK_R 41 55 #define R8A779A0_CLK_OSC 42 56 57 #endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */ 58