1 /* $NetBSD: r8a77990-cpg-mssr.h,v 1.1.1.1 2018/06/27 16:27:08 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 #ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ 8 #define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ 9 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12 /* r8a77990 CPG Core Clocks */ 13 #define R8A77990_CLK_Z2 0 14 #define R8A77990_CLK_ZR 1 15 #define R8A77990_CLK_ZG 2 16 #define R8A77990_CLK_ZTR 3 17 #define R8A77990_CLK_ZT 4 18 #define R8A77990_CLK_ZX 5 19 #define R8A77990_CLK_S0D1 6 20 #define R8A77990_CLK_S0D3 7 21 #define R8A77990_CLK_S0D6 8 22 #define R8A77990_CLK_S0D12 9 23 #define R8A77990_CLK_S0D24 10 24 #define R8A77990_CLK_S1D1 11 25 #define R8A77990_CLK_S1D2 12 26 #define R8A77990_CLK_S1D4 13 27 #define R8A77990_CLK_S2D1 14 28 #define R8A77990_CLK_S2D2 15 29 #define R8A77990_CLK_S2D4 16 30 #define R8A77990_CLK_S3D1 17 31 #define R8A77990_CLK_S3D2 18 32 #define R8A77990_CLK_S3D4 19 33 #define R8A77990_CLK_S0D6C 20 34 #define R8A77990_CLK_S3D1C 21 35 #define R8A77990_CLK_S3D2C 22 36 #define R8A77990_CLK_S3D4C 23 37 #define R8A77990_CLK_LB 24 38 #define R8A77990_CLK_CL 25 39 #define R8A77990_CLK_ZB3 26 40 #define R8A77990_CLK_ZB3D2 27 41 #define R8A77990_CLK_CR 28 42 #define R8A77990_CLK_CRD2 29 43 #define R8A77990_CLK_SD0H 30 44 #define R8A77990_CLK_SD0 31 45 #define R8A77990_CLK_SD1H 32 46 #define R8A77990_CLK_SD1 33 47 #define R8A77990_CLK_SD3H 34 48 #define R8A77990_CLK_SD3 35 49 #define R8A77990_CLK_RPC 36 50 #define R8A77990_CLK_RPCD2 37 51 #define R8A77990_CLK_ZA2 38 52 #define R8A77990_CLK_ZA8 39 53 #define R8A77990_CLK_Z2D 40 54 #define R8A77990_CLK_CANFD 41 55 #define R8A77990_CLK_MSO 42 56 #define R8A77990_CLK_R 43 57 #define R8A77990_CLK_OSC 44 58 #define R8A77990_CLK_LV0 45 59 #define R8A77990_CLK_LV1 46 60 #define R8A77990_CLK_CSI0 47 61 #define R8A77990_CLK_CP 48 62 #define R8A77990_CLK_CPEX 49 63 64 #endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ 65