1 /* $NetBSD: r8a77970-cpg-mssr.h,v 1.1.1.2 2019/01/22 14:57:02 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0+ 4 * 5 * Copyright (C) 2016 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 #ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 9 #define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 10 11 #include <dt-bindings/clock/renesas-cpg-mssr.h> 12 13 /* r8a77970 CPG Core Clocks */ 14 #define R8A77970_CLK_Z2 0 15 #define R8A77970_CLK_ZR 1 16 #define R8A77970_CLK_ZTR 2 17 #define R8A77970_CLK_ZTRD2 3 18 #define R8A77970_CLK_ZT 4 19 #define R8A77970_CLK_ZX 5 20 #define R8A77970_CLK_S1D1 6 21 #define R8A77970_CLK_S1D2 7 22 #define R8A77970_CLK_S1D4 8 23 #define R8A77970_CLK_S2D1 9 24 #define R8A77970_CLK_S2D2 10 25 #define R8A77970_CLK_S2D4 11 26 #define R8A77970_CLK_LB 12 27 #define R8A77970_CLK_CL 13 28 #define R8A77970_CLK_ZB3 14 29 #define R8A77970_CLK_ZB3D2 15 30 #define R8A77970_CLK_DDR 16 31 #define R8A77970_CLK_CR 17 32 #define R8A77970_CLK_CRD2 18 33 #define R8A77970_CLK_SD0H 19 34 #define R8A77970_CLK_SD0 20 35 #define R8A77970_CLK_RPC 21 36 #define R8A77970_CLK_RPCD2 22 37 #define R8A77970_CLK_MSO 23 38 #define R8A77970_CLK_CANFD 24 39 #define R8A77970_CLK_CSI0 25 40 #define R8A77970_CLK_FRAY 26 41 #define R8A77970_CLK_CP 27 42 #define R8A77970_CLK_CPEX 28 43 #define R8A77970_CLK_R 29 44 #define R8A77970_CLK_OSC 30 45 46 #endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ 47