1 /* $NetBSD: r8a7794-cpg-mssr.h,v 1.1.1.2 2019/01/22 14:57:02 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0+ 4 * 5 * Copyright (C) 2015 Renesas Electronics Corp. 6 */ 7 8 #ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ 9 #define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ 10 11 #include <dt-bindings/clock/renesas-cpg-mssr.h> 12 13 /* r8a7794 CPG Core Clocks */ 14 #define R8A7794_CLK_Z2 0 15 #define R8A7794_CLK_ZG 1 16 #define R8A7794_CLK_ZTR 2 17 #define R8A7794_CLK_ZTRD2 3 18 #define R8A7794_CLK_ZT 4 19 #define R8A7794_CLK_ZX 5 20 #define R8A7794_CLK_ZS 6 21 #define R8A7794_CLK_HP 7 22 #define R8A7794_CLK_I 8 23 #define R8A7794_CLK_B 9 24 #define R8A7794_CLK_LB 10 25 #define R8A7794_CLK_P 11 26 #define R8A7794_CLK_CL 12 27 #define R8A7794_CLK_CP 13 28 #define R8A7794_CLK_M2 14 29 #define R8A7794_CLK_ADSP 15 30 #define R8A7794_CLK_ZB3 16 31 #define R8A7794_CLK_ZB3D2 17 32 #define R8A7794_CLK_DDR 18 33 #define R8A7794_CLK_SDH 19 34 #define R8A7794_CLK_SD0 20 35 #define R8A7794_CLK_SD2 21 36 #define R8A7794_CLK_SD3 22 37 #define R8A7794_CLK_MMC0 23 38 #define R8A7794_CLK_MP 24 39 #define R8A7794_CLK_QSPI 25 40 #define R8A7794_CLK_CPEX 26 41 #define R8A7794_CLK_RCAN 27 42 #define R8A7794_CLK_R 28 43 #define R8A7794_CLK_OSC 29 44 45 #endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */ 46