1 /* $NetBSD: r8a7792-clock.h,v 1.1.1.3 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright (C) 2016 Cogent Embedded, Inc. 6 */ 7 8 #ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ 9 #define __DT_BINDINGS_CLOCK_R8A7792_H__ 10 11 /* CPG */ 12 #define R8A7792_CLK_MAIN 0 13 #define R8A7792_CLK_PLL0 1 14 #define R8A7792_CLK_PLL1 2 15 #define R8A7792_CLK_PLL3 3 16 #define R8A7792_CLK_LB 4 17 #define R8A7792_CLK_QSPI 5 18 19 /* MSTP0 */ 20 #define R8A7792_CLK_MSIOF0 0 21 22 /* MSTP1 */ 23 #define R8A7792_CLK_JPU 6 24 #define R8A7792_CLK_TMU1 11 25 #define R8A7792_CLK_TMU3 21 26 #define R8A7792_CLK_TMU2 22 27 #define R8A7792_CLK_CMT0 24 28 #define R8A7792_CLK_TMU0 25 29 #define R8A7792_CLK_VSP1DU1 27 30 #define R8A7792_CLK_VSP1DU0 28 31 #define R8A7792_CLK_VSP1_SY 31 32 33 /* MSTP2 */ 34 #define R8A7792_CLK_MSIOF1 8 35 #define R8A7792_CLK_SYS_DMAC1 18 36 #define R8A7792_CLK_SYS_DMAC0 19 37 38 /* MSTP3 */ 39 #define R8A7792_CLK_TPU0 4 40 #define R8A7792_CLK_SDHI0 14 41 #define R8A7792_CLK_CMT1 29 42 43 /* MSTP4 */ 44 #define R8A7792_CLK_IRQC 7 45 #define R8A7792_CLK_INTC_SYS 8 46 47 /* MSTP5 */ 48 #define R8A7792_CLK_AUDIO_DMAC0 2 49 #define R8A7792_CLK_THERMAL 22 50 #define R8A7792_CLK_PWM 23 51 52 /* MSTP7 */ 53 #define R8A7792_CLK_HSCIF1 16 54 #define R8A7792_CLK_HSCIF0 17 55 #define R8A7792_CLK_SCIF3 18 56 #define R8A7792_CLK_SCIF2 19 57 #define R8A7792_CLK_SCIF1 20 58 #define R8A7792_CLK_SCIF0 21 59 #define R8A7792_CLK_DU1 23 60 #define R8A7792_CLK_DU0 24 61 62 /* MSTP8 */ 63 #define R8A7792_CLK_VIN5 4 64 #define R8A7792_CLK_VIN4 5 65 #define R8A7792_CLK_VIN3 8 66 #define R8A7792_CLK_VIN2 9 67 #define R8A7792_CLK_VIN1 10 68 #define R8A7792_CLK_VIN0 11 69 #define R8A7792_CLK_ETHERAVB 12 70 71 /* MSTP9 */ 72 #define R8A7792_CLK_GPIO7 4 73 #define R8A7792_CLK_GPIO6 5 74 #define R8A7792_CLK_GPIO5 7 75 #define R8A7792_CLK_GPIO4 8 76 #define R8A7792_CLK_GPIO3 9 77 #define R8A7792_CLK_GPIO2 10 78 #define R8A7792_CLK_GPIO1 11 79 #define R8A7792_CLK_GPIO0 12 80 #define R8A7792_CLK_GPIO11 13 81 #define R8A7792_CLK_GPIO10 14 82 #define R8A7792_CLK_CAN1 15 83 #define R8A7792_CLK_CAN0 16 84 #define R8A7792_CLK_QSPI_MOD 17 85 #define R8A7792_CLK_GPIO9 19 86 #define R8A7792_CLK_GPIO8 21 87 #define R8A7792_CLK_I2C5 25 88 #define R8A7792_CLK_IICDVFS 26 89 #define R8A7792_CLK_I2C4 27 90 #define R8A7792_CLK_I2C3 28 91 #define R8A7792_CLK_I2C2 29 92 #define R8A7792_CLK_I2C1 30 93 #define R8A7792_CLK_I2C0 31 94 95 /* MSTP10 */ 96 #define R8A7792_CLK_SSI_ALL 5 97 #define R8A7792_CLK_SSI4 11 98 #define R8A7792_CLK_SSI3 12 99 100 #endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ 101