1 /* $NetBSD: r8a7790-cpg-mssr.h,v 1.1.1.2 2019/01/22 14:57:01 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0+ 4 * 5 * Copyright (C) 2015 Renesas Electronics Corp. 6 */ 7 8 #ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ 9 #define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ 10 11 #include <dt-bindings/clock/renesas-cpg-mssr.h> 12 13 /* r8a7790 CPG Core Clocks */ 14 #define R8A7790_CLK_Z 0 15 #define R8A7790_CLK_Z2 1 16 #define R8A7790_CLK_ZG 2 17 #define R8A7790_CLK_ZTR 3 18 #define R8A7790_CLK_ZTRD2 4 19 #define R8A7790_CLK_ZT 5 20 #define R8A7790_CLK_ZX 6 21 #define R8A7790_CLK_ZS 7 22 #define R8A7790_CLK_HP 8 23 #define R8A7790_CLK_I 9 24 #define R8A7790_CLK_B 10 25 #define R8A7790_CLK_LB 11 26 #define R8A7790_CLK_P 12 27 #define R8A7790_CLK_CL 13 28 #define R8A7790_CLK_M2 14 29 #define R8A7790_CLK_ADSP 15 30 #define R8A7790_CLK_IMP 16 31 #define R8A7790_CLK_ZB3 17 32 #define R8A7790_CLK_ZB3D2 18 33 #define R8A7790_CLK_DDR 19 34 #define R8A7790_CLK_SDH 20 35 #define R8A7790_CLK_SD0 21 36 #define R8A7790_CLK_SD1 22 37 #define R8A7790_CLK_SD2 23 38 #define R8A7790_CLK_SD3 24 39 #define R8A7790_CLK_MMC0 25 40 #define R8A7790_CLK_MMC1 26 41 #define R8A7790_CLK_MP 27 42 #define R8A7790_CLK_SSP 28 43 #define R8A7790_CLK_SSPRS 29 44 #define R8A7790_CLK_QSPI 30 45 #define R8A7790_CLK_CP 31 46 #define R8A7790_CLK_RCAN 32 47 #define R8A7790_CLK_R 33 48 #define R8A7790_CLK_OSC 34 49 50 #endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */ 51