1 /* $NetBSD: r8a7790-clock.h,v 1.1.1.3 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright 2013 Ideas On Board SPRL 6 */ 7 8 #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ 9 #define __DT_BINDINGS_CLOCK_R8A7790_H__ 10 11 /* CPG */ 12 #define R8A7790_CLK_MAIN 0 13 #define R8A7790_CLK_PLL0 1 14 #define R8A7790_CLK_PLL1 2 15 #define R8A7790_CLK_PLL3 3 16 #define R8A7790_CLK_LB 4 17 #define R8A7790_CLK_QSPI 5 18 #define R8A7790_CLK_SDH 6 19 #define R8A7790_CLK_SD0 7 20 #define R8A7790_CLK_SD1 8 21 #define R8A7790_CLK_Z 9 22 #define R8A7790_CLK_RCAN 10 23 #define R8A7790_CLK_ADSP 11 24 25 /* MSTP0 */ 26 #define R8A7790_CLK_MSIOF0 0 27 28 /* MSTP1 */ 29 #define R8A7790_CLK_VCP1 0 30 #define R8A7790_CLK_VCP0 1 31 #define R8A7790_CLK_VPC1 2 32 #define R8A7790_CLK_VPC0 3 33 #define R8A7790_CLK_JPU 6 34 #define R8A7790_CLK_SSP1 9 35 #define R8A7790_CLK_TMU1 11 36 #define R8A7790_CLK_3DG 12 37 #define R8A7790_CLK_2DDMAC 15 38 #define R8A7790_CLK_FDP1_2 17 39 #define R8A7790_CLK_FDP1_1 18 40 #define R8A7790_CLK_FDP1_0 19 41 #define R8A7790_CLK_TMU3 21 42 #define R8A7790_CLK_TMU2 22 43 #define R8A7790_CLK_CMT0 24 44 #define R8A7790_CLK_TMU0 25 45 #define R8A7790_CLK_VSP1_DU1 27 46 #define R8A7790_CLK_VSP1_DU0 28 47 #define R8A7790_CLK_VSP1_R 30 48 #define R8A7790_CLK_VSP1_S 31 49 50 /* MSTP2 */ 51 #define R8A7790_CLK_SCIFA2 2 52 #define R8A7790_CLK_SCIFA1 3 53 #define R8A7790_CLK_SCIFA0 4 54 #define R8A7790_CLK_MSIOF2 5 55 #define R8A7790_CLK_SCIFB0 6 56 #define R8A7790_CLK_SCIFB1 7 57 #define R8A7790_CLK_MSIOF1 8 58 #define R8A7790_CLK_MSIOF3 15 59 #define R8A7790_CLK_SCIFB2 16 60 #define R8A7790_CLK_SYS_DMAC1 18 61 #define R8A7790_CLK_SYS_DMAC0 19 62 63 /* MSTP3 */ 64 #define R8A7790_CLK_IIC2 0 65 #define R8A7790_CLK_TPU0 4 66 #define R8A7790_CLK_MMCIF1 5 67 #define R8A7790_CLK_SCIF2 10 68 #define R8A7790_CLK_SDHI3 11 69 #define R8A7790_CLK_SDHI2 12 70 #define R8A7790_CLK_SDHI1 13 71 #define R8A7790_CLK_SDHI0 14 72 #define R8A7790_CLK_MMCIF0 15 73 #define R8A7790_CLK_IIC0 18 74 #define R8A7790_CLK_PCIEC 19 75 #define R8A7790_CLK_IIC1 23 76 #define R8A7790_CLK_SSUSB 28 77 #define R8A7790_CLK_CMT1 29 78 #define R8A7790_CLK_USBDMAC0 30 79 #define R8A7790_CLK_USBDMAC1 31 80 81 /* MSTP4 */ 82 #define R8A7790_CLK_IRQC 7 83 #define R8A7790_CLK_INTC_SYS 8 84 85 /* MSTP5 */ 86 #define R8A7790_CLK_AUDIO_DMAC1 1 87 #define R8A7790_CLK_AUDIO_DMAC0 2 88 #define R8A7790_CLK_ADSP_MOD 6 89 #define R8A7790_CLK_THERMAL 22 90 #define R8A7790_CLK_PWM 23 91 92 /* MSTP7 */ 93 #define R8A7790_CLK_EHCI 3 94 #define R8A7790_CLK_HSUSB 4 95 #define R8A7790_CLK_HSCIF1 16 96 #define R8A7790_CLK_HSCIF0 17 97 #define R8A7790_CLK_SCIF1 20 98 #define R8A7790_CLK_SCIF0 21 99 #define R8A7790_CLK_DU2 22 100 #define R8A7790_CLK_DU1 23 101 #define R8A7790_CLK_DU0 24 102 #define R8A7790_CLK_LVDS1 25 103 #define R8A7790_CLK_LVDS0 26 104 105 /* MSTP8 */ 106 #define R8A7790_CLK_MLB 2 107 #define R8A7790_CLK_VIN3 8 108 #define R8A7790_CLK_VIN2 9 109 #define R8A7790_CLK_VIN1 10 110 #define R8A7790_CLK_VIN0 11 111 #define R8A7790_CLK_ETHERAVB 12 112 #define R8A7790_CLK_ETHER 13 113 #define R8A7790_CLK_SATA1 14 114 #define R8A7790_CLK_SATA0 15 115 116 /* MSTP9 */ 117 #define R8A7790_CLK_GPIO5 7 118 #define R8A7790_CLK_GPIO4 8 119 #define R8A7790_CLK_GPIO3 9 120 #define R8A7790_CLK_GPIO2 10 121 #define R8A7790_CLK_GPIO1 11 122 #define R8A7790_CLK_GPIO0 12 123 #define R8A7790_CLK_RCAN1 15 124 #define R8A7790_CLK_RCAN0 16 125 #define R8A7790_CLK_QSPI_MOD 17 126 #define R8A7790_CLK_IICDVFS 26 127 #define R8A7790_CLK_I2C3 28 128 #define R8A7790_CLK_I2C2 29 129 #define R8A7790_CLK_I2C1 30 130 #define R8A7790_CLK_I2C0 31 131 132 /* MSTP10 */ 133 #define R8A7790_CLK_SSI_ALL 5 134 #define R8A7790_CLK_SSI9 6 135 #define R8A7790_CLK_SSI8 7 136 #define R8A7790_CLK_SSI7 8 137 #define R8A7790_CLK_SSI6 9 138 #define R8A7790_CLK_SSI5 10 139 #define R8A7790_CLK_SSI4 11 140 #define R8A7790_CLK_SSI3 12 141 #define R8A7790_CLK_SSI2 13 142 #define R8A7790_CLK_SSI1 14 143 #define R8A7790_CLK_SSI0 15 144 #define R8A7790_CLK_SCU_ALL 17 145 #define R8A7790_CLK_SCU_DVC1 18 146 #define R8A7790_CLK_SCU_DVC0 19 147 #define R8A7790_CLK_SCU_CTU1_MIX1 20 148 #define R8A7790_CLK_SCU_CTU0_MIX0 21 149 #define R8A7790_CLK_SCU_SRC9 22 150 #define R8A7790_CLK_SCU_SRC8 23 151 #define R8A7790_CLK_SCU_SRC7 24 152 #define R8A7790_CLK_SCU_SRC6 25 153 #define R8A7790_CLK_SCU_SRC5 26 154 #define R8A7790_CLK_SCU_SRC4 27 155 #define R8A7790_CLK_SCU_SRC3 28 156 #define R8A7790_CLK_SCU_SRC2 29 157 #define R8A7790_CLK_SCU_SRC1 30 158 #define R8A7790_CLK_SCU_SRC0 31 159 160 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ 161